From a8a50641f6aae8d85f0438d8ebcd2ab74b8fffff Mon Sep 17 00:00:00 2001 From: Connor McLaughlin Date: Thu, 9 Sep 2021 17:36:36 +1000 Subject: [PATCH] R5900: Fix LWL not sign extending in interpreter This was zero extending because of the implicit promotion from signed->unsigned, causing incorrect high bits in the GPR. Funnily enough, this was noted in the source, but implemented incorrectly. --- pcsx2/R5900OpcodeImpl.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/pcsx2/R5900OpcodeImpl.cpp b/pcsx2/R5900OpcodeImpl.cpp index 4bf4c1e801..faa61baa50 100644 --- a/pcsx2/R5900OpcodeImpl.cpp +++ b/pcsx2/R5900OpcodeImpl.cpp @@ -595,13 +595,13 @@ void LWL() s32 addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_; u32 shift = addr & 3; - // ensure the compiler does correct sign extension into 64 bits by using s32 - s32 mem = memRead32(addr & ~3); + u32 mem = memRead32(addr & ~3); if (!_Rt_) return; - cpuRegs.GPR.r[_Rt_].SD[0] = (cpuRegs.GPR.r[_Rt_].SL[0] & LWL_MASK[shift]) | - (mem << LWL_SHIFT[shift]); + // ensure the compiler does correct sign extension into 64 bits by using s32 + cpuRegs.GPR.r[_Rt_].SD[0] = (s32)((cpuRegs.GPR.r[_Rt_].UL[0] & LWL_MASK[shift]) | + (mem << LWL_SHIFT[shift])); /* Mem = 1234. Reg = abcd