mirror of https://github.com/PCSX2/pcsx2.git
microVU:
- Non-functional change... just storing some IR info I'll need to use later. git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1303 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
cottonvibes
parent
a336e6b277
commit
a8266a48d8
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@ -23,35 +23,28 @@
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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// FMAC1 - Normal FMAC Opcodes
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// Helper Macros
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//------------------------------------------------------------------
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#define aReg(x) mVUregs.VF[x]
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#define aReg(x) mVUregs.VF[x]
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#define bReg(x, y) mVUregsTemp.VFreg[y] = x; mVUregsTemp.VF[y]
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#define aMax(x, y) ((x > y) ? x : y)
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#define analyzeReg1(reg) { \
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if (reg) { \
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if (_X) { mVUstall = aMax(mVUstall, aReg(reg).x); } \
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if (_Y) { mVUstall = aMax(mVUstall, aReg(reg).y); } \
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if (_Z) { mVUstall = aMax(mVUstall, aReg(reg).z); } \
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if (_W) { mVUstall = aMax(mVUstall, aReg(reg).w); } \
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} \
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// Read a VF reg by upper op
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#define analyzeReg1(xReg, vfRead) { \
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if (xReg) { \
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if (_X) { mVUstall = aMax(mVUstall, aReg(xReg).x); vfRead.reg = xReg; vfRead.x = 1; } \
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if (_Y) { mVUstall = aMax(mVUstall, aReg(xReg).y); vfRead.reg = xReg; vfRead.y = 1; } \
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if (_Z) { mVUstall = aMax(mVUstall, aReg(xReg).z); vfRead.reg = xReg; vfRead.z = 1; } \
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if (_W) { mVUstall = aMax(mVUstall, aReg(xReg).w); vfRead.reg = xReg; vfRead.w = 1; } \
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} \
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}
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#define analyzeReg2(reg, isLowOp) { \
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if (reg) { \
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if (_X) { bReg(reg, isLowOp).x = 4; } \
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if (_Y) { bReg(reg, isLowOp).y = 4; } \
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if (_Z) { bReg(reg, isLowOp).z = 4; } \
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if (_W) { bReg(reg, isLowOp).w = 4; } \
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} \
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}
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#define analyzeReg1b(reg) { \
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if (reg) { \
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analyzeReg1(reg); \
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if (mVUregsTemp.VFreg[0] == reg) { \
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// Read a VF reg by lower op
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#define analyzeReg1b(xReg, vfRead) { \
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if (xReg) { \
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analyzeReg1(xReg, vfRead); \
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if (mVUregsTemp.VFreg[0] == xReg) { \
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if ((mVUregsTemp.VF[0].x && _X) \
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|| (mVUregsTemp.VF[0].y && _Y) \
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|| (mVUregsTemp.VF[0].z && _Z) \
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@ -61,11 +54,115 @@
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} \
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}
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// Write to a VF reg
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#define analyzeReg2(xReg, vfWrite, isLowOp) { \
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if (xReg) { \
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if (_X) { bReg(xReg, isLowOp).x = 4; vfWrite.reg = xReg; vfWrite.x = 4; } \
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if (_Y) { bReg(xReg, isLowOp).y = 4; vfWrite.reg = xReg; vfWrite.y = 4; } \
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if (_Z) { bReg(xReg, isLowOp).z = 4; vfWrite.reg = xReg; vfWrite.z = 4; } \
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if (_W) { bReg(xReg, isLowOp).w = 4; vfWrite.reg = xReg; vfWrite.w = 4; } \
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} \
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}
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// Read a VF reg (BC opcodes)
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#define analyzeReg3(xReg, vfRead) { \
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if (xReg) { \
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if (_bc_x) { mVUstall = aMax(mVUstall, aReg(xReg).x); vfRead.reg = xReg; vfRead.x = 1; } \
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else if (_bc_y) { mVUstall = aMax(mVUstall, aReg(xReg).y); vfRead.reg = xReg; vfRead.y = 1; } \
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else if (_bc_z) { mVUstall = aMax(mVUstall, aReg(xReg).z); vfRead.reg = xReg; vfRead.z = 1; } \
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else { mVUstall = aMax(mVUstall, aReg(xReg).w); vfRead.reg = xReg; vfRead.w = 1; } \
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} \
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}
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// For Clip Opcode
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#define analyzeReg4(xReg, vfRead) { \
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if (xReg) { \
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mVUstall = aMax(mVUstall, aReg(xReg).w); \
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vfRead.reg = xReg; vfRead.w = 1; \
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} \
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}
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// Read VF reg (FsF/FtF)
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#define analyzeReg5(xReg, fxf, vfRead) { \
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if (xReg) { \
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switch (fxf) { \
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case 0: mVUstall = aMax(mVUstall, aReg(xReg).x); vfRead.reg = xReg; vfRead.x = 1; break; \
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case 1: mVUstall = aMax(mVUstall, aReg(xReg).y); vfRead.reg = xReg; vfRead.y = 1; break; \
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case 2: mVUstall = aMax(mVUstall, aReg(xReg).z); vfRead.reg = xReg; vfRead.z = 1; break; \
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case 3: mVUstall = aMax(mVUstall, aReg(xReg).w); vfRead.reg = xReg; vfRead.w = 1; break; \
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} \
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if (mVUregsTemp.VFreg[0] == xReg) { \
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if ((mVUregsTemp.VF[0].x && (fxf == 0)) \
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|| (mVUregsTemp.VF[0].y && (fxf == 1)) \
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|| (mVUregsTemp.VF[0].z && (fxf == 2)) \
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|| (mVUregsTemp.VF[0].w && (fxf == 3))) \
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{ mVUinfo.swapOps = 1; } \
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} \
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} \
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}
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// Flips xyzw stalls to yzwx (MR32 Opcode)
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#define analyzeReg6(xReg, vfRead) { \
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if (xReg) { \
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if (_X) { mVUstall = aMax(mVUstall, aReg(xReg).y); vfRead.reg = xReg; vfRead.y = 1; } \
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if (_Y) { mVUstall = aMax(mVUstall, aReg(xReg).z); vfRead.reg = xReg; vfRead.z = 1; } \
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if (_Z) { mVUstall = aMax(mVUstall, aReg(xReg).w); vfRead.reg = xReg; vfRead.w = 1; } \
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if (_W) { mVUstall = aMax(mVUstall, aReg(xReg).x); vfRead.reg = xReg; vfRead.x = 1; } \
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if (mVUregsTemp.VFreg[0] == xReg) { \
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if ((mVUregsTemp.VF[0].y && _X) \
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|| (mVUregsTemp.VF[0].z && _Y) \
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|| (mVUregsTemp.VF[0].w && _Z) \
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|| (mVUregsTemp.VF[0].x && _W)) \
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{ mVUinfo.swapOps = 1; } \
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} \
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} \
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}
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// Reading a VI reg
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#define analyzeVIreg1(xReg, viRead) { \
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if (xReg) { \
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mVUstall = aMax(mVUstall, mVUregs.VI[xReg]); \
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viRead.reg = xReg; viRead.used = 1; \
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} \
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}
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// Writing to a VI reg
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#define analyzeVIreg2(xReg, viWrite, aCycles) { \
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if (xReg) { \
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mVUregsTemp.VIreg = xReg; \
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mVUregsTemp.VI = aCycles; \
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mVUlow.writesVI = 1; \
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mVU->VIbackup[0] = xReg; \
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viWrite.reg = xReg; \
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viWrite.used = aCycles; \
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} \
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}
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// Writing to a VI reg (FSxxx, FMxxx, FCxxx opcodes)
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#define analyzeVIreg3(xReg, viWrite, aCycles) { \
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if (xReg) { \
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mVUregsTemp.VIreg = xReg; \
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mVUregsTemp.VI = aCycles; \
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viWrite.reg = xReg; \
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viWrite.used = aCycles; \
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} \
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}
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#define analyzeQreg(x) { mVUregsTemp.q = x; mVUstall = aMax(mVUstall, mVUregs.q); }
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#define analyzePreg(x) { mVUregsTemp.p = x; mVUstall = aMax(mVUstall, ((mVUregs.p) ? (mVUregs.p - 1) : 0)); }
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#define analyzeRreg() { mVUregsTemp.r = 1; }
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#define analyzeXGkick1() { mVUstall = aMax(mVUstall, mVUregs.xgkick); }
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#define analyzeXGkick2(x) { mVUregsTemp.xgkick = x; }
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//------------------------------------------------------------------
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// FMAC1 - Normal FMAC Opcodes
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//------------------------------------------------------------------
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microVUt(void) mVUanalyzeFMAC1(mV, int Fd, int Fs, int Ft) {
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sFLAG.doFlag = 1;
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analyzeReg1(Fs);
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analyzeReg1(Ft);
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analyzeReg2(Fd, 0);
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analyzeReg1(Fs, mVUup.VF_read[0]);
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analyzeReg1(Ft, mVUup.VF_read[1]);
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analyzeReg2(Fd, mVUup.VF_write, 0);
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}
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//------------------------------------------------------------------
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@ -73,121 +170,66 @@ microVUt(void) mVUanalyzeFMAC1(mV, int Fd, int Fs, int Ft) {
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//------------------------------------------------------------------
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microVUt(void) mVUanalyzeFMAC2(mV, int Fs, int Ft) {
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analyzeReg1(Fs);
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analyzeReg2(Ft, 0);
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analyzeReg1(Fs, mVUup.VF_read[0]);
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analyzeReg2(Ft, mVUup.VF_write, 0);
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}
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//------------------------------------------------------------------
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// FMAC3 - BC(xyzw) FMAC Opcodes
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//------------------------------------------------------------------
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#define analyzeReg3(reg) { \
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if (reg) { \
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if (_bc_x) { mVUstall = aMax(mVUstall, aReg(reg).x); } \
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else if (_bc_y) { mVUstall = aMax(mVUstall, aReg(reg).y); } \
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else if (_bc_z) { mVUstall = aMax(mVUstall, aReg(reg).z); } \
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else { mVUstall = aMax(mVUstall, aReg(reg).w); } \
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} \
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}
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microVUt(void) mVUanalyzeFMAC3(mV, int Fd, int Fs, int Ft) {
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sFLAG.doFlag = 1;
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analyzeReg1(Fs);
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analyzeReg3(Ft);
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analyzeReg2(Fd, 0);
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analyzeReg1(Fs, mVUup.VF_read[0]);
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analyzeReg3(Ft, mVUup.VF_read[1]);
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analyzeReg2(Fd, mVUup.VF_write, 0);
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}
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//------------------------------------------------------------------
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// FMAC4 - Clip FMAC Opcode
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//------------------------------------------------------------------
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#define analyzeReg4(reg) { \
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if (reg) { mVUstall = aMax(mVUstall, aReg(reg).w); } \
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}
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microVUt(void) mVUanalyzeFMAC4(mV, int Fs, int Ft) {
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cFLAG.doFlag = 1;
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analyzeReg1(Fs);
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analyzeReg4(Ft);
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analyzeReg1(Fs, mVUup.VF_read[0]);
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analyzeReg4(Ft, mVUup.VF_read[1]);
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}
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//------------------------------------------------------------------
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// IALU - IALU Opcodes
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//------------------------------------------------------------------
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#define analyzeVIreg1(reg) { if (reg) { mVUstall = aMax(mVUstall, mVUregs.VI[reg]); } }
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#define analyzeVIreg2(reg, aCycles) { if (reg) { mVUregsTemp.VIreg = reg; mVUregsTemp.VI = aCycles; mVUlow.writesVI = 1; mVU->VIbackup[0] = reg; } }
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#define analyzeVIreg3(reg, aCycles) { if (reg) { mVUregsTemp.VIreg = reg; mVUregsTemp.VI = aCycles; } }
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microVUt(void) mVUanalyzeIALU1(mV, int Id, int Is, int It) {
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if (!Id) { mVUlow.isNOP = 1; }
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analyzeVIreg1(Is);
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analyzeVIreg1(It);
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analyzeVIreg2(Id, 1);
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analyzeVIreg1(Is, mVUlow.VI_read[0]);
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analyzeVIreg1(It, mVUlow.VI_read[1]);
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analyzeVIreg2(Id, mVUlow.VI_write, 1);
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}
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microVUt(void) mVUanalyzeIALU2(mV, int Is, int It) {
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if (!It) { mVUlow.isNOP = 1; }
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analyzeVIreg1(Is);
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analyzeVIreg2(It, 1);
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analyzeVIreg1(Is, mVUlow.VI_read[0]);
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analyzeVIreg2(It, mVUlow.VI_write, 1);
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}
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//------------------------------------------------------------------
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// MR32 - MR32 Opcode
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//------------------------------------------------------------------
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// Flips xyzw stalls to yzwx
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#define analyzeReg6(reg) { \
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if (reg) { \
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if (_X) { mVUstall = aMax(mVUstall, aReg(reg).y); } \
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if (_Y) { mVUstall = aMax(mVUstall, aReg(reg).z); } \
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if (_Z) { mVUstall = aMax(mVUstall, aReg(reg).w); } \
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if (_W) { mVUstall = aMax(mVUstall, aReg(reg).x); } \
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if (mVUregsTemp.VFreg[0] == reg) { \
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if ((mVUregsTemp.VF[0].y && _X) \
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|| (mVUregsTemp.VF[0].z && _Y) \
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|| (mVUregsTemp.VF[0].w && _Z) \
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|| (mVUregsTemp.VF[0].x && _W)) \
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{ mVUinfo.swapOps = 1; } \
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} \
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} \
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}
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microVUt(void) mVUanalyzeMR32(mV, int Fs, int Ft) {
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if (!Ft) { mVUlow.isNOP = 1; }
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analyzeReg6(Fs);
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analyzeReg2(Ft, 1);
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analyzeReg6(Fs, mVUlow.VF_read[0]);
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analyzeReg2(Ft, mVUlow.VF_write, 1);
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}
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//------------------------------------------------------------------
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// FDIV - DIV/SQRT/RSQRT Opcodes
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//------------------------------------------------------------------
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#define analyzeReg5(reg, fxf) { \
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if (reg) { \
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switch (fxf) { \
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case 0: mVUstall = aMax(mVUstall, aReg(reg).x); break; \
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case 1: mVUstall = aMax(mVUstall, aReg(reg).y); break; \
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case 2: mVUstall = aMax(mVUstall, aReg(reg).z); break; \
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case 3: mVUstall = aMax(mVUstall, aReg(reg).w); break; \
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} \
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if (mVUregsTemp.VFreg[0] == reg) { \
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if ((mVUregsTemp.VF[0].x && (fxf == 0)) \
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|| (mVUregsTemp.VF[0].y && (fxf == 1)) \
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|| (mVUregsTemp.VF[0].z && (fxf == 2)) \
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|| (mVUregsTemp.VF[0].w && (fxf == 3))) \
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{ mVUinfo.swapOps = 1; } \
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} \
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} \
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}
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#define analyzeQreg(x) { mVUregsTemp.q = x; mVUstall = aMax(mVUstall, mVUregs.q); }
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#define analyzePreg(x) { mVUregsTemp.p = x; mVUstall = aMax(mVUstall, ((mVUregs.p) ? (mVUregs.p - 1) : 0)); }
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microVUt(void) mVUanalyzeFDIV(mV, int Fs, int Fsf, int Ft, int Ftf, u8 xCycles) {
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mVUprint("microVU: DIV Opcode");
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analyzeReg5(Fs, Fsf);
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analyzeReg5(Ft, Ftf);
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analyzeReg5(Fs, Fsf, mVUlow.VF_read[0]);
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analyzeReg5(Ft, Ftf, mVUlow.VF_read[1]);
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analyzeQreg(xCycles);
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}
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@ -197,13 +239,13 @@ microVUt(void) mVUanalyzeFDIV(mV, int Fs, int Fsf, int Ft, int Ftf, u8 xCycles)
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microVUt(void) mVUanalyzeEFU1(mV, int Fs, int Fsf, u8 xCycles) {
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mVUprint("microVU: EFU Opcode");
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analyzeReg5(Fs, Fsf);
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analyzeReg5(Fs, Fsf, mVUlow.VF_read[0]);
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analyzePreg(xCycles);
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}
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microVUt(void) mVUanalyzeEFU2(mV, int Fs, u8 xCycles) {
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mVUprint("microVU: EFU Opcode");
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analyzeReg1b(Fs);
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analyzeReg1b(Fs, mVUlow.VF_read[0]);
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analyzePreg(xCycles);
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}
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@ -213,7 +255,7 @@ microVUt(void) mVUanalyzeEFU2(mV, int Fs, u8 xCycles) {
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microVUt(void) mVUanalyzeMFP(mV, int Ft) {
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if (!Ft) { mVUlow.isNOP = 1; }
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analyzeReg2(Ft, 1);
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analyzeReg2(Ft, mVUlow.VF_write, 1);
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}
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//------------------------------------------------------------------
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@ -222,20 +264,19 @@ microVUt(void) mVUanalyzeMFP(mV, int Ft) {
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microVUt(void) mVUanalyzeMOVE(mV, int Fs, int Ft) {
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if (!Ft || (Ft == Fs)) { mVUlow.isNOP = 1; }
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analyzeReg1b(Fs);
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analyzeReg2(Ft, 1);
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analyzeReg1b(Fs, mVUlow.VF_read[0]);
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analyzeReg2 (Ft, mVUlow.VF_write, 1);
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}
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//------------------------------------------------------------------
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// LQx - LQ/LQD/LQI Opcodes
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//------------------------------------------------------------------
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microVUt(void) mVUanalyzeLQ(mV, int Ft, int Is, bool writeIs) {
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analyzeVIreg1(Is);
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analyzeReg2(Ft, 1);
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analyzeVIreg1(Is, mVUlow.VI_read[0]);
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analyzeReg2 (Ft, mVUlow.VF_write, 1);
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if (!Ft) { if (writeIs && Is) { mVUlow.noWriteVF = 1; } else { mVUlow.isNOP = 1; } }
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if (writeIs) { analyzeVIreg2(Is, 1); }
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if (writeIs) { analyzeVIreg2(Is, mVUlow.VI_write, 1); }
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}
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//------------------------------------------------------------------
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@ -243,25 +284,23 @@ microVUt(void) mVUanalyzeLQ(mV, int Ft, int Is, bool writeIs) {
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//------------------------------------------------------------------
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microVUt(void) mVUanalyzeSQ(mV, int Fs, int It, bool writeIt) {
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analyzeReg1b(Fs);
|
||||
analyzeVIreg1(It);
|
||||
if (writeIt) { analyzeVIreg2(It, 1); }
|
||||
analyzeReg1b (Fs, mVUlow.VF_read[0]);
|
||||
analyzeVIreg1(It, mVUlow.VI_read[0]);
|
||||
if (writeIt) { analyzeVIreg2(It, mVUlow.VI_write, 1); }
|
||||
}
|
||||
|
||||
//------------------------------------------------------------------
|
||||
// R*** - R Reg Opcodes
|
||||
//------------------------------------------------------------------
|
||||
|
||||
#define analyzeRreg() { mVUregsTemp.r = 1; }
|
||||
|
||||
microVUt(void) mVUanalyzeR1(mV, int Fs, int Fsf) {
|
||||
analyzeReg5(Fs, Fsf);
|
||||
analyzeReg5(Fs, Fsf, mVUlow.VF_read[0]);
|
||||
analyzeRreg();
|
||||
}
|
||||
|
||||
microVUt(void) mVUanalyzeR2(mV, int Ft, bool canBeNOP) {
|
||||
if (!Ft) { if (canBeNOP) { mVUlow.isNOP = 1; } else { mVUlow.noWriteVF = 1; } }
|
||||
analyzeReg2(Ft, 1);
|
||||
analyzeReg2(Ft, mVUlow.VF_write, 1);
|
||||
analyzeRreg();
|
||||
}
|
||||
|
||||
|
|
@ -280,7 +319,7 @@ microVUt(void) mVUanalyzeSflag(mV, int It) {
|
|||
// Do to stalls, it can only be set one instruction prior to the status flag read instruction
|
||||
// if we were guaranteed no-stalls were to happen, it could be set 4 instruction prior.
|
||||
}
|
||||
analyzeVIreg3(It, 1);
|
||||
analyzeVIreg3(It, mVUlow.VI_write, 1);
|
||||
}
|
||||
|
||||
microVUt(void) mVUanalyzeFSSET(mV) {
|
||||
|
|
@ -308,8 +347,8 @@ microVUt(void) mVUanalyzeMflag(mV, int Is, int It) {
|
|||
}
|
||||
iPC = curPC;
|
||||
}
|
||||
analyzeVIreg1(Is);
|
||||
analyzeVIreg3(It, 1);
|
||||
analyzeVIreg1(Is, mVUlow.VI_read[0]);
|
||||
analyzeVIreg3(It, mVUlow.VI_write, 1);
|
||||
}
|
||||
|
||||
//------------------------------------------------------------------
|
||||
|
|
@ -319,18 +358,15 @@ microVUt(void) mVUanalyzeMflag(mV, int Is, int It) {
|
|||
microVUt(void) mVUanalyzeCflag(mV, int It) {
|
||||
mVUinfo.swapOps = 1;
|
||||
if (mVUcount < 4) { mVUpBlock->pState.needExactMatch |= 0xf << (/*mVUcount +*/ 8); }
|
||||
analyzeVIreg3(It, 1);
|
||||
analyzeVIreg3(It, mVUlow.VI_write, 1);
|
||||
}
|
||||
|
||||
//------------------------------------------------------------------
|
||||
// XGkick
|
||||
//------------------------------------------------------------------
|
||||
|
||||
#define analyzeXGkick1() { mVUstall = aMax(mVUstall, mVUregs.xgkick); }
|
||||
#define analyzeXGkick2(x) { mVUregsTemp.xgkick = x; }
|
||||
|
||||
microVUt(void) mVUanalyzeXGkick(mV, int Fs, int xCycles) {
|
||||
analyzeVIreg1(Fs);
|
||||
analyzeVIreg1(Fs, mVUlow.VI_read[0]);
|
||||
analyzeXGkick1();
|
||||
analyzeXGkick2(xCycles);
|
||||
// Note: Technically XGKICK should stall on the next instruction,
|
||||
|
|
@ -360,11 +396,11 @@ microVUt(void) mVUanalyzeXGkick(mV, int Fs, int xCycles) {
|
|||
}
|
||||
|
||||
microVUt(void) mVUanalyzeBranch1(mV, int Is) {
|
||||
if (mVUregs.VI[Is] || mVUstall) { analyzeVIreg1(Is); }
|
||||
if (mVUregs.VI[Is] || mVUstall) { analyzeVIreg1(Is, mVUlow.VI_read[0]); }
|
||||
else { analyzeBranchVI(Is, mVUlow.memReadIs); }
|
||||
}
|
||||
|
||||
microVUt(void) mVUanalyzeBranch2(mV, int Is, int It) {
|
||||
if (mVUregs.VI[Is] || mVUregs.VI[It] || mVUstall) { analyzeVIreg1(Is); analyzeVIreg1(It); }
|
||||
if (mVUregs.VI[Is] || mVUregs.VI[It] || mVUstall) { analyzeVIreg1(Is, mVUlow.VI_read[0]); analyzeVIreg1(It, mVUlow.VI_read[1]); }
|
||||
else { analyzeBranchVI(Is, mVUlow.memReadIs); analyzeBranchVI(It, mVUlow.memReadIt);}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -65,12 +65,31 @@ struct microBlock {
|
|||
u8* x86ptrStart; // Start of code
|
||||
};
|
||||
|
||||
struct microVFreg {
|
||||
u8 reg; // Reg Index
|
||||
u8 x; // X vector read/written to?
|
||||
u8 y; // Y vector read/written to?
|
||||
u8 z; // Z vector read/written to?
|
||||
u8 w; // W vector read/written to?
|
||||
};
|
||||
|
||||
struct microVIreg {
|
||||
u8 reg; // Reg Index
|
||||
u8 used; // Reg is Used? (Read/Written)
|
||||
};
|
||||
|
||||
struct microUpperOp {
|
||||
bool eBit; // Has E-bit set
|
||||
bool iBit; // Has I-bit set
|
||||
bool eBit; // Has E-bit set
|
||||
bool iBit; // Has I-bit set
|
||||
microVFreg VF_write; // VF Vectors written to by this instruction
|
||||
microVFreg VF_read[2]; // VF Vectors read by this instruction
|
||||
};
|
||||
|
||||
struct microLowerOp {
|
||||
microVFreg VF_write; // VF Vectors written to by this instruction
|
||||
microVFreg VF_read[2]; // VF Vectors read by this instruction
|
||||
microVIreg VI_write; // VI reg written to by this instruction
|
||||
microVIreg VI_read[2]; // VI regs read by this instruction
|
||||
bool isNOP; // This instruction is a NOP
|
||||
bool isFSSET; // This instruction is a FSSET
|
||||
bool useSflag; // This instruction uses/reads Sflag
|
||||
|
|
|
|||
|
|
@ -664,7 +664,7 @@ mVUop(mVU_ISUBIU) {
|
|||
//------------------------------------------------------------------
|
||||
|
||||
mVUop(mVU_MFIR) {
|
||||
pass1 { if (!_Ft_) { mVUlow.isNOP = 1; } analyzeVIreg1(_Is_); analyzeReg2(_Ft_, 1); }
|
||||
pass1 { if (!_Ft_) { mVUlow.isNOP = 1; } analyzeVIreg1(_Is_, mVUlow.VI_read[0]); analyzeReg2(_Ft_, mVUlow.VF_write, 1); }
|
||||
pass2 {
|
||||
mVUallocVIa(mVU, gprT1, _Is_);
|
||||
MOVSX32R16toR(gprT1, gprT1);
|
||||
|
|
@ -704,7 +704,7 @@ mVUop(mVU_MR32) {
|
|||
}
|
||||
|
||||
mVUop(mVU_MTIR) {
|
||||
pass1 { if (!_It_) { mVUlow.isNOP = 1; } analyzeReg5(_Fs_, _Fsf_); analyzeVIreg2(_It_, 1); }
|
||||
pass1 { if (!_It_) { mVUlow.isNOP = 1; } analyzeReg5(_Fs_, _Fsf_, mVUlow.VF_read[0]); analyzeVIreg2(_It_, mVUlow.VI_write, 1); }
|
||||
pass2 {
|
||||
MOVZX32M16toR(gprT1, (uptr)&mVU->regs->VF[_Fs_].UL[_Fsf_]);
|
||||
mVUallocVIb(mVU, gprT1, _It_);
|
||||
|
|
@ -717,7 +717,7 @@ mVUop(mVU_MTIR) {
|
|||
//------------------------------------------------------------------
|
||||
|
||||
mVUop(mVU_ILW) {
|
||||
pass1 { if (!_It_) { mVUlow.isNOP = 1; } analyzeVIreg1(_Is_); analyzeVIreg2(_It_, 4); }
|
||||
pass1 { if (!_It_) { mVUlow.isNOP = 1; } analyzeVIreg1(_Is_, mVUlow.VI_read[0]); analyzeVIreg2(_It_, mVUlow.VI_write, 4); }
|
||||
pass2 {
|
||||
if (!_Is_) {
|
||||
MOVZX32M16toR(gprT1, (uptr)mVU->regs->Mem + getVUmem(_Imm11_) + offsetSS);
|
||||
|
|
@ -735,7 +735,7 @@ mVUop(mVU_ILW) {
|
|||
}
|
||||
|
||||
mVUop(mVU_ILWR) {
|
||||
pass1 { if (!_It_) { mVUlow.isNOP = 1; } analyzeVIreg1(_Is_); analyzeVIreg2(_It_, 4); }
|
||||
pass1 { if (!_It_) { mVUlow.isNOP = 1; } analyzeVIreg1(_Is_, mVUlow.VI_read[0]); analyzeVIreg2(_It_, mVUlow.VI_write, 4); }
|
||||
pass2 {
|
||||
if (!_Is_) {
|
||||
MOVZX32M16toR(gprT1, (uptr)mVU->regs->Mem + offsetSS);
|
||||
|
|
@ -756,7 +756,7 @@ mVUop(mVU_ILWR) {
|
|||
//------------------------------------------------------------------
|
||||
|
||||
mVUop(mVU_ISW) {
|
||||
pass1 { analyzeVIreg1(_Is_); analyzeVIreg1(_It_); }
|
||||
pass1 { analyzeVIreg1(_Is_, mVUlow.VI_read[0]); analyzeVIreg1(_It_, mVUlow.VI_read[1]); }
|
||||
pass2 {
|
||||
if (!_Is_) {
|
||||
int imm = getVUmem(_Imm11_);
|
||||
|
|
@ -781,7 +781,7 @@ mVUop(mVU_ISW) {
|
|||
}
|
||||
|
||||
mVUop(mVU_ISWR) {
|
||||
pass1 { analyzeVIreg1(_Is_); analyzeVIreg1(_It_); }
|
||||
pass1 { analyzeVIreg1(_Is_, mVUlow.VI_read[0]); analyzeVIreg1(_It_, mVUlow.VI_read[1]); }
|
||||
pass2 {
|
||||
if (!_Is_) {
|
||||
mVUallocVIa(mVU, gprT1, _It_);
|
||||
|
|
@ -1018,7 +1018,7 @@ mVUop(mVU_WAITQ) {
|
|||
//------------------------------------------------------------------
|
||||
|
||||
mVUop(mVU_XTOP) {
|
||||
pass1 { if (!_It_) { mVUlow.isNOP = 1; } analyzeVIreg2(_It_, 1); }
|
||||
pass1 { if (!_It_) { mVUlow.isNOP = 1; } analyzeVIreg2(_It_, mVUlow.VI_write, 1); }
|
||||
pass2 {
|
||||
MOVZX32M16toR(gprT1, (uptr)&mVU->regs->vifRegs->top);
|
||||
mVUallocVIb(mVU, gprT1, _It_);
|
||||
|
|
@ -1027,7 +1027,7 @@ mVUop(mVU_XTOP) {
|
|||
}
|
||||
|
||||
mVUop(mVU_XITOP) {
|
||||
pass1 { if (!_It_) { mVUlow.isNOP = 1; } analyzeVIreg2(_It_, 1); }
|
||||
pass1 { if (!_It_) { mVUlow.isNOP = 1; } analyzeVIreg2(_It_, mVUlow.VI_write, 1); }
|
||||
pass2 {
|
||||
MOVZX32M16toR(gprT1, (uptr)&mVU->regs->vifRegs->itop);
|
||||
mVUallocVIb(mVU, gprT1, _It_);
|
||||
|
|
@ -1100,7 +1100,7 @@ mVUop(mVU_B) {
|
|||
|
||||
mVUop(mVU_BAL) {
|
||||
setBranchA(2, _It_);
|
||||
pass1 { analyzeVIreg2(_It_, 1); }
|
||||
pass1 { analyzeVIreg2(_It_, mVUlow.VI_write, 1); }
|
||||
pass2 {
|
||||
MOV32ItoR(gprT1, bSaveAddr);
|
||||
mVUallocVIb(mVU, gprT1, _It_);
|
||||
|
|
@ -1180,7 +1180,7 @@ mVUop(mVU_IBNE) {
|
|||
|
||||
mVUop(mVU_JR) {
|
||||
mVUbranch = 9;
|
||||
pass1 { analyzeVIreg1(_Is_); }
|
||||
pass1 { analyzeVIreg1(_Is_, mVUlow.VI_read[0]); }
|
||||
pass2 {
|
||||
mVUallocVIa(mVU, gprT1, _Is_);
|
||||
SHL32ItoR(gprT1, 3);
|
||||
|
|
@ -1192,7 +1192,7 @@ mVUop(mVU_JR) {
|
|||
|
||||
mVUop(mVU_JALR) {
|
||||
mVUbranch = 10;
|
||||
pass1 { analyzeVIreg1(_Is_); analyzeVIreg2(_It_, 1); }
|
||||
pass1 { analyzeVIreg1(_Is_, mVUlow.VI_read[0]); analyzeVIreg2(_It_, mVUlow.VI_write, 1); }
|
||||
pass2 {
|
||||
mVUallocVIa(mVU, gprT1, _Is_);
|
||||
SHL32ItoR(gprT1, 3);
|
||||
|
|
|
|||
Loading…
Reference in New Issue