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Replace assert() with pxAssert() in pcsx2 core and recompilers. 

Rationale: assert() is not thread safe on win32 (the modal popup can block user input or hang the program), and is neigh useless on Linux (just does a DebugBreak/Trap).  Furthermore, pxAssert() registers stack traces and supports more detailed textual descriptions.  I considered just #undef/#define on the assert macro, but MSVC's assert.h also does #undef/#define so it'd be too prone to accidentally calling MSVC's problematic version if some nested header included <assert.h> (which many do).

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2077 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
Jake.Stine 2009-10-25 15:07:43 +00:00
parent 6db222ff56
commit a6d716b351
28 changed files with 273 additions and 318 deletions
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4
pcsx2/FiFo.cpp
View File

@ -116,7 +116,7 @@ void __fastcall WriteFIFO_page_4(u32 mem, const mem128_t *value)
vif0ch->qwc += 1; vif0ch->qwc += 1;
int ret = VIF0transfer((u32*)value, 4, 0); int ret = VIF0transfer((u32*)value, 4, 0);
assert( ret == 0 ); // vif stall code not implemented pxAssertDev( ret == 0, "vif stall code not implemented" );
} }
void __fastcall WriteFIFO_page_5(u32 mem, const mem128_t *value) void __fastcall WriteFIFO_page_5(u32 mem, const mem128_t *value)
@ -135,7 +135,7 @@ void __fastcall WriteFIFO_page_5(u32 mem, const mem128_t *value)
vif1ch->qwc += 1; vif1ch->qwc += 1;
int ret = VIF1transfer((u32*)value, 4, 0); int ret = VIF1transfer((u32*)value, 4, 0);
assert( ret == 0 ); // vif stall code not implemented pxAssertDev( ret == 0, "vif stall code not implemented" );
} }
// Dummy GIF-TAG Packet to Guarantee Count = 1 // Dummy GIF-TAG Packet to Guarantee Count = 1

2
pcsx2/HwWrite.cpp
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@ -329,7 +329,7 @@ void hwWrite8(u32 mem, u8 value)
break; break;
default: default:
assert( (mem & 0xff0f) != 0xf200 ); pxAssert( (mem & 0xff0f) != 0xf200 );
switch(mem&~3) { switch(mem&~3) {
case SIO_ISR: case SIO_ISR:

18
pcsx2/IPU/IPU.cpp
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@ -447,7 +447,7 @@ static __forceinline BOOL ipuIDEC(u32 val)
g_decoder.dcr = 1;//resets DC prediction value g_decoder.dcr = 1;//resets DC prediction value
s_routine = so_create(mpeg2sliceIDEC, &s_RoutineDone, s_tempstack, sizeof(s_tempstack)); s_routine = so_create(mpeg2sliceIDEC, &s_RoutineDone, s_tempstack, sizeof(s_tempstack));
assert(s_routine != NULL); pxAssert(s_routine != NULL);
so_call(s_routine); so_call(s_routine);
if (s_RoutineDone) s_routine = NULL; if (s_RoutineDone) s_routine = NULL;
@ -501,7 +501,7 @@ static __forceinline BOOL ipuBDEC(u32 val)
memzero(mb16); memzero(mb16);
s_routine = so_create(mpeg2_slice, &s_RoutineDone, s_tempstack, sizeof(s_tempstack)); s_routine = so_create(mpeg2_slice, &s_RoutineDone, s_tempstack, sizeof(s_tempstack));
assert(s_routine != NULL); pxAssert(s_routine != NULL);
so_call(s_routine); so_call(s_routine);
if (s_RoutineDone) s_routine = NULL; if (s_RoutineDone) s_routine = NULL;
@ -872,7 +872,7 @@ void IPUCMD_WRITE(u32 val)
void IPUWorker() void IPUWorker()
{ {
assert(ipuRegs->ctrl.BUSY); pxAssert(ipuRegs->ctrl.BUSY);
switch (ipuCurCmd) switch (ipuCurCmd)
{ {
@ -1032,7 +1032,7 @@ u16 __fastcall FillInternalBuffer(u32 * pointer, u32 advance, u32 size)
if (*(int*)pointer >= 128) if (*(int*)pointer >= 128)
{ {
assert(g_BP.FP >= 1); pxAssert(g_BP.FP >= 1);
if (g_BP.FP > 1) inc_readbits(); if (g_BP.FP > 1) inc_readbits();
@ -1312,7 +1312,7 @@ int FIFOto_read(void *value)
{ {
// This is the only spot that wants a return value for IPU1dma. // This is the only spot that wants a return value for IPU1dma.
if (IPU1dma() == 0) return 0; if (IPU1dma() == 0) return 0;
assert(g_BP.IFC > 0); pxAssert(g_BP.IFC > 0);
} }
// transfer 1 qword, split into two transfers // transfer 1 qword, split into two transfers
@ -1450,11 +1450,11 @@ int IPU1dma()
bool done = false; bool done = false;
int ipu1cycles = 0, totalqwc = 0; int ipu1cycles = 0, totalqwc = 0;
assert(!ipu1dma->chcr.TTE); pxAssert(!ipu1dma->chcr.TTE);
if (!(ipu1dma->chcr.STR) || (cpuRegs.interrupt & (1 << DMAC_TO_IPU))) return 0; if (!(ipu1dma->chcr.STR) || (cpuRegs.interrupt & (1 << DMAC_TO_IPU))) return 0;
assert(g_nDMATransfer.TIE1 == 0); pxAssert(g_nDMATransfer.TIE1 == 0);
//We need to make sure GIF has flushed before sending IPU data, it seems to REALLY screw FFX videos //We need to make sure GIF has flushed before sending IPU data, it seems to REALLY screw FFX videos
flushGIF(); flushGIF();
@ -1662,12 +1662,12 @@ int IPU0dma()
if ((!(ipu0dma->chcr.STR) || (cpuRegs.interrupt & (1 << DMAC_FROM_IPU))) || (ipu0dma->qwc == 0)) if ((!(ipu0dma->chcr.STR) || (cpuRegs.interrupt & (1 << DMAC_FROM_IPU))) || (ipu0dma->qwc == 0))
return 0; return 0;
assert(!(ipu0dma->chcr.TTE)); pxAssert(!(ipu0dma->chcr.TTE));
IPU_LOG("dmaIPU0 chcr = %lx, madr = %lx, qwc = %lx", IPU_LOG("dmaIPU0 chcr = %lx, madr = %lx, qwc = %lx",
ipu0dma->chcr._u32, ipu0dma->madr, ipu0dma->qwc); ipu0dma->chcr._u32, ipu0dma->madr, ipu0dma->qwc);
assert((ipu0dma->chcr._u32 & 0xC) == 0); pxAssert((ipu0dma->chcr._u32 & 0xC) == 0);
pMem = (u32*)dmaGetAddr(ipu0dma->madr); pMem = (u32*)dmaGetAddr(ipu0dma->madr);
readsize = min(ipu0dma->qwc, (u16)ipuRegs->ctrl.OFC); readsize = min(ipu0dma->qwc, (u16)ipuRegs->ctrl.OFC);

2
pcsx2/IPU/coroutine.cpp
View File

@ -64,7 +64,7 @@ coroutine_t so_create(void (*func)(void *), void *data, void *stack, int size)
void so_delete(coroutine_t coro) void so_delete(coroutine_t coro)
{ {
coroutine *co = (coroutine *) coro; coroutine *co = (coroutine *) coro;
assert( co != NULL ); pxAssert( co != NULL );
if (co->alloc) free(co); if (co->alloc) free(co);
} }

20
pcsx2/IopCounters.cpp
View File

@ -317,7 +317,7 @@ static void _psxCheckEndGate(int i)
void psxCheckStartGate16(int i) void psxCheckStartGate16(int i)
{ {
assert( i < 3 ); pxAssert( i < 3 );
if(i == 0) // hSync counting... if(i == 0) // hSync counting...
{ {
@ -353,20 +353,20 @@ void psxCheckStartGate16(int i)
void psxCheckEndGate16(int i) void psxCheckEndGate16(int i)
{ {
assert(i < 3); pxAssert(i < 3);
_psxCheckEndGate( i ); _psxCheckEndGate( i );
} }
static void psxCheckStartGate32(int i) static void psxCheckStartGate32(int i)
{ {
// 32 bit gate is called for gate 3 only. Ever. // 32 bit gate is called for gate 3 only. Ever.
assert(i == 3); pxAssert(i == 3);
_psxCheckStartGate( i ); _psxCheckStartGate( i );
} }
static void psxCheckEndGate32(int i) static void psxCheckEndGate32(int i)
{ {
assert(i == 3); pxAssert(i == 3);
_psxCheckEndGate( i ); _psxCheckEndGate( i );
} }
@ -496,7 +496,7 @@ void psxRcntWcount16(int index, u16 value)
{ {
u32 change; u32 change;
assert( index < 3 ); pxAssert( index < 3 );
PSXCNT_LOG("IOP Counter[%d] writeCount16 = %x", index, value); PSXCNT_LOG("IOP Counter[%d] writeCount16 = %x", index, value);
if(psxCounters[index].rate != PSXHBLANK) if(psxCounters[index].rate != PSXHBLANK)
@ -519,7 +519,7 @@ void psxRcntWcount32(int index, u32 value)
{ {
u32 change; u32 change;
assert( index >= 3 && index < 6 ); pxAssert( index >= 3 && index < 6 );
PSXCNT_LOG("IOP Counter[%d] writeCount32 = %x", index, value); PSXCNT_LOG("IOP Counter[%d] writeCount32 = %x", index, value);
if(psxCounters[index].rate != PSXHBLANK) if(psxCounters[index].rate != PSXHBLANK)
@ -652,7 +652,7 @@ __forceinline void psxRcntWmode32( int index, u32 value )
// //
void psxRcntWtarget16(int index, u32 value) void psxRcntWtarget16(int index, u32 value)
{ {
assert( index < 3 ); pxAssert( index < 3 );
PSXCNT_LOG("IOP Counter[%d] writeTarget16 = %lx", index, value); PSXCNT_LOG("IOP Counter[%d] writeTarget16 = %lx", index, value);
psxCounters[index].target = value & 0xffff; psxCounters[index].target = value & 0xffff;
@ -668,7 +668,7 @@ void psxRcntWtarget16(int index, u32 value)
void psxRcntWtarget32(int index, u32 value) void psxRcntWtarget32(int index, u32 value)
{ {
assert( index >= 3 && index < 6); pxAssert( index >= 3 && index < 6);
PSXCNT_LOG("IOP Counter[%d] writeTarget32 = %lx", index, value); PSXCNT_LOG("IOP Counter[%d] writeTarget32 = %lx", index, value);
psxCounters[index].target = value; psxCounters[index].target = value;
@ -687,7 +687,7 @@ u16 psxRcntRcount16(int index)
{ {
u32 retval = (u32)psxCounters[index].count; u32 retval = (u32)psxCounters[index].count;
assert( index < 3 ); pxAssert( index < 3 );
PSXCNT_LOG("IOP Counter[%d] readCount16 = %lx", index, (u16)retval ); PSXCNT_LOG("IOP Counter[%d] readCount16 = %lx", index, (u16)retval );
@ -709,7 +709,7 @@ u32 psxRcntRcount32(int index)
{ {
u32 retval = (u32)psxCounters[index].count; u32 retval = (u32)psxCounters[index].count;
assert( index >= 3 && index < 6 ); pxAssert( index >= 3 && index < 6 );
PSXCNT_LOG("IOP Counter[%d] readCount32 = %lx", index, retval ); PSXCNT_LOG("IOP Counter[%d] readCount32 = %lx", index, retval );

2
pcsx2/R5900.cpp
View File

@ -172,7 +172,7 @@ void cpuTlbMiss(u32 addr, u32 bd, u32 excode)
if (bd) Console.Notice("branch delay!!"); if (bd) Console.Notice("branch delay!!");
assert(0); // temporary pxFail( "TLB Miss handler is uninished code." ); // temporary
cpuRegs.CP0.n.BadVAddr = addr; cpuRegs.CP0.n.BadVAddr = addr;
cpuRegs.CP0.n.Context &= 0xFF80000F; cpuRegs.CP0.n.Context &= 0xFF80000F;

12
pcsx2/SourceLog.cpp
View File

@ -61,12 +61,8 @@ void __Log( const char* fmt, ... )
int length = vsprintf(tmp, fmt, list); int length = vsprintf(tmp, fmt, list);
va_end( list ); va_end( list );
assert( length <= 2020 ); pxAssertDev( length <= 2020, "Source log buffer overrun" );
if( length > 2020 )
{
Msgbox::Alert( _("Source log buffer overrun") );
// fixme: should throw an exception here once we have proper exception handling implemented. // fixme: should throw an exception here once we have proper exception handling implemented.
}
#ifdef PCSX2_DEVBUILD #ifdef PCSX2_DEVBUILD
if (varLog.LogToConsole) // log to console enabled? if (varLog.LogToConsole) // log to console enabled?
@ -92,12 +88,8 @@ static __forceinline void _vSourceLog( u16 protocol, u8 source, u32 cpuPc, u32 c
// concatenate the log message after the prefix: // concatenate the log message after the prefix:
int length = vsprintf(&tmp[prelength], fmt, list); int length = vsprintf(&tmp[prelength], fmt, list);
assert( length <= 2020 ); pxAssertDev( length <= 2020, "Source log buffer overrun" );
if( length > 2020 )
{
Msgbox::Alert( _("Source log buffer overrun") );
// fixme: should throw an exception here once we have proper exception handling implemented. // fixme: should throw an exception here once we have proper exception handling implemented.
}
#ifdef PCSX2_DEVBUILD #ifdef PCSX2_DEVBUILD
#ifdef _WIN32 #ifdef _WIN32

8
pcsx2/Vif0Dma.cpp
View File

@ -130,9 +130,9 @@ static int __fastcall Vif0TransSTRow(u32 *data) // STROW
u32* pmem = &vif0Regs->r0 + (vif0.tag.addr << 2); u32* pmem = &vif0Regs->r0 + (vif0.tag.addr << 2);
u32* pmem2 = g_vifmask.Row0 + vif0.tag.addr; u32* pmem2 = g_vifmask.Row0 + vif0.tag.addr;
assert(vif0.tag.addr < 4); pxAssert(vif0.tag.addr < 4);
ret = min(4 - vif0.tag.addr, vif0.vifpacketsize); ret = min(4 - vif0.tag.addr, vif0.vifpacketsize);
assert(ret > 0); pxAssert(ret > 0);
switch (ret) switch (ret)
{ {
@ -756,7 +756,7 @@ void vif0Write32(u32 mem, u32 value)
case VIF0_R1: case VIF0_R1:
case VIF0_R2: case VIF0_R2:
case VIF0_R3: case VIF0_R3:
assert((mem&0xf) == 0); pxAssert((mem&0xf) == 0);
g_vifmask.Row0[(mem>>4) & 3] = value; g_vifmask.Row0[(mem>>4) & 3] = value;
break; break;
@ -764,7 +764,7 @@ void vif0Write32(u32 mem, u32 value)
case VIF0_C1: case VIF0_C1:
case VIF0_C2: case VIF0_C2:
case VIF0_C3: case VIF0_C3:
assert((mem&0xf) == 0); pxAssert((mem&0xf) == 0);
g_vifmask.Col0[(mem>>4) & 3] = value; g_vifmask.Col0[(mem>>4) & 3] = value;
break; break;

10
pcsx2/Vif1Dma.cpp
View File

@ -112,7 +112,7 @@ static __forceinline void vif1mpgTransfer(u32 addr, u32 *data, int size)
fwrite(data, 1, size*4, f); fwrite(data, 1, size*4, f);
fclose(f); fclose(f);
}*/ }*/
assert(VU1.Micro > 0); pxAssert(VU1.Micro > 0);
if (memcmp(VU1.Micro + addr, data, size << 2)) if (memcmp(VU1.Micro + addr, data, size << 2))
{ {
CpuVU1.Clear(addr, size << 2); // Clear before writing! :/ CpuVU1.Clear(addr, size << 2); // Clear before writing! :/
@ -148,9 +148,9 @@ static int __fastcall Vif1TransSTRow(u32 *data) // STROW
u32* pmem = &vif1Regs->r0 + (vif1.tag.addr << 2); u32* pmem = &vif1Regs->r0 + (vif1.tag.addr << 2);
u32* pmem2 = g_vifmask.Row1 + vif1.tag.addr; u32* pmem2 = g_vifmask.Row1 + vif1.tag.addr;
assert(vif1.tag.addr < 4); pxAssert(vif1.tag.addr < 4);
ret = min(4 - vif1.tag.addr, vif1.vifpacketsize); ret = min(4 - vif1.tag.addr, vif1.vifpacketsize);
assert(ret > 0); pxAssert(ret > 0);
switch (ret) switch (ret)
{ {
@ -1149,7 +1149,7 @@ void vif1Write32(u32 mem, u32 value)
case VIF1_R1: case VIF1_R1:
case VIF1_R2: case VIF1_R2:
case VIF1_R3: case VIF1_R3:
assert((mem&0xf) == 0); pxAssert((mem&0xf) == 0);
g_vifmask.Row1[(mem>>4) & 3] = value; g_vifmask.Row1[(mem>>4) & 3] = value;
break; break;
@ -1157,7 +1157,7 @@ void vif1Write32(u32 mem, u32 value)
case VIF1_C1: case VIF1_C1:
case VIF1_C2: case VIF1_C2:
case VIF1_C3: case VIF1_C3:
assert((mem&0xf) == 0); pxAssert((mem&0xf) == 0);
g_vifmask.Col1[(mem>>4) & 3] = value; g_vifmask.Col1[(mem>>4) & 3] = value;
break; break;

6
pcsx2/VifDma.cpp
View File

@ -286,7 +286,7 @@ template<const u32 VIFdmanum> u32 VIFalign(u32 *data, vifCode *v, u32 size)
vif = &vif1; vif = &vif1;
vifRow = g_vifmask.Row1; vifRow = g_vifmask.Row1;
} }
assert(v->addr < memsize); pxAssert(v->addr < memsize);
dest = (u32*)(VU->Mem + v->addr); dest = (u32*)(VU->Mem + v->addr);
@ -493,7 +493,7 @@ template<const u32 VIFdmanum> void VIFunpack(u32 *data, vifCode *v, u32 size)
vifMaskRegs = g_vif0Masks; vifMaskRegs = g_vif0Masks;
vif = &vif0; vif = &vif0;
vifRow = g_vifmask.Row0; vifRow = g_vifmask.Row0;
assert(v->addr < memsize); pxAssert(v->addr < memsize);
} }
else else
{ {
@ -503,7 +503,7 @@ template<const u32 VIFdmanum> void VIFunpack(u32 *data, vifCode *v, u32 size)
vifMaskRegs = g_vif1Masks; vifMaskRegs = g_vif1Masks;
vif = &vif1; vif = &vif1;
vifRow = g_vifmask.Row1; vifRow = g_vifmask.Row1;
assert(v->addr < memsize); pxAssert(v->addr < memsize);
} }
dest = (u32*)(VU->Mem + v->addr); dest = (u32*)(VU->Mem + v->addr);

2
pcsx2/x86/BaseblockEx.cpp
View File

@ -36,7 +36,7 @@ BASEBLOCKEX* BaseBlocks::New(u32 startpc, uptr fnptr)
imin = imid + 1; imin = imid + 1;
} }
assert(imin == blocks.size() || blocks[imin].startpc > startpc); pxAssert(imin == blocks.size() || blocks[imin].startpc > startpc);
iter = blocks.insert(blocks.begin() + imin, newblock); iter = blocks.insert(blocks.begin() + imin, newblock);
std::pair<linkiter_t, linkiter_t> range = links.equal_range(startpc); std::pair<linkiter_t, linkiter_t> range = links.equal_range(startpc);

8
pcsx2/x86/iCOP2.cpp
View File

@ -137,7 +137,7 @@ static void recCTC2(s32 info)
break; break;
case REG_CMSAR1: // REG_CMSAR1 case REG_CMSAR1: // REG_CMSAR1
iFlushCall(FLUSH_NOCONST); iFlushCall(FLUSH_NOCONST);
assert( _checkX86reg(X86TYPE_VI, REG_VPU_STAT, 0) < 0 && pxAssert( _checkX86reg(X86TYPE_VI, REG_VPU_STAT, 0) < 0 &&
_checkX86reg(X86TYPE_VI, REG_TPC, 0) < 0 ); _checkX86reg(X86TYPE_VI, REG_TPC, 0) < 0 );
// Execute VU1 Micro SubRoutine // Execute VU1 Micro SubRoutine
@ -147,7 +147,7 @@ static void recCTC2(s32 info)
default: default:
{ {
if( _Fs_ < 16 ) if( _Fs_ < 16 )
assert( (g_cpuConstRegs[_Rt_].UL[0]&0xffff0000)==0); pxAssert( (g_cpuConstRegs[_Rt_].UL[0]&0xffff0000)==0);
// a lot of games have vu0 spinning on some integer // a lot of games have vu0 spinning on some integer
// then they modify the register and expect vu0 to stop spinning within 10 cycles (donald duck) // then they modify the register and expect vu0 to stop spinning within 10 cycles (donald duck)
@ -174,7 +174,7 @@ static void recCTC2(s32 info)
break; break;
case REG_FBRST: case REG_FBRST:
iFlushCall(FLUSH_FREE_TEMPX86); iFlushCall(FLUSH_FREE_TEMPX86);
assert( _checkX86reg(X86TYPE_VI, REG_FBRST, 0) < 0 ); pxAssert( _checkX86reg(X86TYPE_VI, REG_FBRST, 0) < 0 );
_eeMoveGPRtoR(EAX, _Rt_); _eeMoveGPRtoR(EAX, _Rt_);
@ -311,7 +311,7 @@ static void recQMTC2(s32 info)
} }
else { else {
if( GPR_IS_CONST1( _Rt_ ) ) { if( GPR_IS_CONST1( _Rt_ ) ) {
assert( _checkXMMreg(XMMTYPE_GPRREG, _Rt_, MODE_READ) == -1 ); pxAssert( _checkXMMreg(XMMTYPE_GPRREG, _Rt_, MODE_READ) == -1 );
_flushConstReg(_Rt_); _flushConstReg(_Rt_);
} }

40
pcsx2/x86/iCore.cpp
View File

@ -65,7 +65,7 @@ __forceinline void* _XMMGetAddr(int type, int reg, VURegs *VU)
case XMMTYPE_GPRREG: case XMMTYPE_GPRREG:
if( reg < 32 ) if( reg < 32 )
assert( !(g_cpuHasConstReg & (1<<reg)) || (g_cpuFlushedConstReg & (1<<reg)) ); pxAssert( !(g_cpuHasConstReg & (1<<reg)) || (g_cpuFlushedConstReg & (1<<reg)) );
return &cpuRegs.GPR.r[reg].UL[0]; return &cpuRegs.GPR.r[reg].UL[0];
case XMMTYPE_FPREG: case XMMTYPE_FPREG:
@ -342,7 +342,7 @@ int _allocGPRtoXMMreg(int xmmreg, int gprreg, int mode)
if (xmmregs[i].type != XMMTYPE_GPRREG) continue; if (xmmregs[i].type != XMMTYPE_GPRREG) continue;
if (xmmregs[i].reg != gprreg) continue; if (xmmregs[i].reg != gprreg) continue;
assert( _checkMMXreg(MMX_GPR|gprreg, mode) == -1 ); pxAssert( _checkMMXreg(MMX_GPR|gprreg, mode) == -1 );
g_xmmtypes[i] = XMMT_INT; g_xmmtypes[i] = XMMT_INT;
@ -354,7 +354,7 @@ int _allocGPRtoXMMreg(int xmmreg, int gprreg, int mode)
} }
else else
{ {
//assert( !(g_cpuHasConstReg & (1<<gprreg)) || (g_cpuFlushedConstReg & (1<<gprreg)) ); //pxAssert( !(g_cpuHasConstReg & (1<<gprreg)) || (g_cpuFlushedConstReg & (1<<gprreg)) );
_flushConstReg(gprreg); _flushConstReg(gprreg);
SSEX_MOVDQA_M128_to_XMM(i, (uptr)&cpuRegs.GPR.r[gprreg].UL[0]); SSEX_MOVDQA_M128_to_XMM(i, (uptr)&cpuRegs.GPR.r[gprreg].UL[0]);
} }
@ -364,7 +364,7 @@ int _allocGPRtoXMMreg(int xmmreg, int gprreg, int mode)
if ((mode & MODE_WRITE) && (gprreg < 32)) if ((mode & MODE_WRITE) && (gprreg < 32))
{ {
g_cpuHasConstReg &= ~(1<<gprreg); g_cpuHasConstReg &= ~(1<<gprreg);
//assert( !(g_cpuHasConstReg & (1<<gprreg)) ); //pxAssert( !(g_cpuHasConstReg & (1<<gprreg)) );
} }
xmmregs[i].counter = g_xmmAllocCounter++; // update counter xmmregs[i].counter = g_xmmAllocCounter++; // update counter
@ -377,7 +377,7 @@ int _allocGPRtoXMMreg(int xmmreg, int gprreg, int mode)
// fixme - do we really need to execute this both here and in the loop? // fixme - do we really need to execute this both here and in the loop?
if ((mode & MODE_WRITE) && gprreg < 32) if ((mode & MODE_WRITE) && gprreg < 32)
{ {
//assert( !(g_cpuHasConstReg & (1<<gprreg)) ); //pxAssert( !(g_cpuHasConstReg & (1<<gprreg)) );
g_cpuHasConstReg &= ~(1<<gprreg); g_cpuHasConstReg &= ~(1<<gprreg);
} }
@ -559,7 +559,7 @@ void _clearNeededXMMregs() {
} }
if( xmmregs[i].inuse ) { if( xmmregs[i].inuse ) {
assert( xmmregs[i].type != XMMTYPE_TEMP ); pxAssert( xmmregs[i].type != XMMTYPE_TEMP );
} }
} }
} }
@ -582,7 +582,7 @@ void _deleteVFtoXMMreg(int reg, int vu, int flush)
case 2: case 2:
if( xmmregs[i].mode & MODE_WRITE ) if( xmmregs[i].mode & MODE_WRITE )
{ {
assert( reg != 0 ); pxAssert( reg != 0 );
if( xmmregs[i].mode & MODE_VUXYZ ) if( xmmregs[i].mode & MODE_VUXYZ )
{ {
@ -710,9 +710,9 @@ void _deleteGPRtoXMMreg(int reg, int flush)
case 1: case 1:
case 2: case 2:
if( xmmregs[i].mode & MODE_WRITE ) { if( xmmregs[i].mode & MODE_WRITE ) {
assert( reg != 0 ); pxAssert( reg != 0 );
//assert( g_xmmtypes[i] == XMMT_INT ); //pxAssert( g_xmmtypes[i] == XMMT_INT );
SSEX_MOVDQA_XMM_to_M128((uptr)&cpuRegs.GPR.r[reg].UL[0], i); SSEX_MOVDQA_XMM_to_M128((uptr)&cpuRegs.GPR.r[reg].UL[0], i);
// get rid of MODE_WRITE since don't want to flush again // get rid of MODE_WRITE since don't want to flush again
@ -759,7 +759,7 @@ void _deleteFPtoXMMreg(int reg, int flush)
void _freeXMMreg(int xmmreg) void _freeXMMreg(int xmmreg)
{ {
assert( xmmreg < iREGCNT_XMM ); pxAssert( xmmreg < iREGCNT_XMM );
if (!xmmregs[xmmreg].inuse) return; if (!xmmregs[xmmreg].inuse) return;
@ -849,8 +849,8 @@ void _freeXMMreg(int xmmreg)
break; break;
case XMMTYPE_GPRREG: case XMMTYPE_GPRREG:
assert( xmmregs[xmmreg].reg != 0 ); pxAssert( xmmregs[xmmreg].reg != 0 );
//assert( g_xmmtypes[xmmreg] == XMMT_INT ); //pxAssert( g_xmmtypes[xmmreg] == XMMT_INT );
SSEX_MOVDQA_XMM_to_M128((uptr)&cpuRegs.GPR.r[xmmregs[xmmreg].reg].UL[0], xmmreg); SSEX_MOVDQA_XMM_to_M128((uptr)&cpuRegs.GPR.r[xmmregs[xmmreg].reg].UL[0], xmmreg);
break; break;
@ -938,8 +938,8 @@ void _flushXMMregs()
for (i=0; i<iREGCNT_XMM; i++) { for (i=0; i<iREGCNT_XMM; i++) {
if (xmmregs[i].inuse == 0) continue; if (xmmregs[i].inuse == 0) continue;
assert( xmmregs[i].type != XMMTYPE_TEMP ); pxAssert( xmmregs[i].type != XMMTYPE_TEMP );
assert( xmmregs[i].mode & (MODE_READ|MODE_WRITE) ); pxAssert( xmmregs[i].mode & (MODE_READ|MODE_WRITE) );
_freeXMMreg(i); _freeXMMreg(i);
xmmregs[i].inuse = 1; xmmregs[i].inuse = 1;
@ -955,8 +955,8 @@ void _freeXMMregs()
for (i=0; i<iREGCNT_XMM; i++) { for (i=0; i<iREGCNT_XMM; i++) {
if (xmmregs[i].inuse == 0) continue; if (xmmregs[i].inuse == 0) continue;
assert( xmmregs[i].type != XMMTYPE_TEMP ); pxAssert( xmmregs[i].type != XMMTYPE_TEMP );
//assert( xmmregs[i].mode & (MODE_READ|MODE_WRITE) ); //pxAssert( xmmregs[i].mode & (MODE_READ|MODE_WRITE) );
_freeXMMreg(i); _freeXMMreg(i);
} }
@ -976,7 +976,7 @@ int _signExtendXMMtoM(u32 to, x86SSERegType from, int candestroy)
} }
else { else {
// can't destroy and type is int // can't destroy and type is int
assert( g_xmmtypes[from] == XMMT_INT ); pxAssert( g_xmmtypes[from] == XMMT_INT );
if( _hasFreeXMMreg() ) { if( _hasFreeXMMreg() ) {
@ -1000,7 +1000,7 @@ int _signExtendXMMtoM(u32 to, x86SSERegType from, int candestroy)
return 0; return 0;
} }
assert(0); pxAssert( false );
} }
int _allocCheckGPRtoXMM(EEINST* pinst, int gprreg, int mode) int _allocCheckGPRtoXMM(EEINST* pinst, int gprreg, int mode)
@ -1079,7 +1079,7 @@ void _recFillRegister(EEINST& pinst, int type, int reg, int write)
return; return;
} }
} }
assert(0); pxAssert( false );
} }
else { else {
for(i = 0; i < ArraySize(pinst.readType); ++i) { for(i = 0; i < ArraySize(pinst.readType); ++i) {
@ -1089,7 +1089,7 @@ void _recFillRegister(EEINST& pinst, int type, int reg, int write)
return; return;
} }
} }
assert(0); pxAssert( false );
} }
} }

4
pcsx2/x86/iMMI.cpp
View File

@ -241,7 +241,7 @@ void recPMFHL()
break; break;
default: default:
Console.Error("PMFHL?? *pcsx2 head esplode!*"); Console.Error("PMFHL?? *pcsx2 head esplode!*");
assert(0); pxFail("PMFHL?? *pcsx2 head esplode!*");
} }
_clearNeededXMMregs(); _clearNeededXMMregs();
@ -2516,7 +2516,7 @@ void recPINTEH()
SSE2_PSHUFHW_XMM_to_XMM(EEREC_D, EEREC_D, 0xa0); SSE2_PSHUFHW_XMM_to_XMM(EEREC_D, EEREC_D, 0xa0);
} }
else if( EEREC_D == EEREC_T ) { else if( EEREC_D == EEREC_T ) {
assert( EEREC_D != EEREC_S ); pxAssert( EEREC_D != EEREC_S );
t0reg = _allocTempXMMreg(XMMT_INT, -1); t0reg = _allocTempXMMreg(XMMT_INT, -1);
SSE2_PSLLD_I8_to_XMM(EEREC_D, 16); SSE2_PSLLD_I8_to_XMM(EEREC_D, 16);
SSE2_MOVDQA_XMM_to_XMM(t0reg, EEREC_S); SSE2_MOVDQA_XMM_to_XMM(t0reg, EEREC_S);

22
pcsx2/x86/iR3000A.cpp
View File

@ -955,7 +955,7 @@ void psxSetBranchReg(u32 reg)
psxRecompileNextInstruction(1); psxRecompileNextInstruction(1);
if( x86regs[ESI].inuse ) { if( x86regs[ESI].inuse ) {
assert( x86regs[ESI].type == X86TYPE_PCWRITEBACK ); pxAssert( x86regs[ESI].type == X86TYPE_PCWRITEBACK );
MOV32RtoM((uptr)&psxRegs.pc, ESI); MOV32RtoM((uptr)&psxRegs.pc, ESI);
x86regs[ESI].inuse = 0; x86regs[ESI].inuse = 0;
#ifdef PCSX2_DEBUG #ifdef PCSX2_DEBUG
@ -987,7 +987,7 @@ void psxSetBranchReg(u32 reg)
void psxSetBranchImm( u32 imm ) void psxSetBranchImm( u32 imm )
{ {
psxbranch = 1; psxbranch = 1;
assert( imm ); pxAssert( imm );
// end the current block // end the current block
MOV32ItoM( (uptr)&psxRegs.pc, imm ); MOV32ItoM( (uptr)&psxRegs.pc, imm );
@ -1161,7 +1161,7 @@ static void __fastcall iopRecRecompile( const u32 startpc )
iDumpPsxRegisters(startpc, 0); iDumpPsxRegisters(startpc, 0);
} }
assert( startpc ); pxAssert( startpc );
// if recPtr reached the mem limit reset whole mem // if recPtr reached the mem limit reset whole mem
if (((uptr)recPtr - (uptr)recMem) >= (RECMEM_SIZE - 0x10000)) if (((uptr)recPtr - (uptr)recMem) >= (RECMEM_SIZE - 0x10000))
@ -1173,7 +1173,7 @@ static void __fastcall iopRecRecompile( const u32 startpc )
s_pCurBlock = PSX_GETBLOCK(startpc); s_pCurBlock = PSX_GETBLOCK(startpc);
assert(s_pCurBlock->GetFnptr() == (uptr)iopJITCompile pxAssert(s_pCurBlock->GetFnptr() == (uptr)iopJITCompile
|| s_pCurBlock->GetFnptr() == (uptr)iopJITCompileInBlock); || s_pCurBlock->GetFnptr() == (uptr)iopJITCompileInBlock);
s_pCurBlockEx = recBlocks.Get(HWADDR(startpc)); s_pCurBlockEx = recBlocks.Get(HWADDR(startpc));
@ -1264,7 +1264,7 @@ StartRecomp:
free(s_pInstCache); free(s_pInstCache);
s_nInstCacheSize = (s_nEndBlock-startpc)/4+10; s_nInstCacheSize = (s_nEndBlock-startpc)/4+10;
s_pInstCache = (EEINST*)malloc(sizeof(EEINST)*s_nInstCacheSize); s_pInstCache = (EEINST*)malloc(sizeof(EEINST)*s_nInstCacheSize);
assert( s_pInstCache != NULL ); pxAssert( s_pInstCache != NULL );
} }
pcur = s_pInstCache + (s_nEndBlock-startpc)/4; pcur = s_pInstCache + (s_nEndBlock-startpc)/4;
@ -1300,7 +1300,7 @@ StartRecomp:
if( IsDebugBuild && (psxdump & 1) ) if( IsDebugBuild && (psxdump & 1) )
iIopDumpBlock(startpc, recPtr); iIopDumpBlock(startpc, recPtr);
assert( (psxpc-startpc)>>2 <= 0xffff ); pxAssert( (psxpc-startpc)>>2 <= 0xffff );
s_pCurBlockEx->size = (psxpc-startpc)>>2; s_pCurBlockEx->size = (psxpc-startpc)>>2;
for(i = 1; i < (u32)s_pCurBlockEx->size; ++i) { for(i = 1; i < (u32)s_pCurBlockEx->size; ++i) {
@ -1319,7 +1319,7 @@ StartRecomp:
JMP32((uptr)iopDispatcherReg - ( (uptr)x86Ptr + 5 )); JMP32((uptr)iopDispatcherReg - ( (uptr)x86Ptr + 5 ));
} }
else { else {
if( psxbranch ) assert( !willbranch3 ); if( psxbranch ) pxAssert( !willbranch3 );
else else
{ {
ADD32ItoM((uptr)&psxRegs.cycle, psxScaleBlockCycles() ); ADD32ItoM((uptr)&psxRegs.cycle, psxScaleBlockCycles() );
@ -1327,7 +1327,7 @@ StartRecomp:
} }
if (willbranch3 || !psxbranch) { if (willbranch3 || !psxbranch) {
assert( psxpc == s_nEndBlock ); pxAssert( psxpc == s_nEndBlock );
_psxFlushCall(FLUSH_EVERYTHING); _psxFlushCall(FLUSH_EVERYTHING);
MOV32ItoM((uptr)&psxRegs.pc, psxpc); MOV32ItoM((uptr)&psxRegs.pc, psxpc);
recBlocks.Link(HWADDR(s_nEndBlock), xJcc32() ); recBlocks.Link(HWADDR(s_nEndBlock), xJcc32() );
@ -1335,14 +1335,14 @@ StartRecomp:
} }
} }
assert( x86Ptr < recMem+RECMEM_SIZE ); pxAssert( x86Ptr < recMem+RECMEM_SIZE );
assert(x86Ptr - recPtr < 0x10000); pxAssert(x86Ptr - recPtr < 0x10000);
s_pCurBlockEx->x86size = x86Ptr - recPtr; s_pCurBlockEx->x86size = x86Ptr - recPtr;
recPtr = x86Ptr; recPtr = x86Ptr;
assert( (g_psxHasConstReg&g_psxFlushedConstReg) == g_psxHasConstReg ); pxAssert( (g_psxHasConstReg&g_psxFlushedConstReg) == g_psxHasConstReg );
s_pCurBlock = NULL; s_pCurBlock = NULL;
s_pCurBlockEx = NULL; s_pCurBlockEx = NULL;

4
pcsx2/x86/iR3000Atables.cpp
View File

@ -945,7 +945,7 @@ void rpsxJALR()
psxRecompileNextInstruction(1); psxRecompileNextInstruction(1);
if( x86regs[ESI].inuse ) { if( x86regs[ESI].inuse ) {
assert( x86regs[ESI].type == X86TYPE_PCWRITEBACK ); pxAssert( x86regs[ESI].type == X86TYPE_PCWRITEBACK );
MOV32RtoM((uptr)&psxRegs.pc, ESI); MOV32RtoM((uptr)&psxRegs.pc, ESI);
x86regs[ESI].inuse = 0; x86regs[ESI].inuse = 0;
#ifdef PCSX2_DEBUG #ifdef PCSX2_DEBUG
@ -1590,7 +1590,7 @@ void rpsxpropBSC(EEINST* prev, EEINST* pinst)
break; break;
case 16: rpsxpropCP0(prev, pinst); break; case 16: rpsxpropCP0(prev, pinst); break;
case 18: assert(0); break; case 18: pxFailDev( "iop invalid opcode in const propagation" ); break;
// stores // stores
case 40: case 41: case 42: case 43: case 46: case 40: case 41: case 42: case 43: case 46:

11
pcsx2/x86/ir5900tables.cpp
View File

@ -420,9 +420,8 @@ __forceinline void BSCPropagate::rpropREGIMM()
case 25: // mtsah case 25: // mtsah
rpropSetRead(_Rs_, 0); rpropSetRead(_Rs_, 0);
break; break;
default:
assert(0); jNO_DEFAULT;
break;
} }
} }
@ -544,12 +543,12 @@ __forceinline void BSCPropagate::rpropCP1()
} }
break; break;
case 20: case 20:
assert( _Funct_ == 32 ); // CVT.S.W pxAssert( _Funct_ == 32 ); // CVT.S.W
rpropSetFPUWrite(_Fd_, EEINST_REALXMM); rpropSetFPUWrite(_Fd_, EEINST_REALXMM);
rpropSetFPURead(_Fs_, EEINST_REALXMM); rpropSetFPURead(_Fs_, EEINST_REALXMM);
break; break;
default:
assert(0); jNO_DEFAULT;
} }
} }

43
pcsx2/x86/ix86-32/iCore-32.cpp
View File

@ -153,8 +153,8 @@ int _getFreeX86reg(int mode)
_freeX86reg(tempi); _freeX86reg(tempi);
return tempi; return tempi;
} }
Console.Error("*PCSX2*: x86 error");
assert(0); pxFailDev( "x86 register allocation error" );
return -1; return -1;
} }
@ -434,7 +434,7 @@ void _deleteX86reg(int type, int reg, int flush)
void _freeX86reg(int x86reg) void _freeX86reg(int x86reg)
{ {
assert( x86reg >= 0 && x86reg < iREGCNT_GPR ); pxAssert( x86reg >= 0 && x86reg < iREGCNT_GPR );
if( x86regs[x86reg].inuse && (x86regs[x86reg].mode&MODE_WRITE) ) { if( x86regs[x86reg].inuse && (x86regs[x86reg].mode&MODE_WRITE) ) {
x86regs[x86reg].mode &= ~MODE_WRITE; x86regs[x86reg].mode &= ~MODE_WRITE;
@ -468,7 +468,7 @@ void _initMMXregs()
__forceinline void* _MMXGetAddr(int reg) __forceinline void* _MMXGetAddr(int reg)
{ {
assert( reg != MMX_TEMP ); pxAssert( reg != MMX_TEMP );
if( reg == MMX_LO ) return &cpuRegs.LO; if( reg == MMX_LO ) return &cpuRegs.LO;
if( reg == MMX_HI ) return &cpuRegs.HI; if( reg == MMX_HI ) return &cpuRegs.HI;
@ -478,7 +478,7 @@ __forceinline void* _MMXGetAddr(int reg)
if( reg >= MMX_FPU && reg < MMX_FPU+32 ) return &fpuRegs.fpr[reg&31]; if( reg >= MMX_FPU && reg < MMX_FPU+32 ) return &fpuRegs.fpr[reg&31];
if( reg >= MMX_COP0 && reg < MMX_COP0+32 ) return &cpuRegs.CP0.r[reg&31]; if( reg >= MMX_COP0 && reg < MMX_COP0+32 ) return &cpuRegs.CP0.r[reg&31];
assert( 0 ); pxAssert( false );
return NULL; return NULL;
} }
@ -541,9 +541,8 @@ int _getFreeMMXreg()
_freeMMXreg(tempi); _freeMMXreg(tempi);
return tempi; return tempi;
} }
Console.Error("*PCSX2*: mmx error");
assert(0);
pxFailDev( "mmx register allocation error" );
return -1; return -1;
} }
@ -556,7 +555,7 @@ int _allocMMXreg(int mmxreg, int reg, int mode)
if (mmxregs[i].inuse == 0 || mmxregs[i].reg != reg ) continue; if (mmxregs[i].inuse == 0 || mmxregs[i].reg != reg ) continue;
if( MMX_ISGPR(reg)) { if( MMX_ISGPR(reg)) {
assert( _checkXMMreg(XMMTYPE_GPRREG, reg-MMX_GPR, 0) == -1 ); pxAssert( _checkXMMreg(XMMTYPE_GPRREG, reg-MMX_GPR, 0) == -1 );
} }
mmxregs[i].needed = 1; mmxregs[i].needed = 1;
@ -700,7 +699,7 @@ void _deleteMMXreg(int reg, int flush)
break; break;
case 1: // flushes all of the reg case 1: // flushes all of the reg
if( mmxregs[i].mode & MODE_WRITE) { if( mmxregs[i].mode & MODE_WRITE) {
assert( mmxregs[i].reg != MMX_GPR ); pxAssert( mmxregs[i].reg != MMX_GPR );
if( MMX_IS32BITS(reg) ) if( MMX_IS32BITS(reg) )
MOVDMMXtoM((u32)_MMXGetAddr(mmxregs[i].reg), i); MOVDMMXtoM((u32)_MMXGetAddr(mmxregs[i].reg), i);
@ -764,15 +763,15 @@ u8 _hasFreeMMXreg()
void _freeMMXreg(int mmxreg) void _freeMMXreg(int mmxreg)
{ {
assert( mmxreg < iREGCNT_MMX ); pxAssert( mmxreg < iREGCNT_MMX );
if (!mmxregs[mmxreg].inuse) return; if (!mmxregs[mmxreg].inuse) return;
if (mmxregs[mmxreg].mode & MODE_WRITE ) { if (mmxregs[mmxreg].mode & MODE_WRITE ) {
// Not sure if this line is accurate, since if the 32 was 34, it would be MMX_ISGPR. // Not sure if this line is accurate, since if the 32 was 34, it would be MMX_ISGPR.
if ( /*mmxregs[mmxreg].reg >= MMX_GPR &&*/ mmxregs[mmxreg].reg < MMX_GPR+32 ) // Checking if a u32 is >=0 is pointless. if ( /*mmxregs[mmxreg].reg >= MMX_GPR &&*/ mmxregs[mmxreg].reg < MMX_GPR+32 ) // Checking if a u32 is >=0 is pointless.
assert( !(g_cpuHasConstReg & (1<<(mmxregs[mmxreg].reg-MMX_GPR))) ); pxAssert( !(g_cpuHasConstReg & (1<<(mmxregs[mmxreg].reg-MMX_GPR))) );
assert( mmxregs[mmxreg].reg != MMX_GPR ); pxAssert( mmxregs[mmxreg].reg != MMX_GPR );
if( MMX_IS32BITS(mmxregs[mmxreg].reg) ) if( MMX_IS32BITS(mmxregs[mmxreg].reg) )
MOVDMMXtoM((u32)_MMXGetAddr(mmxregs[mmxreg].reg), mmxreg); MOVDMMXtoM((u32)_MMXGetAddr(mmxregs[mmxreg].reg), mmxreg);
@ -816,10 +815,10 @@ void _flushMMXregs()
if (mmxregs[i].inuse == 0) continue; if (mmxregs[i].inuse == 0) continue;
if( mmxregs[i].mode & MODE_WRITE ) { if( mmxregs[i].mode & MODE_WRITE ) {
assert( !(g_cpuHasConstReg & (1<<mmxregs[i].reg)) ); pxAssert( !(g_cpuHasConstReg & (1<<mmxregs[i].reg)) );
assert( mmxregs[i].reg != MMX_TEMP ); pxAssert( mmxregs[i].reg != MMX_TEMP );
assert( mmxregs[i].mode & MODE_READ ); pxAssert( mmxregs[i].mode & MODE_READ );
assert( mmxregs[i].reg != MMX_GPR ); pxAssert( mmxregs[i].reg != MMX_GPR );
if( MMX_IS32BITS(mmxregs[i].reg) ) if( MMX_IS32BITS(mmxregs[i].reg) )
MOVDMMXtoM((u32)_MMXGetAddr(mmxregs[i].reg), i); MOVDMMXtoM((u32)_MMXGetAddr(mmxregs[i].reg), i);
@ -839,8 +838,8 @@ void _freeMMXregs()
for (i=0; i<iREGCNT_MMX; i++) { for (i=0; i<iREGCNT_MMX; i++) {
if (mmxregs[i].inuse == 0) continue; if (mmxregs[i].inuse == 0) continue;
assert( mmxregs[i].reg != MMX_TEMP ); pxAssert( mmxregs[i].reg != MMX_TEMP );
assert( mmxregs[i].mode & MODE_READ ); pxAssert( mmxregs[i].mode & MODE_READ );
_freeMMXreg(i); _freeMMXreg(i);
} }
@ -883,7 +882,7 @@ int _signExtendMtoMMX(x86MMXRegType to, u32 mem)
int _signExtendGPRMMXtoMMX(x86MMXRegType to, u32 gprreg, x86MMXRegType from, u32 gprfromreg) int _signExtendGPRMMXtoMMX(x86MMXRegType to, u32 gprreg, x86MMXRegType from, u32 gprfromreg)
{ {
assert( to >= 0 && from >= 0 ); pxAssert( to >= 0 && from >= 0 );
if( !EEINST_ISLIVE1(gprreg) ) { if( !EEINST_ISLIVE1(gprreg) ) {
EEINST_RESETHASLIVE1(gprreg); EEINST_RESETHASLIVE1(gprreg);
if( to != from ) MOVQRtoR(to, from); if( to != from ) MOVQRtoR(to, from);
@ -921,12 +920,12 @@ int _signExtendGPRMMXtoMMX(x86MMXRegType to, u32 gprreg, x86MMXRegType from, u32
return -1; return -1;
} }
assert(0); pxAssert( false );
} }
int _signExtendGPRtoMMX(x86MMXRegType to, u32 gprreg, int shift) int _signExtendGPRtoMMX(x86MMXRegType to, u32 gprreg, int shift)
{ {
assert( to >= 0 && shift >= 0 ); pxAssert( to >= 0 && shift >= 0 );
if( !EEINST_ISLIVE1(gprreg) ) { if( !EEINST_ISLIVE1(gprreg) ) {
if( shift > 0 ) PSRADItoR(to, shift); if( shift > 0 ) PSRADItoR(to, shift);
EEINST_RESETHASLIVE1(gprreg); EEINST_RESETHASLIVE1(gprreg);
@ -970,7 +969,7 @@ int _signExtendGPRtoMMX(x86MMXRegType to, u32 gprreg, int shift)
return -1; return -1;
} }
assert(0); pxAssert( false );
} }
int _allocCheckGPRtoMMX(EEINST* pinst, int reg, int mode) int _allocCheckGPRtoMMX(EEINST* pinst, int reg, int mode)

77
pcsx2/x86/ix86-32/iR5900-32.cpp
View File

@ -115,7 +115,7 @@ void _eeFlushAllUnused()
u32* _eeGetConstReg(int reg) u32* _eeGetConstReg(int reg)
{ {
assert( GPR_IS_CONST1( reg ) ); pxAssert( GPR_IS_CONST1( reg ) );
if( g_cpuFlushedConstReg & (1<<reg) ) if( g_cpuFlushedConstReg & (1<<reg) )
return &cpuRegs.GPR.r[ reg ].UL[0]; return &cpuRegs.GPR.r[ reg ].UL[0];
@ -923,7 +923,7 @@ void SetBranchReg( u32 reg )
recompileNextInstruction(1); recompileNextInstruction(1);
if( x86regs[ESI].inuse ) { if( x86regs[ESI].inuse ) {
assert( x86regs[ESI].type == X86TYPE_PCWRITEBACK ); pxAssert( x86regs[ESI].type == X86TYPE_PCWRITEBACK );
MOV32RtoM((int)&cpuRegs.pc, ESI); MOV32RtoM((int)&cpuRegs.pc, ESI);
x86regs[ESI].inuse = 0; x86regs[ESI].inuse = 0;
} }
@ -947,7 +947,7 @@ void SetBranchImm( u32 imm )
{ {
branch = 1; branch = 1;
assert( imm ); pxAssert( imm );
// end the current block // end the current block
iFlushCall(FLUSH_EVERYTHING); iFlushCall(FLUSH_EVERYTHING);
@ -1163,27 +1163,13 @@ static void iBranchTest(u32 newpc)
*/ */
} }
static void checkcodefn()
{
int pctemp;
#ifdef _MSC_VER
__asm mov pctemp, eax;
#else
__asm__("movl %%eax, %[pctemp]" : [pctemp]"=m"(pctemp) );
#endif
Console.Error("code changed! %x", pctemp);
assert(0);
}
void recompileNextInstruction(int delayslot) void recompileNextInstruction(int delayslot)
{ {
static u8 s_bFlushReg = 1; static u8 s_bFlushReg = 1;
int i, count; int i, count;
s_pCode = (int *)PSM( pc ); s_pCode = (int *)PSM( pc );
assert(s_pCode); pxAssert(s_pCode);
if( IsDebugBuild ) if( IsDebugBuild )
MOV32ItoR(EAX, pc); // acts as a tag for delimiting recompiled instructions when viewing x86 disasm. MOV32ItoR(EAX, pc); // acts as a tag for delimiting recompiled instructions when viewing x86 disasm.
@ -1191,34 +1177,11 @@ void recompileNextInstruction(int delayslot)
cpuRegs.code = *(int *)s_pCode; cpuRegs.code = *(int *)s_pCode;
pc += 4; pc += 4;
#if 0
#ifdef PCSX2_DEBUG
CMP32ItoM((u32)s_pCode, cpuRegs.code);
j8Ptr[0] = JE8(0);
MOV32ItoR(EAX, pc);
CALLFunc((uptr)checkcodefn);
x86SetJ8( j8Ptr[ 0 ] );
if( !delayslot ) {
CMP32ItoM((u32)&cpuRegs.pc, s_pCurBlockEx->startpc);
j8Ptr[0] = JB8(0);
CMP32ItoM((u32)&cpuRegs.pc, pc);
j8Ptr[1] = JA8(0);
j8Ptr[2] = JMP8(0);
x86SetJ8( j8Ptr[ 0 ] );
x86SetJ8( j8Ptr[ 1 ] );
PUSH32I(s_pCurBlockEx->startpc);
ADD32ItoR(ESP, 4);
x86SetJ8( j8Ptr[ 2 ] );
}
#endif
#endif
g_pCurInstInfo++; g_pCurInstInfo++;
for(i = 0; i < iREGCNT_MMX; ++i) { for(i = 0; i < iREGCNT_MMX; ++i) {
if( mmxregs[i].inuse ) { if( mmxregs[i].inuse ) {
assert( MMX_ISGPR(mmxregs[i].reg) ); pxAssert( MMX_ISGPR(mmxregs[i].reg) );
count = _recIsRegWritten(g_pCurInstInfo, (s_nEndBlock-pc)/4 + 1, XMMTYPE_GPRREG, mmxregs[i].reg-MMX_GPR); count = _recIsRegWritten(g_pCurInstInfo, (s_nEndBlock-pc)/4 + 1, XMMTYPE_GPRREG, mmxregs[i].reg-MMX_GPR);
if( count > 0 ) mmxregs[i].counter = 1000-count; if( count > 0 ) mmxregs[i].counter = 1000-count;
else mmxregs[i].counter = 0; else mmxregs[i].counter = 0;
@ -1235,7 +1198,7 @@ void recompileNextInstruction(int delayslot)
const OPCODE& opcode = GetCurrentInstruction(); const OPCODE& opcode = GetCurrentInstruction();
//assert( !(g_pCurInstInfo->info & EEINSTINFO_NOREC) ); //pxAssert( !(g_pCurInstInfo->info & EEINSTINFO_NOREC) );
// if this instruction is a jump or a branch, exit right away // if this instruction is a jump or a branch, exit right away
if( delayslot ) { if( delayslot ) {
@ -1359,7 +1322,7 @@ static void __fastcall recRecompile( const u32 startpc )
iDumpRegisters(startpc, 0); iDumpRegisters(startpc, 0);
#endif #endif
assert( startpc ); pxAssert( startpc );
// if recPtr reached the mem limit reset whole mem // if recPtr reached the mem limit reset whole mem
if ( ( (uptr)recPtr - (uptr)recMem ) >= REC_CACHEMEM-0x40000 || dumplog == 0xffffffff) { if ( ( (uptr)recPtr - (uptr)recMem ) >= REC_CACHEMEM-0x40000 || dumplog == 0xffffffff) {
@ -1380,15 +1343,15 @@ static void __fastcall recRecompile( const u32 startpc )
s_pCurBlock = PC_GETBLOCK(startpc); s_pCurBlock = PC_GETBLOCK(startpc);
assert(s_pCurBlock->GetFnptr() == (uptr)JITCompile pxAssert(s_pCurBlock->GetFnptr() == (uptr)JITCompile
|| s_pCurBlock->GetFnptr() == (uptr)JITCompileInBlock); || s_pCurBlock->GetFnptr() == (uptr)JITCompileInBlock);
s_pCurBlockEx = recBlocks.Get(HWADDR(startpc)); s_pCurBlockEx = recBlocks.Get(HWADDR(startpc));
assert(!s_pCurBlockEx || s_pCurBlockEx->startpc != HWADDR(startpc)); pxAssert(!s_pCurBlockEx || s_pCurBlockEx->startpc != HWADDR(startpc));
s_pCurBlockEx = recBlocks.New(HWADDR(startpc), (uptr)recPtr); s_pCurBlockEx = recBlocks.New(HWADDR(startpc), (uptr)recPtr);
assert(s_pCurBlockEx); pxAssert(s_pCurBlockEx);
branch = 0; branch = 0;
@ -1399,7 +1362,7 @@ static void __fastcall recRecompile( const u32 startpc )
g_cpuHasConstReg = g_cpuFlushedConstReg = 1; g_cpuHasConstReg = g_cpuFlushedConstReg = 1;
g_cpuPrevRegHasLive1 = g_cpuRegHasLive1 = 0xffffffff; g_cpuPrevRegHasLive1 = g_cpuRegHasLive1 = 0xffffffff;
g_cpuPrevRegHasSignExt = g_cpuRegHasSignExt = 0; g_cpuPrevRegHasSignExt = g_cpuRegHasSignExt = 0;
assert( g_cpuConstRegs[0].UD[0] == 0 ); pxAssert( g_cpuConstRegs[0].UD[0] == 0 );
_initX86regs(); _initX86regs();
_initXMMregs(); _initXMMregs();
@ -1516,7 +1479,7 @@ StartRecomp:
free(s_pInstCache); free(s_pInstCache);
s_nInstCacheSize = (s_nEndBlock-startpc)/4+10; s_nInstCacheSize = (s_nEndBlock-startpc)/4+10;
s_pInstCache = (EEINST*)malloc(sizeof(EEINST)*s_nInstCacheSize); s_pInstCache = (EEINST*)malloc(sizeof(EEINST)*s_nInstCacheSize);
assert( s_pInstCache != NULL ); pxAssert( s_pInstCache != NULL );
} }
pcur = s_pInstCache + (s_nEndBlock-startpc)/4; pcur = s_pInstCache + (s_nEndBlock-startpc)/4;
@ -1675,7 +1638,7 @@ StartRecomp:
iDumpBlock(startpc, recPtr); iDumpBlock(startpc, recPtr);
#endif #endif
assert( (pc-startpc)>>2 <= 0xffff ); pxAssert( (pc-startpc)>>2 <= 0xffff );
s_pCurBlockEx->size = (pc-startpc)>>2; s_pCurBlockEx->size = (pc-startpc)>>2;
if (HWADDR(pc) <= Ps2MemSize::Base) { if (HWADDR(pc) <= Ps2MemSize::Base) {
@ -1694,7 +1657,7 @@ StartRecomp:
oldBlock->size * 4)) { oldBlock->size * 4)) {
recClear(startpc, (pc - startpc) / 4); recClear(startpc, (pc - startpc) / 4);
s_pCurBlockEx = recBlocks.Get(HWADDR(startpc)); s_pCurBlockEx = recBlocks.Get(HWADDR(startpc));
assert(s_pCurBlockEx->startpc == HWADDR(startpc)); pxAssert(s_pCurBlockEx->startpc == HWADDR(startpc));
break; break;
} }
} }
@ -1726,7 +1689,7 @@ StartRecomp:
else else
{ {
if( branch ) if( branch )
assert( !willbranch3 ); pxAssert( !willbranch3 );
if( willbranch3 || !branch) { if( willbranch3 || !branch) {
@ -1750,16 +1713,16 @@ StartRecomp:
} }
} }
assert( x86Ptr < recMem+REC_CACHEMEM ); pxAssert( x86Ptr < recMem+REC_CACHEMEM );
assert( recConstBufPtr < recConstBuf + RECCONSTBUF_SIZE ); pxAssert( recConstBufPtr < recConstBuf + RECCONSTBUF_SIZE );
assert( x86FpuState == 0 ); pxAssert( x86FpuState == 0 );
assert(x86Ptr - recPtr < 0x10000); pxAssert(x86Ptr - recPtr < 0x10000);
s_pCurBlockEx->x86size = x86Ptr - recPtr; s_pCurBlockEx->x86size = x86Ptr - recPtr;
recPtr = x86Ptr; recPtr = x86Ptr;
assert( (g_cpuHasConstReg&g_cpuFlushedConstReg) == g_cpuHasConstReg ); pxAssert( (g_cpuHasConstReg&g_cpuFlushedConstReg) == g_cpuHasConstReg );
s_pCurBlock = NULL; s_pCurBlock = NULL;
s_pCurBlockEx = NULL; s_pCurBlockEx = NULL;

38
pcsx2/x86/ix86-32/iR5900Arit.cpp
View File

@ -63,7 +63,7 @@ void recADD_const()
void recADD_constv(int info, int creg, int vreg) void recADD_constv(int info, int creg, int vreg)
{ {
assert( !(info&PROCESS_EE_XMM) ); pxAssert( !(info&PROCESS_EE_XMM) );
if( info & PROCESS_EE_MMX ) { if( info & PROCESS_EE_MMX ) {
int mmreg = vreg == _Rt_ ? EEREC_T : EEREC_S; int mmreg = vreg == _Rt_ ? EEREC_T : EEREC_S;
@ -165,7 +165,7 @@ void recADD_constt(int info)
// nothing is constant // nothing is constant
void recADD_(int info) void recADD_(int info)
{ {
assert( !(info&PROCESS_EE_XMM) ); pxAssert( !(info&PROCESS_EE_XMM) );
EEINST_SETSIGNEXT(_Rd_); EEINST_SETSIGNEXT(_Rd_);
EEINST_SETSIGNEXT(_Rs_); EEINST_SETSIGNEXT(_Rs_);
EEINST_SETSIGNEXT(_Rt_); EEINST_SETSIGNEXT(_Rt_);
@ -253,7 +253,7 @@ void recDADD_const( void )
void recDADD_constv(int info, int creg, int vreg) void recDADD_constv(int info, int creg, int vreg)
{ {
assert( !(info&PROCESS_EE_XMM) ); pxAssert( !(info&PROCESS_EE_XMM) );
if( info & PROCESS_EE_MMX ) { if( info & PROCESS_EE_MMX ) {
int mmreg = vreg == _Rt_ ? EEREC_T : EEREC_S; int mmreg = vreg == _Rt_ ? EEREC_T : EEREC_S;
@ -336,7 +336,7 @@ void recDADD_constt(int info)
void recDADD_(int info) void recDADD_(int info)
{ {
assert( !(info&PROCESS_EE_XMM) ); pxAssert( !(info&PROCESS_EE_XMM) );
if( info & PROCESS_EE_MMX ) { if( info & PROCESS_EE_MMX ) {
@ -402,7 +402,7 @@ void recSUB_const()
void recSUB_consts(int info) void recSUB_consts(int info)
{ {
assert( !(info&PROCESS_EE_XMM) ); pxAssert( !(info&PROCESS_EE_XMM) );
EEINST_SETSIGNEXT(_Rt_); EEINST_SETSIGNEXT(_Rt_);
EEINST_SETSIGNEXT(_Rd_); EEINST_SETSIGNEXT(_Rd_);
@ -485,7 +485,7 @@ void recSUB_consts(int info)
void recSUB_constt(int info) void recSUB_constt(int info)
{ {
assert( !(info&PROCESS_EE_XMM) ); pxAssert( !(info&PROCESS_EE_XMM) );
EEINST_SETSIGNEXT(_Rs_); EEINST_SETSIGNEXT(_Rs_);
EEINST_SETSIGNEXT(_Rd_); EEINST_SETSIGNEXT(_Rd_);
@ -563,7 +563,7 @@ void recSUB_constt(int info)
void recSUB_(int info) void recSUB_(int info)
{ {
assert( !(info&PROCESS_EE_XMM) ); pxAssert( !(info&PROCESS_EE_XMM) );
EEINST_SETSIGNEXT(_Rs_); EEINST_SETSIGNEXT(_Rs_);
EEINST_SETSIGNEXT(_Rt_); EEINST_SETSIGNEXT(_Rt_);
EEINST_SETSIGNEXT(_Rd_); EEINST_SETSIGNEXT(_Rd_);
@ -646,7 +646,7 @@ void recDSUB_const()
void recDSUB_consts(int info) void recDSUB_consts(int info)
{ {
assert( !(info&PROCESS_EE_XMM) ); pxAssert( !(info&PROCESS_EE_XMM) );
if( info & PROCESS_EE_MMX ) { if( info & PROCESS_EE_MMX ) {
@ -748,7 +748,7 @@ void recDSUB_consts(int info)
void recDSUB_constt(int info) void recDSUB_constt(int info)
{ {
assert( !(info&PROCESS_EE_XMM) ); pxAssert( !(info&PROCESS_EE_XMM) );
if( info & PROCESS_EE_MMX ) { if( info & PROCESS_EE_MMX ) {
@ -803,7 +803,7 @@ void recDSUB_constt(int info)
void recDSUB_(int info) void recDSUB_(int info)
{ {
assert( !(info&PROCESS_EE_XMM) ); pxAssert( !(info&PROCESS_EE_XMM) );
if( info & PROCESS_EE_MMX ) { if( info & PROCESS_EE_MMX ) {
@ -873,7 +873,7 @@ void recAND_const()
void recAND_constv(int info, int creg, int vreg) void recAND_constv(int info, int creg, int vreg)
{ {
assert( !(info & PROCESS_EE_XMM) ); pxAssert( !(info & PROCESS_EE_XMM) );
if( info & PROCESS_EE_MMX ) { if( info & PROCESS_EE_MMX ) {
int mmreg = vreg == _Rt_ ? EEREC_T : EEREC_S; int mmreg = vreg == _Rt_ ? EEREC_T : EEREC_S;
@ -944,7 +944,7 @@ void recAND_constt(int info)
void recLogicalOp(int info, int op) void recLogicalOp(int info, int op)
{ {
assert( !(info & PROCESS_EE_XMM) ); pxAssert( !(info & PROCESS_EE_XMM) );
if( info & PROCESS_EE_MMX ) { if( info & PROCESS_EE_MMX ) {
if( EEREC_D == EEREC_S ) LogicalOpRtoR(EEREC_D, EEREC_T, op); if( EEREC_D == EEREC_S ) LogicalOpRtoR(EEREC_D, EEREC_T, op);
@ -1034,7 +1034,7 @@ void recOR_const()
void recOR_constv(int info, int creg, int vreg) void recOR_constv(int info, int creg, int vreg)
{ {
assert( !(info & PROCESS_EE_XMM) ); pxAssert( !(info & PROCESS_EE_XMM) );
if( info & PROCESS_EE_MMX ) { if( info & PROCESS_EE_MMX ) {
int mmreg = vreg == _Rt_ ? EEREC_T : EEREC_S; int mmreg = vreg == _Rt_ ? EEREC_T : EEREC_S;
@ -1112,7 +1112,7 @@ void recXOR_const()
void recXOR_constv(int info, int creg, int vreg) void recXOR_constv(int info, int creg, int vreg)
{ {
assert( !(info & PROCESS_EE_XMM) ); pxAssert( !(info & PROCESS_EE_XMM) );
if( info & PROCESS_EE_MMX ) { if( info & PROCESS_EE_MMX ) {
int mmreg = vreg == _Rt_ ? EEREC_T : EEREC_S; int mmreg = vreg == _Rt_ ? EEREC_T : EEREC_S;
@ -1189,7 +1189,7 @@ void recNOR_const()
void recNOR_constv(int info, int creg, int vreg) void recNOR_constv(int info, int creg, int vreg)
{ {
assert( !(info & PROCESS_EE_XMM) ); pxAssert( !(info & PROCESS_EE_XMM) );
if( info & PROCESS_EE_MMX ) { if( info & PROCESS_EE_MMX ) {
int mmreg = vreg == _Rt_ ? EEREC_T : EEREC_S; int mmreg = vreg == _Rt_ ? EEREC_T : EEREC_S;
@ -1285,7 +1285,7 @@ u32 s_sltone = 1;
void recSLTs_consts(int info, int sign) void recSLTs_consts(int info, int sign)
{ {
assert( !(info & PROCESS_EE_XMM) ); pxAssert( !(info & PROCESS_EE_XMM) );
if( info & PROCESS_EE_MMX ) { if( info & PROCESS_EE_MMX ) {
@ -1419,7 +1419,7 @@ void recSLTmemconstt(int regd, int regs, u32 mem, int sign)
void recSLTs_constt(int info, int sign) void recSLTs_constt(int info, int sign)
{ {
assert( !(info & PROCESS_EE_XMM) ); pxAssert( !(info & PROCESS_EE_XMM) );
if( info & PROCESS_EE_MMX ) { if( info & PROCESS_EE_MMX ) {
if( _Rs_ == _Rt_ ) { if( _Rs_ == _Rt_ ) {
@ -1528,7 +1528,7 @@ void recSLT_constt(int info)
void recSLT_(int info) void recSLT_(int info)
{ {
int t0reg; int t0reg;
assert( !(info & PROCESS_EE_XMM) ); pxAssert( !(info & PROCESS_EE_XMM) );
if( !(info & PROCESS_EE_MMX) ) { if( !(info & PROCESS_EE_MMX) ) {
recSLTs_(info, 1); recSLTs_(info, 1);
@ -1601,7 +1601,7 @@ void recSLTU_(int info)
{ {
int t1reg; int t1reg;
assert( !(info & PROCESS_EE_XMM) ); pxAssert( !(info & PROCESS_EE_XMM) );
EEINST_SETSIGNEXT(_Rd_); EEINST_SETSIGNEXT(_Rd_);
if( !(info & PROCESS_EE_MMX) ) { if( !(info & PROCESS_EE_MMX) ) {

4
pcsx2/x86/ix86-32/iR5900AritImm.cpp
View File

@ -55,7 +55,7 @@ void recADDI_const( void )
void recADDI_(int info) void recADDI_(int info)
{ {
assert( !(info&PROCESS_EE_XMM) ); pxAssert( !(info&PROCESS_EE_XMM) );
EEINST_SETSIGNEXT(_Rt_); EEINST_SETSIGNEXT(_Rt_);
EEINST_SETSIGNEXT(_Rs_); EEINST_SETSIGNEXT(_Rs_);
@ -146,7 +146,7 @@ void recDADDI_const( void )
void recDADDI_(int info) void recDADDI_(int info)
{ {
assert( !(info&PROCESS_EE_XMM) ); pxAssert( !(info&PROCESS_EE_XMM) );
if( info & PROCESS_EE_MMX ) { if( info & PROCESS_EE_MMX ) {

2
pcsx2/x86/ix86-32/iR5900Jump.cpp
View File

@ -113,7 +113,7 @@ void recJALR( void )
recompileNextInstruction(1); recompileNextInstruction(1);
if( x86regs[ESI].inuse ) { if( x86regs[ESI].inuse ) {
assert( x86regs[ESI].type == X86TYPE_PCWRITEBACK ); pxAssert( x86regs[ESI].type == X86TYPE_PCWRITEBACK );
MOV32RtoM((int)&cpuRegs.pc, ESI); MOV32RtoM((int)&cpuRegs.pc, ESI);
x86regs[ESI].inuse = 0; x86regs[ESI].inuse = 0;
} }

4
pcsx2/x86/ix86-32/iR5900Move.cpp
View File

@ -96,7 +96,7 @@ void recMFHILO(int hi)
if( reghi >= 0 ) { if( reghi >= 0 ) {
if( regd >= 0 ) { if( regd >= 0 ) {
assert( regd != reghi ); pxAssert( regd != reghi );
xmmregs[regd].inuse = 0; xmmregs[regd].inuse = 0;
@ -191,7 +191,7 @@ void recMTHILO(int hi)
if( reghi >= 0 ) { if( reghi >= 0 ) {
if( regs >= 0 ) { if( regs >= 0 ) {
assert( reghi != regs ); pxAssert( reghi != regs );
_deleteGPRtoXMMreg(_Rs_, 0); _deleteGPRtoXMMreg(_Rs_, 0);
SSE2_PUNPCKHQDQ_XMM_to_XMM(reghi, reghi); SSE2_PUNPCKHQDQ_XMM_to_XMM(reghi, reghi);

4
pcsx2/x86/ix86-32/iR5900MultDiv.cpp
View File

@ -317,7 +317,7 @@ void recMULT_const()
void recMULTUsuper(int info, int upper, int process); void recMULTUsuper(int info, int upper, int process);
void recMULTsuper(int info, int upper, int process) void recMULTsuper(int info, int upper, int process)
{ {
assert( !(info&PROCESS_EE_MMX) ); pxAssert( !(info&PROCESS_EE_MMX) );
if( _Rd_ ) EEINST_SETSIGNEXT(_Rd_); if( _Rd_ ) EEINST_SETSIGNEXT(_Rd_);
EEINST_SETSIGNEXT(_Rs_); EEINST_SETSIGNEXT(_Rs_);
EEINST_SETSIGNEXT(_Rt_); EEINST_SETSIGNEXT(_Rt_);
@ -429,7 +429,7 @@ void recMULTUsuper(int info, int upper, int process)
if( !_Rd_ ) { if( !_Rd_ ) {
// need some temp reg // need some temp reg
int t0reg = _allocMMXreg(-1, MMX_TEMP, 0); int t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
assert( EEREC_D == 0 ); pxAssert( EEREC_D == 0 );
info |= PROCESS_EE_SET_D(t0reg); info |= PROCESS_EE_SET_D(t0reg);
} }

20
pcsx2/x86/ix86-32/iR5900Shift.cpp
View File

@ -62,7 +62,7 @@ void recSLL_const()
void recSLLs_(int info, int sa) void recSLLs_(int info, int sa)
{ {
int rtreg, rdreg, t0reg; int rtreg, rdreg, t0reg;
assert( !(info & PROCESS_EE_XMM) ); pxAssert( !(info & PROCESS_EE_XMM) );
if( info & PROCESS_EE_MMX ) { if( info & PROCESS_EE_MMX ) {
rtreg = EEREC_T; rtreg = EEREC_T;
@ -136,7 +136,7 @@ void recSRL_const()
void recSRLs_(int info, int sa) void recSRLs_(int info, int sa)
{ {
int rtreg, rdreg; int rtreg, rdreg;
assert( !(info & PROCESS_EE_XMM) ); pxAssert( !(info & PROCESS_EE_XMM) );
if( info & PROCESS_EE_MMX ) { if( info & PROCESS_EE_MMX ) {
rtreg = EEREC_T; rtreg = EEREC_T;
@ -210,7 +210,7 @@ void recSRA_const()
void recSRAs_(int info, int sa) void recSRAs_(int info, int sa)
{ {
int rtreg, rdreg, t0reg; int rtreg, rdreg, t0reg;
assert( !(info & PROCESS_EE_XMM) ); pxAssert( !(info & PROCESS_EE_XMM) );
if( info & PROCESS_EE_MMX ) { if( info & PROCESS_EE_MMX ) {
rtreg = EEREC_T; rtreg = EEREC_T;
@ -289,7 +289,7 @@ void recDSLL_const()
void recDSLLs_(int info, int sa) void recDSLLs_(int info, int sa)
{ {
int rtreg, rdreg; int rtreg, rdreg;
assert( !(info & PROCESS_EE_XMM) ); pxAssert( !(info & PROCESS_EE_XMM) );
if( info & PROCESS_EE_MMX ) { if( info & PROCESS_EE_MMX ) {
rtreg = EEREC_T; rtreg = EEREC_T;
@ -323,7 +323,7 @@ void recDSRL_const()
void recDSRLs_(int info, int sa) void recDSRLs_(int info, int sa)
{ {
int rtreg, rdreg; int rtreg, rdreg;
assert( !(info & PROCESS_EE_XMM) ); pxAssert( !(info & PROCESS_EE_XMM) );
if( info & PROCESS_EE_MMX ) { if( info & PROCESS_EE_MMX ) {
rtreg = EEREC_T; rtreg = EEREC_T;
@ -357,7 +357,7 @@ void recDSRA_const()
void recDSRAs_(int info, int sa) void recDSRAs_(int info, int sa)
{ {
int rtreg, rdreg, t0reg; int rtreg, rdreg, t0reg;
assert( !(info & PROCESS_EE_XMM) ); pxAssert( !(info & PROCESS_EE_XMM) );
if( info & PROCESS_EE_MMX ) { if( info & PROCESS_EE_MMX ) {
rtreg = EEREC_T; rtreg = EEREC_T;
@ -416,7 +416,7 @@ void recDSLL32_const()
void recDSLL32s_(int info, int sa) void recDSLL32s_(int info, int sa)
{ {
int rtreg, rdreg; int rtreg, rdreg;
assert( !(info & PROCESS_EE_XMM) ); pxAssert( !(info & PROCESS_EE_XMM) );
if( info & PROCESS_EE_MMX ) { if( info & PROCESS_EE_MMX ) {
rtreg = EEREC_T; rtreg = EEREC_T;
@ -460,7 +460,7 @@ void recDSRL32_const()
void recDSRL32s_(int info, int sa) void recDSRL32s_(int info, int sa)
{ {
int rtreg, rdreg; int rtreg, rdreg;
assert( !(info & PROCESS_EE_XMM) ); pxAssert( !(info & PROCESS_EE_XMM) );
if( info & PROCESS_EE_MMX ) { if( info & PROCESS_EE_MMX ) {
rtreg = EEREC_T; rtreg = EEREC_T;
@ -503,7 +503,7 @@ void recDSRA32_const()
void recDSRA32s_(int info, int sa) void recDSRA32s_(int info, int sa)
{ {
int rtreg, rdreg, t0reg; int rtreg, rdreg, t0reg;
assert( !(info & PROCESS_EE_XMM) ); pxAssert( !(info & PROCESS_EE_XMM) );
if( info & PROCESS_EE_MMX ) { if( info & PROCESS_EE_MMX ) {
rtreg = EEREC_T; rtreg = EEREC_T;
@ -582,7 +582,7 @@ __aligned16 u32 s_sa[4] = {0x1f, 0, 0x3f, 0};
int recSetShiftV(int info, int* rsreg, int* rtreg, int* rdreg, int* rstemp, int forcemmx, int shift64) int recSetShiftV(int info, int* rsreg, int* rtreg, int* rdreg, int* rstemp, int forcemmx, int shift64)
{ {
assert( !(info & PROCESS_EE_XMM) ); pxAssert( !(info & PROCESS_EE_XMM) );
if( info & PROCESS_EE_MMX ) { if( info & PROCESS_EE_MMX ) {
*rtreg = EEREC_T; *rtreg = EEREC_T;

16
pcsx2/x86/ix86-32/iR5900Templates.cpp
View File

@ -599,7 +599,8 @@ void eeRecompileCode2(R5900FNPTR constcode, R5900FNPTR_INFO noconstcode)
// rt op rs // rt op rs
void eeRecompileCode3(R5900FNPTR constcode, R5900FNPTR_INFO multicode) void eeRecompileCode3(R5900FNPTR constcode, R5900FNPTR_INFO multicode)
{ {
assert(0); pxFail( "Unfinished code reached." );
// for now, don't support xmm // for now, don't support xmm
_deleteEEreg(_Rs_, 1); _deleteEEreg(_Rs_, 1);
_deleteEEreg(_Rt_, 1); _deleteEEreg(_Rt_, 1);
@ -704,7 +705,8 @@ void eeRecompileCodeConst2(R5900FNPTR constcode, R5900FNPTR_INFO noconstcode)
// rd = rt MULT rs (SPECIAL) // rd = rt MULT rs (SPECIAL)
void eeRecompileCodeConstSPECIAL(R5900FNPTR constcode, R5900FNPTR_INFO multicode, int MULT) void eeRecompileCodeConstSPECIAL(R5900FNPTR constcode, R5900FNPTR_INFO multicode, int MULT)
{ {
assert(0); pxFail( "Unfinished code reached." );
// for now, don't support xmm // for now, don't support xmm
if( MULT ) { if( MULT ) {
_deleteGPRtoXMMreg(_Rd_, 0); _deleteGPRtoXMMreg(_Rd_, 0);
@ -860,7 +862,7 @@ void eeFPURecompileCode(R5900FNPTR_INFO xmmcode, R5900FNPTR fpucode, int xmminfo
if( mmregt >= 0 ) info |= PROCESS_EE_SETMODET_XMM(mmregt); if( mmregt >= 0 ) info |= PROCESS_EE_SETMODET_XMM(mmregt);
if( xmminfo & XMMINFO_READD ) { if( xmminfo & XMMINFO_READD ) {
assert( xmminfo & XMMINFO_WRITED ); pxAssert( xmminfo & XMMINFO_WRITED );
mmregd = _allocFPtoXMMreg(-1, _Fd_, MODE_READ); mmregd = _allocFPtoXMMreg(-1, _Fd_, MODE_READ);
} }
@ -950,15 +952,15 @@ void eeFPURecompileCode(R5900FNPTR_INFO xmmcode, R5900FNPTR fpucode, int xmminfo
} }
} }
assert( mmregs >= 0 || mmregt >= 0 || mmregd >= 0 || mmregacc >= 0 ); pxAssert( mmregs >= 0 || mmregt >= 0 || mmregd >= 0 || mmregacc >= 0 );
if( xmminfo & XMMINFO_WRITED ) { if( xmminfo & XMMINFO_WRITED ) {
assert( mmregd >= 0 ); pxAssert( mmregd >= 0 );
info |= PROCESS_EE_SET_D(mmregd); info |= PROCESS_EE_SET_D(mmregd);
} }
if( xmminfo & (XMMINFO_WRITEACC|XMMINFO_READACC) ) { if( xmminfo & (XMMINFO_WRITEACC|XMMINFO_READACC) ) {
if( mmregacc >= 0 ) info |= PROCESS_EE_SET_ACC(mmregacc)|PROCESS_EE_ACC; if( mmregacc >= 0 ) info |= PROCESS_EE_SET_ACC(mmregacc)|PROCESS_EE_ACC;
else assert( !(xmminfo&XMMINFO_WRITEACC)); else pxAssert( !(xmminfo&XMMINFO_WRITEACC));
} }
if( xmminfo & XMMINFO_READS ) { if( xmminfo & XMMINFO_READS ) {
@ -970,7 +972,7 @@ void eeFPURecompileCode(R5900FNPTR_INFO xmmcode, R5900FNPTR fpucode, int xmminfo
// at least one must be in xmm // at least one must be in xmm
if( (xmminfo & (XMMINFO_READS|XMMINFO_READT)) == (XMMINFO_READS|XMMINFO_READT) ) { if( (xmminfo & (XMMINFO_READS|XMMINFO_READT)) == (XMMINFO_READS|XMMINFO_READT) ) {
assert( mmregs >= 0 || mmregt >= 0 ); pxAssert( mmregs >= 0 || mmregt >= 0 );
} }
xmmcode(info); xmmcode(info);

30
pcsx2/x86/sVU_Lower.cpp
View File

@ -602,7 +602,7 @@ void recVUMI_MR32( VURegs *VU, int info )
//------------------------------------------------------------------ //------------------------------------------------------------------
void _loadEAX(VURegs *VU, int x86reg, uptr offset, int info) void _loadEAX(VURegs *VU, int x86reg, uptr offset, int info)
{ {
assert( offset < 0x80000000 ); pxAssert( offset < 0x80000000 );
if( x86reg >= 0 ) { if( x86reg >= 0 ) {
switch(_X_Y_Z_W) { switch(_X_Y_Z_W) {
@ -788,7 +788,7 @@ void recVUMI_LQI(VURegs *VU, int info)
//------------------------------------------------------------------ //------------------------------------------------------------------
void _saveEAX(VURegs *VU, int x86reg, uptr offset, int info) void _saveEAX(VURegs *VU, int x86reg, uptr offset, int info)
{ {
assert( offset < 0x80000000 ); pxAssert( offset < 0x80000000 );
if ( _Fs_ == 0 ) { if ( _Fs_ == 0 ) {
if ( _XYZW_SS ) { if ( _XYZW_SS ) {
@ -1591,7 +1591,7 @@ void vuSqSumXYZ(int regd, int regs, int regtemp) // regd.x = x ^ 2 + y ^ 2 + z
void recVUMI_ESADD( VURegs *VU, int info) void recVUMI_ESADD( VURegs *VU, int info)
{ {
//Console.WriteLn("VU: ESADD"); //Console.WriteLn("VU: ESADD");
assert( VU == &VU1 ); pxAssert( VU == &VU1 );
if( EEREC_TEMP == EEREC_D ) { // special code to reset P ( FixMe: don't know if this is still needed! (cottonvibes) ) if( EEREC_TEMP == EEREC_D ) { // special code to reset P ( FixMe: don't know if this is still needed! (cottonvibes) )
Console.Notice("ESADD: Resetting P reg!!!\n"); Console.Notice("ESADD: Resetting P reg!!!\n");
MOV32ItoM(VU_VI_ADDR(REG_P, 0), 0); MOV32ItoM(VU_VI_ADDR(REG_P, 0), 0);
@ -1610,7 +1610,7 @@ void recVUMI_ESADD( VURegs *VU, int info)
void recVUMI_ERSADD( VURegs *VU, int info ) void recVUMI_ERSADD( VURegs *VU, int info )
{ {
//Console.WriteLn("VU: ERSADD"); //Console.WriteLn("VU: ERSADD");
assert( VU == &VU1 ); pxAssert( VU == &VU1 );
vuSqSumXYZ(EEREC_D, EEREC_S, EEREC_TEMP); vuSqSumXYZ(EEREC_D, EEREC_S, EEREC_TEMP);
// don't use RCPSS (very bad precision) // don't use RCPSS (very bad precision)
SSE_MOVSS_M32_to_XMM(EEREC_TEMP, (uptr)VU_ONE); SSE_MOVSS_M32_to_XMM(EEREC_TEMP, (uptr)VU_ONE);
@ -1627,7 +1627,7 @@ void recVUMI_ERSADD( VURegs *VU, int info )
void recVUMI_ELENG( VURegs *VU, int info ) void recVUMI_ELENG( VURegs *VU, int info )
{ {
//Console.WriteLn("VU: ELENG"); //Console.WriteLn("VU: ELENG");
assert( VU == &VU1 ); pxAssert( VU == &VU1 );
vuSqSumXYZ(EEREC_D, EEREC_S, EEREC_TEMP); vuSqSumXYZ(EEREC_D, EEREC_S, EEREC_TEMP);
if (CHECK_VU_OVERFLOW) SSE_MINSS_M32_to_XMM(EEREC_D, (uptr)g_maxvals); // Only need to do positive clamp since (x ^ 2 + y ^ 2 + z ^ 2) is positive if (CHECK_VU_OVERFLOW) SSE_MINSS_M32_to_XMM(EEREC_D, (uptr)g_maxvals); // Only need to do positive clamp since (x ^ 2 + y ^ 2 + z ^ 2) is positive
SSE_SQRTSS_XMM_to_XMM(EEREC_D, EEREC_D); SSE_SQRTSS_XMM_to_XMM(EEREC_D, EEREC_D);
@ -1642,7 +1642,7 @@ void recVUMI_ELENG( VURegs *VU, int info )
void recVUMI_ERLENG( VURegs *VU, int info ) void recVUMI_ERLENG( VURegs *VU, int info )
{ {
//Console.WriteLn("VU: ERLENG"); //Console.WriteLn("VU: ERLENG");
assert( VU == &VU1 ); pxAssert( VU == &VU1 );
vuSqSumXYZ(EEREC_D, EEREC_S, EEREC_TEMP); vuSqSumXYZ(EEREC_D, EEREC_S, EEREC_TEMP);
if (CHECK_VU_OVERFLOW) SSE_MINSS_M32_to_XMM(EEREC_D, (uptr)g_maxvals); // Only need to do positive clamp since (x ^ 2 + y ^ 2 + z ^ 2) is positive if (CHECK_VU_OVERFLOW) SSE_MINSS_M32_to_XMM(EEREC_D, (uptr)g_maxvals); // Only need to do positive clamp since (x ^ 2 + y ^ 2 + z ^ 2) is positive
SSE_SQRTSS_XMM_to_XMM(EEREC_D, EEREC_D); // regd <- sqrt(x^2 + y^2 + z^2) SSE_SQRTSS_XMM_to_XMM(EEREC_D, EEREC_D); // regd <- sqrt(x^2 + y^2 + z^2)
@ -1659,7 +1659,7 @@ void recVUMI_ERLENG( VURegs *VU, int info )
//------------------------------------------------------------------ //------------------------------------------------------------------
void recVUMI_EATANxy( VURegs *VU, int info ) void recVUMI_EATANxy( VURegs *VU, int info )
{ {
assert( VU == &VU1 ); pxAssert( VU == &VU1 );
//Console.WriteLn("recVUMI_EATANxy"); //Console.WriteLn("recVUMI_EATANxy");
if( (xmmregs[EEREC_S].mode & MODE_WRITE) && (xmmregs[EEREC_S].mode&MODE_NOFLUSH) ) { if( (xmmregs[EEREC_S].mode & MODE_WRITE) && (xmmregs[EEREC_S].mode&MODE_NOFLUSH) ) {
SSE_MOVLPS_XMM_to_M64((uptr)s_tempmem, EEREC_S); SSE_MOVLPS_XMM_to_M64((uptr)s_tempmem, EEREC_S);
@ -1687,7 +1687,7 @@ void recVUMI_EATANxy( VURegs *VU, int info )
//------------------------------------------------------------------ //------------------------------------------------------------------
void recVUMI_EATANxz( VURegs *VU, int info ) void recVUMI_EATANxz( VURegs *VU, int info )
{ {
assert( VU == &VU1 ); pxAssert( VU == &VU1 );
//Console.WriteLn("recVUMI_EATANxz"); //Console.WriteLn("recVUMI_EATANxz");
if( (xmmregs[EEREC_S].mode & MODE_WRITE) && (xmmregs[EEREC_S].mode&MODE_NOFLUSH) ) { if( (xmmregs[EEREC_S].mode & MODE_WRITE) && (xmmregs[EEREC_S].mode&MODE_NOFLUSH) ) {
SSE_MOVLPS_XMM_to_M64((uptr)s_tempmem, EEREC_S); SSE_MOVLPS_XMM_to_M64((uptr)s_tempmem, EEREC_S);
@ -1715,7 +1715,7 @@ void recVUMI_EATANxz( VURegs *VU, int info )
void recVUMI_ESUM( VURegs *VU, int info ) void recVUMI_ESUM( VURegs *VU, int info )
{ {
//Console.WriteLn("VU: ESUM"); //Console.WriteLn("VU: ESUM");
assert( VU == &VU1 ); pxAssert( VU == &VU1 );
if( x86caps.hasStreamingSIMD3Extensions ) { if( x86caps.hasStreamingSIMD3Extensions ) {
SSE_MOVAPS_XMM_to_XMM(EEREC_TEMP, EEREC_S); SSE_MOVAPS_XMM_to_XMM(EEREC_TEMP, EEREC_S);
@ -1742,7 +1742,7 @@ void recVUMI_ESUM( VURegs *VU, int info )
//------------------------------------------------------------------ //------------------------------------------------------------------
void recVUMI_ERCPR( VURegs *VU, int info ) void recVUMI_ERCPR( VURegs *VU, int info )
{ {
assert( VU == &VU1 ); pxAssert( VU == &VU1 );
//Console.WriteLn("VU1: ERCPR"); //Console.WriteLn("VU1: ERCPR");
// don't use RCPSS (very bad precision) // don't use RCPSS (very bad precision)
@ -1786,7 +1786,7 @@ void recVUMI_ERCPR( VURegs *VU, int info )
//------------------------------------------------------------------ //------------------------------------------------------------------
void recVUMI_ESQRT( VURegs *VU, int info ) void recVUMI_ESQRT( VURegs *VU, int info )
{ {
assert( VU == &VU1 ); pxAssert( VU == &VU1 );
//Console.WriteLn("VU1: ESQRT"); //Console.WriteLn("VU1: ESQRT");
_unpackVFSS_xyzw(EEREC_TEMP, EEREC_S, _Fsf_); _unpackVFSS_xyzw(EEREC_TEMP, EEREC_S, _Fsf_);
@ -1806,7 +1806,7 @@ void recVUMI_ERSQRT( VURegs *VU, int info )
{ {
int t1reg = _vuGetTempXMMreg(info); int t1reg = _vuGetTempXMMreg(info);
assert( VU == &VU1 ); pxAssert( VU == &VU1 );
//Console.WriteLn("VU1: ERSQRT"); //Console.WriteLn("VU1: ERSQRT");
_unpackVFSS_xyzw(EEREC_TEMP, EEREC_S, _Fsf_); _unpackVFSS_xyzw(EEREC_TEMP, EEREC_S, _Fsf_);
@ -1839,7 +1839,7 @@ void recVUMI_ERSQRT( VURegs *VU, int info )
//------------------------------------------------------------------ //------------------------------------------------------------------
void recVUMI_ESIN( VURegs *VU, int info ) void recVUMI_ESIN( VURegs *VU, int info )
{ {
assert( VU == &VU1 ); pxAssert( VU == &VU1 );
//Console.WriteLn("recVUMI_ESIN"); //Console.WriteLn("recVUMI_ESIN");
if( (xmmregs[EEREC_S].mode & MODE_WRITE) && (xmmregs[EEREC_S].mode&MODE_NOFLUSH) ) { if( (xmmregs[EEREC_S].mode & MODE_WRITE) && (xmmregs[EEREC_S].mode&MODE_NOFLUSH) ) {
@ -1870,7 +1870,7 @@ void recVUMI_ESIN( VURegs *VU, int info )
//------------------------------------------------------------------ //------------------------------------------------------------------
void recVUMI_EATAN( VURegs *VU, int info ) void recVUMI_EATAN( VURegs *VU, int info )
{ {
assert( VU == &VU1 ); pxAssert( VU == &VU1 );
//Console.WriteLn("recVUMI_EATAN"); //Console.WriteLn("recVUMI_EATAN");
if( (xmmregs[EEREC_S].mode & MODE_WRITE) && (xmmregs[EEREC_S].mode&MODE_NOFLUSH) ) { if( (xmmregs[EEREC_S].mode & MODE_WRITE) && (xmmregs[EEREC_S].mode&MODE_NOFLUSH) ) {
@ -1901,7 +1901,7 @@ void recVUMI_EATAN( VURegs *VU, int info )
//------------------------------------------------------------------ //------------------------------------------------------------------
void recVUMI_EEXP( VURegs *VU, int info ) void recVUMI_EEXP( VURegs *VU, int info )
{ {
assert( VU == &VU1 ); pxAssert( VU == &VU1 );
//Console.WriteLn("recVUMI_EEXP"); //Console.WriteLn("recVUMI_EEXP");
FLDL2E(); FLDL2E();

174
pcsx2/x86/sVU_zerorec.cpp
View File

@ -531,14 +531,14 @@ u32 s_TotalVUCycles; // total cycles since start of program execution
u32 SuperVUGetVIAddr(int reg, int read) u32 SuperVUGetVIAddr(int reg, int read)
{ {
assert(s_pCurInst != NULL); pxAssert(s_pCurInst != NULL);
switch (reg) switch (reg)
{ {
case REG_STATUS_FLAG: case REG_STATUS_FLAG:
{ {
u32 addr = (read == 2) ? s_PrevStatusWrite : (read ? s_StatusRead : s_pCurInst->pStatusWrite); u32 addr = (read == 2) ? s_PrevStatusWrite : (read ? s_StatusRead : s_pCurInst->pStatusWrite);
assert(!read || addr != 0); pxAssert(!read || addr != 0);
return addr; return addr;
} }
case REG_MAC_FLAG: case REG_MAC_FLAG:
@ -549,7 +549,7 @@ u32 SuperVUGetVIAddr(int reg, int read)
case REG_CLIP_FLAG: case REG_CLIP_FLAG:
{ {
u32 addr = (read == 2) ? s_PrevClipWrite : (read ? s_ClipRead : s_pCurInst->pClipWrite); u32 addr = (read == 2) ? s_PrevClipWrite : (read ? s_ClipRead : s_pCurInst->pClipWrite);
assert(!read || addr != 0); pxAssert(!read || addr != 0);
return addr; return addr;
} }
case REG_Q: case REG_Q:
@ -607,7 +607,7 @@ void SuperVUDumpBlock(list<VuBaseBlock*>& blocks, int vuindex)
i = (*itblock)->startpc; i = (*itblock)->startpc;
while (itinst != (*itblock)->insts.end()) while (itinst != (*itblock)->insts.end())
{ {
assert(i <= (*itblock)->endpc); pxAssert(i <= (*itblock)->endpc);
if (itinst->type & INST_DUMMY) if (itinst->type & INST_DUMMY)
{ {
if (itinst->nParentPc >= 0 && !(itinst->type&INST_DUMMY_)) if (itinst->nParentPc >= 0 && !(itinst->type&INST_DUMMY_))
@ -723,9 +723,9 @@ void SuperVUDumpBlock(list<VuBaseBlock*>& blocks, int vuindex)
// Private methods // Private methods
void* SuperVUGetProgram(u32 startpc, int vuindex) void* SuperVUGetProgram(u32 startpc, int vuindex)
{ {
assert(startpc < s_MemSize[vuindex]); pxAssert(startpc < s_MemSize[vuindex]);
assert((startpc % 8) == 0); pxAssert((startpc % 8) == 0);
assert(recVUHeaders[vuindex] != NULL); pxAssert(recVUHeaders[vuindex] != NULL);
VuFunctionHeader** pheader = &recVUHeaders[vuindex][startpc/8]; VuFunctionHeader** pheader = &recVUHeaders[vuindex][startpc/8];
if (*pheader == NULL) if (*pheader == NULL)
@ -753,7 +753,7 @@ void* SuperVUGetProgram(u32 startpc, int vuindex)
if (*pheader == NULL) if (*pheader == NULL)
{ {
assert(s_TotalVUCycles > 0); pxAssert(s_TotalVUCycles > 0);
if (vuindex) if (vuindex)
VU1.VI[REG_TPC].UL = startpc; VU1.VI[REG_TPC].UL = startpc;
else else
@ -762,11 +762,11 @@ void* SuperVUGetProgram(u32 startpc, int vuindex)
return (void*)SuperVUEndProgram; return (void*)SuperVUEndProgram;
} }
assert((*pheader)->pprogfunc != NULL); pxAssert((*pheader)->pprogfunc != NULL);
} }
//else assert( (*pheader)->IsSame((vuindex&1) ? VU1.Micro : VU0.Micro) ); //else pxAssert( (*pheader)->IsSame((vuindex&1) ? VU1.Micro : VU0.Micro) );
assert((*pheader)->startpc == startpc); pxAssert((*pheader)->startpc == startpc);
return (*pheader)->pprogfunc; return (*pheader)->pprogfunc;
} }
@ -786,7 +786,7 @@ bool VuFunctionHeader::IsSame(void* pmem)
list<VuInstruction>::iterator VuBaseBlock::GetInstIterAtPc(int instpc) list<VuInstruction>::iterator VuBaseBlock::GetInstIterAtPc(int instpc)
{ {
assert(instpc >= 0); pxAssert(instpc >= 0);
u32 curpc = startpc; u32 curpc = startpc;
list<VuInstruction>::iterator it; list<VuInstruction>::iterator it;
@ -799,13 +799,13 @@ list<VuInstruction>::iterator VuBaseBlock::GetInstIterAtPc(int instpc)
if (it != insts.end()) return it; if (it != insts.end()) return it;
assert(0); pxAssert(0);
return insts.begin(); return insts.begin();
} }
void VuBaseBlock::GetInstsAtPc(int instpc, list<VuInstruction*>& listinsts) void VuBaseBlock::GetInstsAtPc(int instpc, list<VuInstruction*>& listinsts)
{ {
assert(instpc >= 0); pxAssert(instpc >= 0);
listinsts.clear(); listinsts.clear();
@ -835,13 +835,13 @@ void VuBaseBlock::GetInstsAtPc(int instpc, list<VuInstruction*>& listinsts)
} }
} }
assert(listinsts.size() > 0); pxAssert(listinsts.size() > 0);
} }
static VuFunctionHeader* SuperVURecompileProgram(u32 startpc, int vuindex) static VuFunctionHeader* SuperVURecompileProgram(u32 startpc, int vuindex)
{ {
assert(vuindex < 2); pxAssert(vuindex < 2);
assert(s_recVUPtr != NULL); pxAssert(s_recVUPtr != NULL);
//Console.WriteLn("svu%c rec: %x", '0'+vuindex, startpc); //Console.WriteLn("svu%c rec: %x", '0'+vuindex, startpc);
// if recPtr reached the mem limit reset whole mem // if recPtr reached the mem limit reset whole mem
@ -889,7 +889,7 @@ static VuFunctionHeader* SuperVURecompileProgram(u32 startpc, int vuindex)
//(*itblock)->type &= ~(BLOCKTYPE_IGNORE|BLOCKTYPE_ANALYZED); //(*itblock)->type &= ~(BLOCKTYPE_IGNORE|BLOCKTYPE_ANALYZED);
} }
assert(s_listBlocks.front()->startpc == startpc); pxAssert(s_listBlocks.front()->startpc == startpc);
s_listBlocks.front()->type |= BLOCKTYPE_FUNCTION; s_listBlocks.front()->type |= BLOCKTYPE_FUNCTION;
for(itblock = s_listBlocks.begin(); itblock != s_listBlocks.end(); itblock++) for(itblock = s_listBlocks.begin(); itblock != s_listBlocks.end(); itblock++)
@ -941,7 +941,7 @@ static VuFunctionHeader* SuperVURecompileProgram(u32 startpc, int vuindex)
} }
s_listBlocks.clear(); s_listBlocks.clear();
assert(s_recVUPtr < s_recVUMem + VU_EXESIZE); pxAssert(s_recVUPtr < s_recVUMem + VU_EXESIZE);
return s_pFnHeader; return s_pFnHeader;
} }
@ -1062,8 +1062,8 @@ static VuBaseBlock* SuperVUBuildBlocks(VuBaseBlock* parent, u32 startpc, const V
} }
// have to divide the blocks, pnewblock is first block // have to divide the blocks, pnewblock is first block
assert(startpc > pblock->startpc); pxAssert(startpc > pblock->startpc);
assert(startpc < pblock->endpc); pxAssert(startpc < pblock->endpc);
u32 dummyinst = (startpc - pblock->startpc) >> 3; u32 dummyinst = (startpc - pblock->startpc) >> 3;
@ -1253,7 +1253,7 @@ static VuBaseBlock* SuperVUBuildBlocks(VuBaseBlock* parent, u32 startpc, const V
{ {
pbh->pblock = pblock; pbh->pblock = pblock;
} }
else assert(prevbranch || pbh->pblock == NULL); else pxAssert(prevbranch || pbh->pblock == NULL);
pblock->insts.push_back(VuInstruction()); pblock->insts.push_back(VuInstruction());
@ -1387,7 +1387,7 @@ static VuBaseBlock* SuperVUBuildBlocks(VuBaseBlock* parent, u32 startpc, const V
if ((s_vu == 1 && i >= 0x799) || (s_vu == 0 && i >= 0x201)) if ((s_vu == 1 && i >= 0x799) || (s_vu == 0 && i >= 0x201))
{ {
Console.Error("VuRec base block doesn't terminate!"); Console.Error("VuRec base block doesn't terminate!");
assert(0); pxAssert(0);
break; break;
} }
@ -1502,7 +1502,7 @@ static VuBaseBlock* SuperVUBuildBlocks(VuBaseBlock* parent, u32 startpc, const V
// update pblock since could have changed // update pblock since could have changed
pblock = recVUBlocks[s_vu][lastpc/8-2].pblock; pblock = recVUBlocks[s_vu][lastpc/8-2].pblock;
assert(pblock != NULL); pxAssert(pblock != NULL);
pblock->blocks.push_back(pjumpblock); pblock->blocks.push_back(pjumpblock);
firstbranch = 0xff; //Non-Conditional Jump firstbranch = 0xff; //Non-Conditional Jump
@ -1514,7 +1514,7 @@ static VuBaseBlock* SuperVUBuildBlocks(VuBaseBlock* parent, u32 startpc, const V
// update pblock since could have changed // update pblock since could have changed
pblock = recVUBlocks[s_vu][lastpc/8-2].pblock; pblock = recVUBlocks[s_vu][lastpc/8-2].pblock;
assert(pblock != NULL); pxAssert(pblock != NULL);
pblock->blocks.push_back(pbranchblock); pblock->blocks.push_back(pbranchblock);
firstbranch = 0xff; //Non-Conditional Jump firstbranch = 0xff; //Non-Conditional Jump
@ -1526,7 +1526,7 @@ static VuBaseBlock* SuperVUBuildBlocks(VuBaseBlock* parent, u32 startpc, const V
// update pblock since could have changed // update pblock since could have changed
pblock = recVUBlocks[s_vu][lastpc/8-2].pblock; pblock = recVUBlocks[s_vu][lastpc/8-2].pblock;
assert(pblock != NULL); pxAssert(pblock != NULL);
pblock->blocks.push_back(pbranchblock); pblock->blocks.push_back(pbranchblock);
firstbranch = 0xff; //Non-Conditional Jump firstbranch = 0xff; //Non-Conditional Jump
break; break;
@ -1542,7 +1542,7 @@ static VuBaseBlock* SuperVUBuildBlocks(VuBaseBlock* parent, u32 startpc, const V
// update pblock since could have changed // update pblock since could have changed
pblock = recVUBlocks[s_vu][lastpc/8-2].pblock; pblock = recVUBlocks[s_vu][lastpc/8-2].pblock;
assert(pblock != NULL); pxAssert(pblock != NULL);
pblock->blocks.push_back(pbranchblock); pblock->blocks.push_back(pbranchblock);
// if has a second branch that is B or BAL, skip this // if has a second branch that is B or BAL, skip this
@ -1558,7 +1558,7 @@ static VuBaseBlock* SuperVUBuildBlocks(VuBaseBlock* parent, u32 startpc, const V
break; break;
} }
default: default:
assert(pblock->blocks.size() == 1); pxAssert(pblock->blocks.size() == 1);
break; break;
} }
@ -1584,13 +1584,13 @@ static VuBaseBlock* SuperVUBuildBlocks(VuBaseBlock* parent, u32 startpc, const V
{ {
case 0x24: // jr case 0x24: // jr
Console.Error("svurec bad jr jump!"); Console.Error("svurec bad jr jump!");
assert(0); pxAssert(0);
break; break;
case 0x25: // jalr case 0x25: // jalr
{ {
Console.Error("svurec bad jalr jump!"); Console.Error("svurec bad jalr jump!");
assert(0); pxAssert(0);
break; break;
} }
case 0x20: // B case 0x20: // B
@ -1648,7 +1648,7 @@ static void SuperVUInitLiveness(VuBaseBlock* pblock)
{ {
list<VuInstruction>::iterator itinst, itnext; list<VuInstruction>::iterator itinst, itnext;
assert(pblock->insts.size() > 0); pxAssert(pblock->insts.size() > 0);
for (itinst = pblock->insts.begin(); itinst != pblock->insts.end(); ++itinst) for (itinst = pblock->insts.begin(); itinst != pblock->insts.end(); ++itinst)
{ {
@ -1903,7 +1903,7 @@ static void SuperVUEliminateDeadCode()
// can be nonzero when a writeback belong to a different block and one branch uses // can be nonzero when a writeback belong to a different block and one branch uses
// it and this one doesn't // it and this one doesn't
#ifndef SUPERVU_WRITEBACKS #ifndef SUPERVU_WRITEBACKS
assert(!(parent->regs[0].VIwrite & (1 << REG_MAC_FLAG)) && !(parent->regs[1].VIwrite & (1 << REG_MAC_FLAG))); pxAssert(!(parent->regs[0].VIwrite & (1 << REG_MAC_FLAG)) && !(parent->regs[1].VIwrite & (1 << REG_MAC_FLAG)));
#endif #endif
// if VUPIPE_FMAC and destination is vf00, probably need to keep the mac flag // if VUPIPE_FMAC and destination is vf00, probably need to keep the mac flag
if (parent->regs[1].pipe == VUPIPE_FMAC && (parent->regs[1].VFwrite == 0 && !(parent->regs[1].VIwrite&(1 << REG_ACC_FLAG)))) if (parent->regs[1].pipe == VUPIPE_FMAC && (parent->regs[1].VFwrite == 0 && !(parent->regs[1].VIwrite&(1 << REG_ACC_FLAG))))
@ -1933,7 +1933,7 @@ static void SuperVUEliminateDeadCode()
// can be nonzero when a writeback belong to a different block and one branch uses // can be nonzero when a writeback belong to a different block and one branch uses
// it and this one doesn't // it and this one doesn't
#ifndef SUPERVU_WRITEBACKS #ifndef SUPERVU_WRITEBACKS
assert(!(parent->regs[0].VIwrite & (1 << REG_STATUS_FLAG)) && !(parent->regs[1].VIwrite & (1 << REG_STATUS_FLAG))); pxAssert(!(parent->regs[0].VIwrite & (1 << REG_STATUS_FLAG)) && !(parent->regs[1].VIwrite & (1 << REG_STATUS_FLAG)));
#endif #endif
if (parent->regs[1].pipe == VUPIPE_FMAC && (parent->regs[1].VFwrite == 0 && !(parent->regs[1].VIwrite&(1 << REG_ACC_FLAG)))) if (parent->regs[1].pipe == VUPIPE_FMAC && (parent->regs[1].VFwrite == 0 && !(parent->regs[1].VIwrite&(1 << REG_ACC_FLAG))))
{ {
@ -2005,7 +2005,7 @@ static void SuperVUEliminateDeadCode()
{ {
//parent->info.macflag = 0; //parent->info.macflag = 0;
#ifndef SUPERVU_WRITEBACKS #ifndef SUPERVU_WRITEBACKS
assert(!(parent->regs[0].VIwrite & (1 << REG_MAC_FLAG)) && !(parent->regs[1].VIwrite & (1 << REG_MAC_FLAG))); pxAssert(!(parent->regs[0].VIwrite & (1 << REG_MAC_FLAG)) && !(parent->regs[1].VIwrite & (1 << REG_MAC_FLAG)));
#endif #endif
removetype |= INST_MAC_WRITE; removetype |= INST_MAC_WRITE;
} }
@ -2023,7 +2023,7 @@ static void SuperVUEliminateDeadCode()
{ {
//parent->info.statusflag = 0; //parent->info.statusflag = 0;
#ifndef SUPERVU_WRITEBACKS #ifndef SUPERVU_WRITEBACKS
assert(!(parent->regs[0].VIwrite & (1 << REG_STATUS_FLAG)) && !(parent->regs[1].VIwrite & (1 << REG_STATUS_FLAG))); pxAssert(!(parent->regs[0].VIwrite & (1 << REG_STATUS_FLAG)) && !(parent->regs[1].VIwrite & (1 << REG_STATUS_FLAG)));
#endif #endif
removetype |= INST_STATUS_WRITE; removetype |= INST_STATUS_WRITE;
} }
@ -2123,7 +2123,7 @@ void VuBaseBlock::AssignVFRegs()
} }
else else
{ {
assert(xmmregs[j].type == XMMTYPE_ACC); pxAssert(xmmregs[j].type == XMMTYPE_ACC);
int count = 0; int count = 0;
itinst2 = itinst; itinst2 = itinst;
@ -2132,7 +2132,7 @@ void VuBaseBlock::AssignVFRegs()
while (itinst2 != insts.end()) while (itinst2 != insts.end())
{ {
assert(!((itinst2->regs[0].VIread | itinst2->regs[0].VIwrite) & (1 << REG_ACC_FLAG))); pxAssert(!((itinst2->regs[0].VIread | itinst2->regs[0].VIwrite) & (1 << REG_ACC_FLAG)));
if ((itinst2->regs[1].VIread | itinst2->regs[1].VIwrite) & (1 << REG_ACC_FLAG)) if ((itinst2->regs[1].VIread | itinst2->regs[1].VIwrite) & (1 << REG_ACC_FLAG))
break; break;
@ -2172,7 +2172,7 @@ void VuBaseBlock::AssignVFRegs()
if (regs->VFwrite) if (regs->VFwrite)
{ {
assert(!(regs->VIwrite&(1 << REG_ACC_FLAG))); pxAssert(!(regs->VIwrite&(1 << REG_ACC_FLAG)));
if (regs->VFwxyzw == 0xf) if (regs->VFwxyzw == 0xf)
{ {
@ -2211,7 +2211,7 @@ void VuBaseBlock::AssignVFRegs()
(itnext == insts.end() || ((regs->VIread&(1 << REG_ACC_FLAG)) && (!(itnext->usedvars[0]&(1 << REG_ACC_FLAG)) || !(itnext->livevars[0]&(1 << REG_ACC_FLAG)))))) (itnext == insts.end() || ((regs->VIread&(1 << REG_ACC_FLAG)) && (!(itnext->usedvars[0]&(1 << REG_ACC_FLAG)) || !(itnext->livevars[0]&(1 << REG_ACC_FLAG))))))
{ {
assert(reusereg == 0); pxAssert(reusereg == 0);
if (itnext == insts.end() || (itnext->livevars[0]&(1 << REG_ACC_FLAG))) _freeXMMreg(itinst->vfacc[i]); if (itnext == insts.end() || (itnext->livevars[0]&(1 << REG_ACC_FLAG))) _freeXMMreg(itinst->vfacc[i]);
xmmregs[itinst->vfacc[i]].inuse = 1; xmmregs[itinst->vfacc[i]].inuse = 1;
xmmregs[itinst->vfacc[i]].reg = reg; xmmregs[itinst->vfacc[i]].reg = reg;
@ -2300,7 +2300,7 @@ void VuBaseBlock::AssignVFRegs()
} }
} }
assert(x86Ptr == oldX86); pxAssert(x86Ptr == oldX86);
u32 analyzechildren = !(type & BLOCKTYPE_ANALYZED); u32 analyzechildren = !(type & BLOCKTYPE_ANALYZED);
type |= BLOCKTYPE_ANALYZED; type |= BLOCKTYPE_ANALYZED;
@ -2345,14 +2345,14 @@ void VuBaseBlock::AssignVIRegs(int parent)
return; return;
// child // child
assert(allocX86Regs == -1); pxAssert(allocX86Regs == -1);
allocX86Regs = s_vecRegArray.size(); allocX86Regs = s_vecRegArray.size();
s_vecRegArray.resize(allocX86Regs + iREGCNT_GPR); s_vecRegArray.resize(allocX86Regs + iREGCNT_GPR);
_x86regs* pregs = &s_vecRegArray[allocX86Regs]; _x86regs* pregs = &s_vecRegArray[allocX86Regs];
memset(pregs, 0, sizeof(_x86regs)*iREGCNT_GPR); memset(pregs, 0, sizeof(_x86regs)*iREGCNT_GPR);
assert(parents.size() > 0); pxAssert(parents.size() > 0);
list<VuBaseBlock*>::iterator itparent; list<VuBaseBlock*>::iterator itparent;
u32 usedvars = insts.front().usedvars[0]; u32 usedvars = insts.front().usedvars[0];
@ -2473,13 +2473,13 @@ static void SuperVUAssignRegs()
for(itblock2 = s_markov.children.begin(); itblock2 != s_markov.children.end(); itblock2++) for(itblock2 = s_markov.children.begin(); itblock2 != s_markov.children.end(); itblock2++)
{ {
assert((*itblock2)->allocX86Regs >= 0); pxAssert((*itblock2)->allocX86Regs >= 0);
_x86regs* pregs = &s_vecRegArray[(*itblock2)->allocX86Regs]; _x86regs* pregs = &s_vecRegArray[(*itblock2)->allocX86Regs];
for (int i = 0; i < iREGCNT_GPR; ++i) for (int i = 0; i < iREGCNT_GPR; ++i)
{ {
if (pregs[i].inuse && pregs[i].reg < 16) if (pregs[i].inuse && pregs[i].reg < 16)
{ {
//assert( pregs[i].reg < 16); //pxAssert( pregs[i].reg < 16);
usedregs[pregs[i].reg]++; usedregs[pregs[i].reg]++;
} }
} }
@ -2504,13 +2504,13 @@ static void SuperVUAssignRegs()
for(itblock2 = s_markov.children.begin(); itblock2 != s_markov.children.end(); itblock2++) for(itblock2 = s_markov.children.begin(); itblock2 != s_markov.children.end(); itblock2++)
{ {
assert((*itblock2)->nStartx86 == -1); pxAssert((*itblock2)->nStartx86 == -1);
(*itblock2)->nStartx86 = regid; (*itblock2)->nStartx86 = regid;
} }
for(itblock2 = s_markov.parents.begin(); itblock2 != s_markov.parents.end(); itblock2++) for(itblock2 = s_markov.parents.begin(); itblock2 != s_markov.parents.end(); itblock2++)
{ {
assert((*itblock2)->nEndx86 == -1); pxAssert((*itblock2)->nEndx86 == -1);
(*itblock2)->nEndx86 = regid; (*itblock2)->nEndx86 = regid;
} }
} }
@ -2562,7 +2562,7 @@ void SuperVUCleanupProgram(u32 startpc, int vuindex)
if ((int)s_writeQ > 0) VU->VI[REG_Q] = VU->q; if ((int)s_writeQ > 0) VU->VI[REG_Q] = VU->q;
if ((int)s_writeP > 0) if ((int)s_writeP > 0)
{ {
assert(VU == &VU1); pxAssert(VU == &VU1);
VU1.VI[REG_P] = VU1.p; // only VU1 VU1.VI[REG_P] = VU1.p; // only VU1
} }
@ -2691,7 +2691,7 @@ void SuperVUFlush(int p, int wait)
// executed only once per program // executed only once per program
static u32* SuperVUStaticAlloc(u32 size) static u32* SuperVUStaticAlloc(u32 size)
{ {
assert(recVUStackPtr + size <= recVUStack + SUPERVU_STACKSIZE); pxAssert(recVUStackPtr + size <= recVUStack + SUPERVU_STACKSIZE);
// always zero // always zero
if (size == 4) *(u32*)recVUStackPtr = 0; if (size == 4) *(u32*)recVUStackPtr = 0;
else memset(recVUStackPtr, 0, size); else memset(recVUStackPtr, 0, size);
@ -2718,7 +2718,7 @@ static void SuperVURecompile()
// make sure everything compiled // make sure everything compiled
for(itblock = s_listBlocks.begin(); itblock != s_listBlocks.end(); itblock++) for(itblock = s_listBlocks.begin(); itblock != s_listBlocks.end(); itblock++)
{ {
assert(((*itblock)->type & BLOCKTYPE_ANALYZED) && (*itblock)->pcode != NULL); pxAssert(((*itblock)->type & BLOCKTYPE_ANALYZED) && (*itblock)->pcode != NULL);
} }
// link all blocks // link all blocks
@ -2726,7 +2726,7 @@ static void SuperVURecompile()
{ {
VuBaseBlock::LISTBLOCKS::iterator itchild; VuBaseBlock::LISTBLOCKS::iterator itchild;
assert((*itblock)->blocks.size() <= ArraySize((*itblock)->pChildJumps)); pxAssert((*itblock)->blocks.size() <= ArraySize((*itblock)->pChildJumps));
int i = 0; int i = 0;
for(itchild = (*itblock)->blocks.begin(); itchild != (*itblock)->blocks.end(); itchild++) for(itchild = (*itblock)->blocks.begin(); itchild != (*itblock)->blocks.end(); itchild++)
@ -2741,7 +2741,7 @@ static void SuperVURecompile()
if (pchild->type & BLOCKTYPE_HASEOP) if (pchild->type & BLOCKTYPE_HASEOP)
{ {
assert(pchild->blocks.size() == 0); pxAssert(pchild->blocks.size() == 0);
AND32ItoM((uptr)&VU0.VI[ REG_VPU_STAT ].UL, s_vu ? ~0x100 : ~0x001); // E flag AND32ItoM((uptr)&VU0.VI[ REG_VPU_STAT ].UL, s_vu ? ~0x100 : ~0x001); // E flag
AND32ItoM((uptr)&VU->vifRegs->stat, ~VIF1_STAT_VEW); AND32ItoM((uptr)&VU->vifRegs->stat, ~VIF1_STAT_VEW);
@ -2752,7 +2752,7 @@ static void SuperVURecompile()
// only other case is when there are two branches // only other case is when there are two branches
else else
{ {
assert((*itblock)->insts.back().regs[0].pipe == VUPIPE_BRANCH); pxAssert((*itblock)->insts.back().regs[0].pipe == VUPIPE_BRANCH);
} }
continue; continue;
@ -2761,7 +2761,7 @@ static void SuperVURecompile()
if ((u32)(uptr)(*itblock)->pChildJumps[i] & 0x80000000) if ((u32)(uptr)(*itblock)->pChildJumps[i] & 0x80000000)
{ {
// relative // relative
assert((uptr)(*itblock)->pChildJumps[i] <= 0xffffffff); pxAssert((uptr)(*itblock)->pChildJumps[i] <= 0xffffffff);
(*itblock)->pChildJumps[i] = (u32*)((uptr)(*itblock)->pChildJumps[i] & 0x7fffffff); (*itblock)->pChildJumps[i] = (u32*)((uptr)(*itblock)->pChildJumps[i] & 0x7fffffff);
*(*itblock)->pChildJumps[i] = (uptr)(*itchild)->pcode - ((uptr)(*itblock)->pChildJumps[i] + 4); *(*itblock)->pChildJumps[i] = (uptr)(*itchild)->pcode - ((uptr)(*itblock)->pChildJumps[i] + 4);
} }
@ -2955,7 +2955,7 @@ void VuBaseBlock::Recompile()
if (s_ScheduleXGKICK && s_XGKICKReg > 0) if (s_ScheduleXGKICK && s_XGKICKReg > 0)
{ {
assert(x86regs[s_XGKICKReg].inuse); pxAssert(x86regs[s_XGKICKReg].inuse);
x86regs[s_XGKICKReg].needed = 1; x86regs[s_XGKICKReg].needed = 1;
} }
itinst->Recompile(itinst, vuxyz); itinst->Recompile(itinst, vuxyz);
@ -2968,8 +2968,8 @@ void VuBaseBlock::Recompile()
} }
} }
} }
assert(pc == endpc); pxAssert(pc == endpc);
assert(s_ScheduleXGKICK == 0); pxAssert(s_ScheduleXGKICK == 0);
// flush flags // flush flags
if (s_PrevClipWrite != (uptr)&VU->VI[REG_CLIP_FLAG]) if (s_PrevClipWrite != (uptr)&VU->VI[REG_CLIP_FLAG])
@ -3058,7 +3058,7 @@ void VuBaseBlock::Recompile()
{ {
if (!x86regs[s_JumpX86].inuse) if (!x86regs[s_JumpX86].inuse)
{ {
assert(x86regs[s_JumpX86].type == X86TYPE_VUJUMP); pxAssert(x86regs[s_JumpX86].type == X86TYPE_VUJUMP);
s_JumpX86 = 0xffffffff; // notify to jump from g_recWriteback s_JumpX86 = 0xffffffff; // notify to jump from g_recWriteback
} }
} }
@ -3172,7 +3172,7 @@ void VuBaseBlock::Recompile()
default: default:
DevCon.Error("Bad branch %x\n", branch); DevCon.Error("Bad branch %x\n", branch);
assert(0); pxAssert(0);
break; break;
} }
} }
@ -3208,7 +3208,7 @@ int VuInstruction::SetCachedRegs(int upper, u32 vuxyz)
} }
if (vfwrite[upper] >= 0) if (vfwrite[upper] >= 0)
{ {
assert(regs[upper].VFwrite > 0); pxAssert(regs[upper].VFwrite > 0);
SuperVUFreeXMMreg(vfwrite[upper], XMMTYPE_VFREG, regs[upper].VFwrite); SuperVUFreeXMMreg(vfwrite[upper], XMMTYPE_VFREG, regs[upper].VFwrite);
_allocVFtoXMMreg(VU, vfwrite[upper], regs[upper].VFwrite, _allocVFtoXMMreg(VU, vfwrite[upper], regs[upper].VFwrite,
MODE_WRITE | (regs[upper].VFwxyzw != 0xf ? MODE_READ : 0) | GET_VUXYZMODE(regs[upper].VFwrite)); MODE_WRITE | (regs[upper].VFwxyzw != 0xf ? MODE_READ : 0) | GET_VUXYZMODE(regs[upper].VFwrite));
@ -3231,7 +3231,7 @@ int VuInstruction::SetCachedRegs(int upper, u32 vuxyz)
} }
else else
{ {
assert(regs[upper].VFwrite == _Fd_); pxAssert(regs[upper].VFwrite == _Fd_);
info |= PROCESS_EE_SET_D(vfwrite[upper]); info |= PROCESS_EE_SET_D(vfwrite[upper]);
} }
} }
@ -3252,7 +3252,7 @@ int VuInstruction::SetCachedRegs(int upper, u32 vuxyz)
if (upper && (regs[upper].VIwrite & (1 << REG_CLIP_FLAG))) if (upper && (regs[upper].VIwrite & (1 << REG_CLIP_FLAG)))
{ {
// CLIP inst, need two extra temp registers, put it EEREC_D and EEREC_ACC // CLIP inst, need two extra temp registers, put it EEREC_D and EEREC_ACC
assert(vfwrite[upper] == -1); pxAssert(vfwrite[upper] == -1);
SuperVUFreeXMMreg((vffree[upper] >> 8)&0xf, XMMTYPE_TEMP, 0); SuperVUFreeXMMreg((vffree[upper] >> 8)&0xf, XMMTYPE_TEMP, 0);
_allocTempXMMreg(XMMT_FPS, (vffree[upper] >> 8)&0xf); _allocTempXMMreg(XMMT_FPS, (vffree[upper] >> 8)&0xf);
info |= PROCESS_EE_SET_D((vffree[upper] >> 8) & 0xf); info |= PROCESS_EE_SET_D((vffree[upper] >> 8) & 0xf);
@ -3290,7 +3290,7 @@ void VuInstruction::Recompile(list<VuInstruction>::iterator& itinst, u32 vuxyz)
u8* pjmp; u8* pjmp;
int vfregstore = 0; int vfregstore = 0;
assert(s_pCurInst == this); pxAssert(s_pCurInst == this);
s_WriteToReadQ = 0; s_WriteToReadQ = 0;
ptr = (u32*) & VU->Micro[ pc ]; ptr = (u32*) & VU->Micro[ pc ];
@ -3338,7 +3338,7 @@ void VuInstruction::Recompile(list<VuInstruction>::iterator& itinst, u32 vuxyz)
} }
} }
assert(pparentinst != NULL); pxAssert(pparentinst != NULL);
} }
#endif #endif
@ -3540,9 +3540,9 @@ void VuInstruction::Recompile(list<VuInstruction>::iterator& itinst, u32 vuxyz)
MOV32ItoM(pparentinst->pMACWrite, 0); MOV32ItoM(pparentinst->pMACWrite, 0);
} }
assert(s_ClipRead != 0); pxAssert(s_ClipRead != 0);
assert(s_MACRead != 0); pxAssert(s_MACRead != 0);
assert(s_StatusRead != 0); pxAssert(s_StatusRead != 0);
return; return;
} }
@ -3552,7 +3552,7 @@ void VuInstruction::Recompile(list<VuInstruction>::iterator& itinst, u32 vuxyz)
if( IsDebugBuild ) if( IsDebugBuild )
MOV32ItoR(EAX, pc); MOV32ItoR(EAX, pc);
assert(!(type & (INST_CLIP_WRITE | INST_STATUS_WRITE | INST_MAC_WRITE))); pxAssert(!(type & (INST_CLIP_WRITE | INST_STATUS_WRITE | INST_MAC_WRITE)));
pc += 8; pc += 8;
list<VuInstruction>::const_iterator itinst2; list<VuInstruction>::const_iterator itinst2;
@ -3574,8 +3574,8 @@ void VuInstruction::Recompile(list<VuInstruction>::iterator& itinst, u32 vuxyz)
} }
else else
{ {
assert(s_StatusRead == (uptr)&VU->VI[REG_STATUS_FLAG]); pxAssert(s_StatusRead == (uptr)&VU->VI[REG_STATUS_FLAG]);
assert(s_MACRead == (uptr)&VU->VI[REG_MAC_FLAG]); pxAssert(s_MACRead == (uptr)&VU->VI[REG_MAC_FLAG]);
pMACWrite = s_MACRead; pMACWrite = s_MACRead;
pStatusWrite = s_StatusRead; pStatusWrite = s_StatusRead;
} }
@ -3637,7 +3637,7 @@ void VuInstruction::Recompile(list<VuInstruction>::iterator& itinst, u32 vuxyz)
if (ptr[1] & 0x80000000) // I flag if (ptr[1] & 0x80000000) // I flag
{ {
assert(!(regs[0].VIwrite & ((1 << REG_Q) | (1 << REG_P)))); pxAssert(!(regs[0].VIwrite & ((1 << REG_Q) | (1 << REG_P))));
VU->code = ptr[1]; VU->code = ptr[1];
s_vuInfo = SetCachedRegs(1, vuxyz); s_vuInfo = SetCachedRegs(1, vuxyz);
@ -3720,7 +3720,7 @@ void VuInstruction::Recompile(list<VuInstruction>::iterator& itinst, u32 vuxyz)
// write new Q // write new Q
if (cacheq) if (cacheq)
{ {
assert(s_pCurInst->pqcycles > 1); pxAssert(s_pCurInst->pqcycles > 1);
ADD32ItoR(x86temp, s_pCurInst->info.cycle + s_pCurInst->pqcycles); ADD32ItoR(x86temp, s_pCurInst->info.cycle + s_pCurInst->pqcycles);
MOV32RtoM((uptr)&s_writeQ, x86temp); MOV32RtoM((uptr)&s_writeQ, x86temp);
s_needFlush |= 1; s_needFlush |= 1;
@ -3767,7 +3767,7 @@ void VuInstruction::Recompile(list<VuInstruction>::iterator& itinst, u32 vuxyz)
} }
// write new P // write new P
assert(s_pCurInst->pqcycles > 1); pxAssert(s_pCurInst->pqcycles > 1);
ADD32ItoR(x86temp, s_pCurInst->info.cycle + s_pCurInst->pqcycles); ADD32ItoR(x86temp, s_pCurInst->info.cycle + s_pCurInst->pqcycles);
MOV32RtoM((uptr)&s_writeP, x86temp); MOV32RtoM((uptr)&s_writeP, x86temp);
s_needFlush |= 2; s_needFlush |= 2;
@ -3798,7 +3798,7 @@ void VuInstruction::Recompile(list<VuInstruction>::iterator& itinst, u32 vuxyz)
if (vfwrite[1] >= 0) if (vfwrite[1] >= 0)
{ {
assert(regs[1].VFwrite > 0); pxAssert(regs[1].VFwrite > 0);
if (vfwrite[0] == vfwrite[1]) if (vfwrite[0] == vfwrite[1])
{ {
@ -3807,8 +3807,8 @@ void VuInstruction::Recompile(list<VuInstruction>::iterator& itinst, u32 vuxyz)
if (vfread0[0] == vfwrite[1] || vfread1[0] == vfwrite[1]) if (vfread0[0] == vfwrite[1] || vfread1[0] == vfwrite[1])
{ {
assert(regs[0].VFread0 == regs[1].VFwrite || regs[0].VFread1 == regs[1].VFwrite); pxAssert(regs[0].VFread0 == regs[1].VFwrite || regs[0].VFread1 == regs[1].VFwrite);
assert(vfflush[0] >= 0); pxAssert(vfflush[0] >= 0);
if (modewrite) if (modewrite)
{ {
SSE_MOVAPS_XMM_to_M128((uptr)&VU->VF[regs[1].VFwrite], (x86SSERegType)vfwrite[1]); SSE_MOVAPS_XMM_to_M128((uptr)&VU->VF[regs[1].VFwrite], (x86SSERegType)vfwrite[1]);
@ -3827,7 +3827,7 @@ void VuInstruction::Recompile(list<VuInstruction>::iterator& itinst, u32 vuxyz)
// necessary because status can be set by both upper and lower // necessary because status can be set by both upper and lower
if (regs[1].VIwrite & (1 << REG_STATUS_FLAG)) if (regs[1].VIwrite & (1 << REG_STATUS_FLAG))
{ {
assert(pStatusWrite != 0); pxAssert(pStatusWrite != 0);
s_PrevStatusWrite = pStatusWrite; s_PrevStatusWrite = pStatusWrite;
} }
@ -3839,7 +3839,7 @@ void VuInstruction::Recompile(list<VuInstruction>::iterator& itinst, u32 vuxyz)
// load // load
SSE_MOVAPS_M128_to_XMM(vfflush[0], (uptr)&VU->VF[regs[1].VFwrite]); SSE_MOVAPS_M128_to_XMM(vfflush[0], (uptr)&VU->VF[regs[1].VFwrite]);
assert(xmmregs[vfwrite[1]].mode & MODE_WRITE); pxAssert(xmmregs[vfwrite[1]].mode & MODE_WRITE);
// replace with vfflush // replace with vfflush
if (_Fs_ == regs[1].VFwrite) if (_Fs_ == regs[1].VFwrite)
@ -3866,7 +3866,7 @@ void VuInstruction::Recompile(list<VuInstruction>::iterator& itinst, u32 vuxyz)
#ifdef SUPERVU_VIBRANCHDELAY #ifdef SUPERVU_VIBRANCHDELAY
if (type & INST_CACHE_VI) if (type & INST_CACHE_VI)
{ {
assert(vicached >= 0); pxAssert(vicached >= 0);
int cachedreg = _allocX86reg(-1, X86TYPE_VI | (s_vu ? X86TYPE_VU1 : 0), vicached, MODE_READ); int cachedreg = _allocX86reg(-1, X86TYPE_VI | (s_vu ? X86TYPE_VU1 : 0), vicached, MODE_READ);
MOV32RtoM((uptr)&s_VIBranchDelay, cachedreg); MOV32RtoM((uptr)&s_VIBranchDelay, cachedreg);
} }
@ -3879,7 +3879,7 @@ void VuInstruction::Recompile(list<VuInstruction>::iterator& itinst, u32 vuxyz)
// if( itinst2->regs[0].pipe == VUPIPE_BRANCH && (itinst->regs[0].VIwrite&itinst2->regs[0].VIread) ) { // if( itinst2->regs[0].pipe == VUPIPE_BRANCH && (itinst->regs[0].VIwrite&itinst2->regs[0].VIread) ) {
// //
// CALLFunc((u32)branchfn); // CALLFunc((u32)branchfn);
// assert( itinst->regs[0].VIwrite & 0xffff ); // pxAssert( itinst->regs[0].VIwrite & 0xffff );
// Console.WriteLn("vi write before branch"); // Console.WriteLn("vi write before branch");
// for(s_CacheVIReg = 0; s_CacheVIReg < 16; ++s_CacheVIReg) { // for(s_CacheVIReg = 0; s_CacheVIReg < 16; ++s_CacheVIReg) {
// if( itinst->regs[0].VIwrite & (1<<s_CacheVIReg) ) // if( itinst->regs[0].VIwrite & (1<<s_CacheVIReg) )
@ -3892,11 +3892,11 @@ void VuInstruction::Recompile(list<VuInstruction>::iterator& itinst, u32 vuxyz)
// } // }
// } // }
// else if( pc == s_pCurBlock->endpc-8 && s_CacheVIReg >= 0 ) { // else if( pc == s_pCurBlock->endpc-8 && s_CacheVIReg >= 0 ) {
// assert( s_CacheVIX86 > 0 && x86regs[s_CacheVIX86].inuse && x86regs[s_CacheVIX86].reg == s_CacheVIReg && x86regs[s_CacheVIX86].type == X86TYPE_VITEMP ); // pxAssert( s_CacheVIX86 > 0 && x86regs[s_CacheVIX86].inuse && x86regs[s_CacheVIX86].reg == s_CacheVIReg && x86regs[s_CacheVIX86].type == X86TYPE_VITEMP );
// //
// oldreg = _allocX86reg(-1, X86TYPE_VI|(s_vu?X86TYPE_VU1:0), s_CacheVIReg, MODE_READ); // oldreg = _allocX86reg(-1, X86TYPE_VI|(s_vu?X86TYPE_VU1:0), s_CacheVIReg, MODE_READ);
// x86regs[s_CacheVIX86].needed = 1; // x86regs[s_CacheVIX86].needed = 1;
// assert( x86regs[oldreg].mode & MODE_WRITE ); // pxAssert( x86regs[oldreg].mode & MODE_WRITE );
// //
// x86regs[s_CacheVIX86].type = X86TYPE_VI|(s_vu?X86TYPE_VU1:0); // x86regs[s_CacheVIX86].type = X86TYPE_VI|(s_vu?X86TYPE_VU1:0);
// x86regs[oldreg].type = X86TYPE_VITEMP; // x86regs[oldreg].type = X86TYPE_VITEMP;
@ -3917,19 +3917,19 @@ void VuInstruction::Recompile(list<VuInstruction>::iterator& itinst, u32 vuxyz)
// clip is always written so ok // clip is always written so ok
if ((regs[0].VIwrite | regs[1].VIwrite) & (1 << REG_CLIP_FLAG)) if ((regs[0].VIwrite | regs[1].VIwrite) & (1 << REG_CLIP_FLAG))
{ {
assert(pClipWrite != 0); pxAssert(pClipWrite != 0);
s_PrevClipWrite = pClipWrite; s_PrevClipWrite = pClipWrite;
} }
if ((regs[0].VIwrite | regs[1].VIwrite) & (1 << REG_STATUS_FLAG)) if ((regs[0].VIwrite | regs[1].VIwrite) & (1 << REG_STATUS_FLAG))
{ {
assert(pStatusWrite != 0); pxAssert(pStatusWrite != 0);
s_PrevStatusWrite = pStatusWrite; s_PrevStatusWrite = pStatusWrite;
} }
if ((regs[0].VIwrite | regs[1].VIwrite) & (1 << REG_MAC_FLAG)) if ((regs[0].VIwrite | regs[1].VIwrite) & (1 << REG_MAC_FLAG))
{ {
assert(pMACWrite != 0); pxAssert(pMACWrite != 0);
s_PrevMACWrite = pMACWrite; s_PrevMACWrite = pMACWrite;
} }
} }
@ -3945,7 +3945,7 @@ void recVUMI_BranchHandle()
if (s_pCurInst->type & INST_BRANCH_DELAY) if (s_pCurInst->type & INST_BRANCH_DELAY)
{ {
assert((branch&0x17) != 0x10 && (branch&0x17) != 4); // no jump handlig for now pxAssert((branch&0x17) != 0x10 && (branch&0x17) != 4); // no jump handlig for now
if ((branch & 0x7) == 3) if ((branch & 0x7) == 3)
{ {
@ -3955,7 +3955,7 @@ void recVUMI_BranchHandle()
else if (branch & 1) curjump = 2; else if (branch & 1) curjump = 2;
} }
assert(s_JumpX86 > 0); pxAssert(s_JumpX86 > 0);
if ((s_pCurBlock->type & BLOCKTYPE_HASEOP) || s_vu == 0 || SUPERVU_CHECKCONDITION) if ((s_pCurBlock->type & BLOCKTYPE_HASEOP) || s_vu == 0 || SUPERVU_CHECKCONDITION)
MOV32ItoM(SuperVUGetVIAddr(REG_TPC, 0), bpc); MOV32ItoM(SuperVUGetVIAddr(REG_TPC, 0), bpc);
@ -4325,7 +4325,7 @@ void recVUMI_JALR(VURegs* vuu, s32 info)
void recVUMI_XGKICK_(VURegs *VU) void recVUMI_XGKICK_(VURegs *VU)
{ {
assert(s_XGKICKReg > 0 && x86regs[s_XGKICKReg].inuse && x86regs[s_XGKICKReg].type == X86TYPE_VITEMP); pxAssert(s_XGKICKReg > 0 && x86regs[s_XGKICKReg].inuse && x86regs[s_XGKICKReg].type == X86TYPE_VITEMP);
x86regs[s_XGKICKReg].inuse = 0; // so free doesn't flush x86regs[s_XGKICKReg].inuse = 0; // so free doesn't flush
_freeX86regs(); _freeX86regs();