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Some work on Vif & Hw. 

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@979 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
arcum42 2009-04-15 04:41:42 +00:00
parent fa1a79b368
commit a661c80a4a
8 changed files with 352 additions and 331 deletions
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30
pcsx2/Gif.cpp
View File

@ -55,8 +55,8 @@ __forceinline void gsInterrupt() {
//Console::WriteLn("Eh? why are you still interrupting! chcr %x, qwc %x, done = %x", params gif->chcr, gif->qwc, done);
return;
}
if(gif->qwc > 0 || gspath3done == 0) {
if( !(psHu32(DMAC_CTRL) & 0x1) ) {
if (gif->qwc > 0 || gspath3done == 0) {
if (!(psHu32(DMAC_CTRL) & 0x1)) {
Console::Notice("gs dma masked, re-scheduling...");
// re-raise the int shortly in the future
CPU_INT( 2, 64 );
@ -71,7 +71,7 @@ __forceinline void gsInterrupt() {
/*if (!(vif1Regs->mskpath3 && (vif1ch->chcr & 0x100)) || (psHu32(GIF_MODE) & 0x1))
CPU_INT( 2, 64 );*/
#endif
if(gspath3done == 0) return;
if (gspath3done == 0) return;
}
gspath3done = 0;
@ -223,7 +223,7 @@ void GIFdma()
ptag = (u32*)dmaGetAddr(gif->tadr); //Set memory pointer to TADR
if (ptag == NULL) { //Is ptag empty?
psHu32(DMAC_STAT)|= 1<<15; //If yes, set BEIS (BUSERR) in DMAC_STAT register
psHu32(DMAC_STAT) |= DMAC_STAT_BEIS; //If yes, set BEIS (BUSERR) in DMAC_STAT register
return;
}
gscycles += 2;
@ -276,7 +276,7 @@ void GIFdma()
while ((gspath3done == 0) && (gif->qwc == 0)) { //Loop if the transfers aren't intermittent
ptag = (u32*)dmaGetAddr(gif->tadr); //Set memory pointer to TADR
if (ptag == NULL) { //Is ptag empty?
psHu32(DMAC_STAT)|= 1<<15; //If yes, set BEIS (BUSERR) in DMAC_STAT register
psHu32(DMAC_STAT)|= DMAC_STAT_BEIS; //If yes, set BEIS (BUSERR) in DMAC_STAT register
return;
}
gscycles+=2; // Add 1 cycles from the QW read for the tag
@ -294,7 +294,7 @@ void GIFdma()
if ((psHu32(DMAC_CTRL) & 0xC0) == 0x80) { // STD == GIF
// there are still bugs, need to also check if gif->madr +16*qwc >= stadr, if not, stall
if(!gspath3done && gif->madr + (gif->qwc * 16) > psHu32(DMAC_STADR) && id == 4) {
if(!gspath3done && ((gif->madr + (gif->qwc * 16)) > psHu32(DMAC_STADR)) && (id == 4)) {
// stalled
Console::WriteLn("GS Stall Control Source = %x, Drain = %x\n MADR = %x, STADR = %x", params (psHu32(0xe000) >> 4) & 0x3, (psHu32(0xe000) >> 6) & 0x3,gif->madr, psHu32(DMAC_STADR));
prevcycles = gscycles;
@ -307,7 +307,7 @@ void GIFdma()
}
GIFchain(); //Transfers the data set by the switch
if ((gif->chcr & 0x80) && ptag[0] >> 31) { //Check TIE bit of CHCR and IRQ bit of tag
if ((gif->chcr & 0x80) && (ptag[0] >> 31)) { //Check TIE bit of CHCR and IRQ bit of tag
GIF_LOG("dmaIrq Set");
gspath3done = 1;
}
@ -408,8 +408,8 @@ static __forceinline int mfifoGIFrbTransfer() {
gifqwc -= mfifoqwc;
gif->qwc -= mfifoqwc;
gif->madr+= mfifoqwc*16;
mfifocycles+= (mfifoqwc) * 2; /* guessing */
gif->madr += mfifoqwc*16;
mfifocycles += (mfifoqwc) * 2; /* guessing */
return 0;
}
@ -432,9 +432,9 @@ static __forceinline int mfifoGIFchain() {
if (pMem == NULL) return -1;
WRITERING_DMA(pMem, mfifoqwc);
gif->madr+= mfifoqwc*16;
gif->madr += mfifoqwc*16;
gif->qwc -= mfifoqwc;
mfifocycles+= (mfifoqwc) * 2; /* guessing */
mfifocycles += (mfifoqwc) * 2; /* guessing */
}
return 0;
@ -450,14 +450,14 @@ void mfifoGIFtransfer(int qwc) {
if(qwc > 0 ) {
gifqwc += qwc;
if(!(gif->chcr & 0x100))return;
if(gifstate == GIF_STATE_STALL) return;
if (!(gif->chcr & 0x100)) return;
if (gifstate == GIF_STATE_STALL) return;
}
SPR_LOG("mfifoGIFtransfer %x madr %x, tadr %x", gif->chcr, gif->madr, gif->tadr);
if(gif->qwc == 0){
if(gif->tadr == spr0->madr) {
if (gif->qwc == 0) {
if (gif->tadr == spr0->madr) {
//if( gifqwc > 1 ) DevCon::WriteLn("gif mfifo tadr==madr but qwc = %d", params gifqwc);
//hwDmacIrq(14);

178
pcsx2/Hw.cpp
View File

@ -148,28 +148,28 @@ int hwMFIFOWrite(u32 addr, u8 *data, u32 size) {
}
int hwDmacSrcChainWithStack(DMACh *dma, int id) {
bool hwDmacSrcChainWithStack(DMACh *dma, int id) {
u32 temp;
switch (id) {
case 0: // Refe - Transfer Packet According to ADDR field
return 1; //End Transfer
return true; //End Transfer
case 1: // CNT - Transfer QWC following the tag.
dma->madr = dma->tadr + 16; //Set MADR to QW after Tag
dma->tadr = dma->madr + (dma->qwc << 4); //Set TADR to QW following the data
return 0;
return false;
case 2: // Next - Transfer QWC following tag. TADR = ADDR
temp = dma->madr; //Temporarily Store ADDR
dma->madr = dma->tadr + 16; //Set MADR to QW following the tag
dma->tadr = temp; //Copy temporarily stored ADDR to Tag
return 0;
return false;
case 3: // Ref - Transfer QWC from ADDR field
case 4: // Refs - Transfer QWC from ADDR field (Stall Control)
dma->tadr += 16; //Set TADR to next tag
return 0;
return false;
case 5: // Call - Transfer QWC following the tag, save succeeding tag
temp = dma->madr; //Temporarily Store ADDR
@ -185,11 +185,11 @@ int hwDmacSrcChainWithStack(DMACh *dma, int id) {
dma->asr1 = dma->madr + (dma->qwc << 4); //If no store Succeeding tag in ASR1
}else {
Console::Notice("Call Stack Overflow (report if it fixes/breaks anything)");
return 1; //Return done
return true; //Return done
}
dma->tadr = temp; //Set TADR to temporarily stored ADDR
return 0;
return false;
case 6: // Ret - Transfer QWC following the tag, load next tag
dma->madr = dma->tadr + 16; //Set MADR to data following the tag
@ -209,47 +209,47 @@ int hwDmacSrcChainWithStack(DMACh *dma, int id) {
return 1; //End Transfer
}
}
return 0;
return false;
case 7: // End - Transfer QWC following the tag
dma->madr = dma->tadr + 16; //Set MADR to data following the tag
//Dont Increment tadr, breaks Soul Calibur II and III
return 1; //End Transfer
return true; //End Transfer
}
return -1;
return false;
}
int hwDmacSrcChain(DMACh *dma, int id) {
bool hwDmacSrcChain(DMACh *dma, int id) {
u32 temp;
switch (id) {
case 0: // Refe - Transfer Packet According to ADDR field
return 1; //End Transfer
return true; //End Transfer
case 1: // CNT - Transfer QWC following the tag.
dma->madr = dma->tadr + 16; //Set MADR to QW after Tag
dma->tadr = dma->madr + (dma->qwc << 4); //Set TADR to QW following the data
return 0;
return false;
case 2: // Next - Transfer QWC following tag. TADR = ADDR
temp = dma->madr; //Temporarily Store ADDR
dma->madr = dma->tadr + 16; //Set MADR to QW following the tag
dma->tadr = temp; //Copy temporarily stored ADDR to Tag
return 0;
return false;
case 3: // Ref - Transfer QWC from ADDR field
case 4: // Refs - Transfer QWC from ADDR field (Stall Control)
dma->tadr += 16; //Set TADR to next tag
return 0;
return false;
case 7: // End - Transfer QWC following the tag
dma->madr = dma->tadr + 16; //Set MADR to data following the tag
//Dont Increment tadr, breaks Soul Calibur II and III
return 1; //End Transfer
return true; //End Transfer
}
return -1;
return false;
}
// Original hwRead/Write32 functions .. left in for now, for troubleshooting purposes.
@ -301,23 +301,27 @@ mem32_t __fastcall hwRead32(u32 mem)
}
#if 0 // Counters Reference Block (original case setup)
case 0x10000000: return (u16)rcntRcount(0);
case 0x10000010: return (u16)counters[0].modeval;
case 0x10000020: return (u16)counters[0].target;
case 0x10000030: return (u16)counters[0].hold;
// 0x10000000 - 0x10000030
case RCNT0_COUNT: return (u16)rcntRcount(0);
case RCNT0_MODE: return (u16)counters[0].modeval;
case RCNT0_TARGET: return (u16)counters[0].target;
case RCNT0_HOLD: return (u16)counters[0].hold;
case 0x10000800: return (u16)rcntRcount(1);
case 0x10000810: return (u16)counters[1].modeval;
case 0x10000820: return (u16)counters[1].target;
case 0x10000830: return (u16)counters[1].hold;
// 0x10000800 - 0x10000830
case RCNT1_COUNT: return (u16)rcntRcount(1);
case RCNT1_MODE: return (u16)counters[1].modeval;
case RCNT1_TARGET: return (u16)counters[1].target;
case RCNT1_HOLD: return (u16)counters[1].hold;
case 0x10001000: return (u16)rcntRcount(2);
case 0x10001010: return (u16)counters[2].modeval;
case 0x10001020: return (u16)counters[2].target;
// 0x10001000 - 0x10001020
case RCNT2_COUNT: return (u16)rcntRcount(2);
case RCNT2_MODE: return (u16)counters[2].modeval;
case RCNT2_TARGET: return (u16)counters[2].target;
case 0x10001800: return (u16)rcntRcount(3);
case 0x10001810: return (u16)counters[3].modeval;
case 0x10001820: return (u16)counters[3].target;
// 0x10001800 - 0x10001820
case RCNT3_COUNT: return (u16)rcntRcount(3);
case RCNT3_MODE: return (u16)counters[3].modeval;
case RCNT3_TARGET: return (u16)counters[3].target;
#endif
break;
@ -386,7 +390,7 @@ mem32_t __fastcall hwRead32(u32 mem)
{
const char* regName = "Unknown";
switch( mem )
switch (mem)
{
case D2_CHCR: regName = "DMA2_CHCR"; break;
case D2_MADR: regName = "DMA2_MADR"; break;
@ -426,8 +430,8 @@ mem32_t __fastcall hwRead32(u32 mem)
__forceinline void __fastcall hwWrite32(u32 mem, u32 value)
{
if ((mem>=0x10002000) && (mem<0x10003000)) { //IPU regs
// Would ((mem >= IPU_CMD) && (mem <= IPU_TOP)) be better? -arcum42
if ((mem >= IPU_CMD) && (mem < GIF_CTRL)) { //IPU regs
ipuWrite32(mem,value);
return;
}
@ -439,25 +443,25 @@ __forceinline void __fastcall hwWrite32(u32 mem, u32 value)
vif1Write32(mem, value);
return;
}
switch (mem) {
case 0x10000000: rcntWcount(0, value); break;
case 0x10000010: rcntWmode(0, value); break;
case 0x10000020: rcntWtarget(0, value); break;
case 0x10000030: rcntWhold(0, value); break;
case RCNT0_COUNT: rcntWcount(0, value); break;
case RCNT0_MODE: rcntWmode(0, value); break;
case RCNT0_TARGET: rcntWtarget(0, value); break;
case RCNT0_TARGET: rcntWhold(0, value); break;
case 0x10000800: rcntWcount(1, value); break;
case 0x10000810: rcntWmode(1, value); break;
case 0x10000820: rcntWtarget(1, value); break;
case 0x10000830: rcntWhold(1, value); break;
case RCNT1_COUNT: rcntWcount(1, value); break;
case RCNT1_MODE: rcntWmode(1, value); break;
case RCNT1_TARGET: rcntWtarget(1, value); break;
case RCNT1_HOLD: rcntWhold(1, value); break;
case 0x10001000: rcntWcount(2, value); break;
case 0x10001010: rcntWmode(2, value); break;
case 0x10001020: rcntWtarget(2, value); break;
case RCNT2_COUNT: rcntWcount(2, value); break;
case RCNT2_MODE: rcntWmode(2, value); break;
case RCNT2_TARGET: rcntWtarget(2, value); break;
case 0x10001800: rcntWcount(3, value); break;
case 0x10001810: rcntWmode(3, value); break;
case 0x10001820: rcntWtarget(3, value); break;
case RCNT3_COUNT: rcntWcount(3, value); break;
case RCNT3_MODE: rcntWmode(3, value); break;
case RCNT3_TARGET: rcntWtarget(3, value); break;
case GIF_CTRL:
//Console::WriteLn("GIF_CTRL write %x", params value);
@ -492,150 +496,150 @@ __forceinline void __fastcall hwWrite32(u32 mem, u32 value)
Console::WriteLn("Gifstat write value = %x", params value);
return;
case 0x10008000: // dma0 - vif0
case D0_CHCR: // dma0 - vif0
DMA_LOG("VIF0dma %lx", value);
DmaExec(dmaVIF0, mem, value);
break;
case 0x10009000: // dma1 - vif1 - chcr
case D1_CHCR: // dma1 - vif1 - chcr
DMA_LOG("VIF1dma CHCR %lx", value);
DmaExec(dmaVIF1, mem, value);
break;
#ifdef PCSX2_DEVBUILD
case 0x10009010: // dma1 - vif1 - madr
case D1_MADR: // dma1 - vif1 - madr
HW_LOG("VIF1dma Madr %lx", value);
psHu32(mem) = value;//dma1 madr
break;
case 0x10009020: // dma1 - vif1 - qwc
case D1_QWC: // dma1 - vif1 - qwc
HW_LOG("VIF1dma QWC %lx", value);
psHu32(mem) = value;//dma1 qwc
break;
case 0x10009030: // dma1 - vif1 - tadr
case D1_TADR: // dma1 - vif1 - tadr
HW_LOG("VIF1dma TADR %lx", value);
psHu32(mem) = value;//dma1 tadr
break;
case 0x10009040: // dma1 - vif1 - asr0
case D1_ASR0: // dma1 - vif1 - asr0
HW_LOG("VIF1dma ASR0 %lx", value);
psHu32(mem) = value;//dma1 asr0
break;
case 0x10009050: // dma1 - vif1 - asr1
case D1_ASR1: // dma1 - vif1 - asr1
HW_LOG("VIF1dma ASR1 %lx", value);
psHu32(mem) = value;//dma1 asr1
break;
case 0x10009080: // dma1 - vif1 - sadr
case D1_SADR: // dma1 - vif1 - sadr
HW_LOG("VIF1dma SADR %lx", value);
psHu32(mem) = value;//dma1 sadr
break;
#endif
case 0x1000a000: // dma2 - gif
case D2_CHCR: // dma2 - gif
DMA_LOG("0x%8.8x hwWrite32: GSdma %lx", cpuRegs.cycle, value);
DmaExec(dmaGIF, mem, value);
break;
#ifdef PCSX2_DEVBUILD
case 0x1000a010:
case D2_MADR:
psHu32(mem) = value;//dma2 madr
HW_LOG("Hardware write DMA2_MADR 32bit at %x with value %x",mem,value);
break;
case 0x1000a020:
case D2_QWC:
psHu32(mem) = value;//dma2 qwc
HW_LOG("Hardware write DMA2_QWC 32bit at %x with value %x",mem,value);
break;
case 0x1000a030:
case D2_TADR:
psHu32(mem) = value;//dma2 taddr
HW_LOG("Hardware write DMA2_TADDR 32bit at %x with value %x",mem,value);
break;
case 0x1000a040:
case D2_ASR0:
psHu32(mem) = value;//dma2 asr0
HW_LOG("Hardware write DMA2_ASR0 32bit at %x with value %x",mem,value);
break;
case 0x1000a050:
case D2_ASR1:
psHu32(mem) = value;//dma2 asr1
HW_LOG("Hardware write DMA2_ASR1 32bit at %x with value %x",mem,value);
break;
case 0x1000a080:
case D2_SADR:
psHu32(mem) = value;//dma2 saddr
HW_LOG("Hardware write DMA2_SADDR 32bit at %x with value %x",mem,value);
break;
#endif
case 0x1000b000: // dma3 - fromIPU
case D3_CHCR: // dma3 - fromIPU
DMA_LOG("IPU0dma %lx", value);
DmaExec(dmaIPU0, mem, value);
break;
#ifdef PCSX2_DEVBUILD
case 0x1000b010:
case D3_MADR:
psHu32(mem) = value;//dma2 madr
HW_LOG("Hardware write IPU0DMA_MADR 32bit at %x with value %x",mem,value);
break;
case 0x1000b020:
case D3_QWC:
psHu32(mem) = value;//dma2 madr
HW_LOG("Hardware write IPU0DMA_QWC 32bit at %x with value %x",mem,value);
break;
case 0x1000b030:
case D3_TADR:
psHu32(mem) = value;//dma2 tadr
HW_LOG("Hardware write IPU0DMA_TADR 32bit at %x with value %x",mem,value);
break;
case 0x1000b080:
case D3_SADR:
psHu32(mem) = value;//dma2 saddr
HW_LOG("Hardware write IPU0DMA_SADDR 32bit at %x with value %x",mem,value);
break;
#endif
case 0x1000b400: // dma4 - toIPU
case D4_CHCR: // dma4 - toIPU
DMA_LOG("IPU1dma %lx", value);
DmaExec(dmaIPU1, mem, value);
break;
#ifdef PCSX2_DEVBUILD
case 0x1000b410:
case D4_MADR:
psHu32(mem) = value;//dma2 madr
HW_LOG("Hardware write IPU1DMA_MADR 32bit at %x with value %x",mem,value);
break;
case 0x1000b420:
case D4_QWC:
psHu32(mem) = value;//dma2 madr
HW_LOG("Hardware write IPU1DMA_QWC 32bit at %x with value %x",mem,value);
break;
case 0x1000b430:
case D4_TADR:
psHu32(mem) = value;//dma2 tadr
HW_LOG("Hardware write IPU1DMA_TADR 32bit at %x with value %x",mem,value);
break;
case 0x1000b480:
case D4_SADR:
psHu32(mem) = value;//dma2 saddr
HW_LOG("Hardware write IPU1DMA_SADDR 32bit at %x with value %x",mem,value);
break;
#endif
case 0x1000c000: // dma5 - sif0
case D5_CHCR: // dma5 - sif0
DMA_LOG("SIF0dma %lx", value);
DmaExec(dmaSIF0, mem, value);
break;
case 0x1000c400: // dma6 - sif1
case D6_CHCR: // dma6 - sif1
DMA_LOG("SIF1dma %lx", value);
DmaExec(dmaSIF1, mem, value);
break;
#ifdef PCSX2_DEVBUILD
case 0x1000c420: // dma6 - sif1 - qwc
case D6_QWC: // dma6 - sif1 - qwc
HW_LOG("SIF1dma QWC = %lx", value);
psHu32(mem) = value;
break;
@ -645,12 +649,12 @@ __forceinline void __fastcall hwWrite32(u32 mem, u32 value)
psHu32(mem) = value;
break;
#endif
case 0x1000c800: // dma7 - sif2
case D7_CHCR: // dma7 - sif2
DMA_LOG("SIF2dma %lx", value);
DmaExec(dmaSIF2, mem, value);
break;
case 0x1000d000: // dma8 - fromSPR
case D8_CHCR: // dma8 - fromSPR
DMA_LOG("fromSPRdma %lx", value);
DmaExec(dmaSPR0, mem, value);
break;
@ -660,12 +664,12 @@ __forceinline void __fastcall hwWrite32(u32 mem, u32 value)
DmaExec(dmaSPR1, mem, value);
break;
case 0x1000e000: // DMAC_CTRL
case DMAC_CTRL: // DMAC_CTRL
HW_LOG("DMAC_CTRL Write 32bit %x", value);
psHu32(0xe000) = value;
break;
case 0x1000e010: // DMAC_STAT
case DMAC_STAT: // DMAC_STAT
HW_LOG("DMAC_STAT Write 32bit %x", value);
psHu16(0xe010)&= ~(value & 0xffff); // clear on 1
psHu16(0xe012) ^= (u16)(value >> 16);
@ -673,12 +677,12 @@ __forceinline void __fastcall hwWrite32(u32 mem, u32 value)
cpuTestDMACInts();
break;
case 0x1000f000: // INTC_STAT
case INTC_STAT: // INTC_STAT
HW_LOG("INTC_STAT Write 32bit %x", value);
psHu32(0xf000)&=~value;
break;
case 0x1000f010: // INTC_MASK
case INTC_MASK: // INTC_MASK
HW_LOG("INTC_MASK Write 32bit %x", value);
psHu32(0xf010) ^= (u16)value;
cpuTestINTCInts();
@ -694,7 +698,7 @@ __forceinline void __fastcall hwWrite32(u32 mem, u32 value)
psHu32(mem) = value;
break;
case 0x1000f590: // DMAC_ENABLEW
case DMAC_ENABLEW: // DMAC_ENABLEW
HW_LOG("DMAC_ENABLEW Write 32bit %lx", value);
psHu32(0xf590) = value;
psHu32(0xf520) = value;
@ -704,15 +708,15 @@ __forceinline void __fastcall hwWrite32(u32 mem, u32 value)
psHu32(mem) = value;
break;
case 0x1000f220:
case SBUS_F220:
psHu32(mem) |= value;
break;
case 0x1000f230:
case SBUS_SMFLG:
psHu32(mem) &= ~value;
break;
case 0x1000f240:
case SBUS_F240:
if(!(value & 0x100))
psHu32(mem) &= ~0x100;
else

327
pcsx2/Hw.h
View File

@ -64,177 +64,183 @@ struct DMACh {
};
// HW defines
enum HWaddress
{
RCNT0_COUNT = 0x10000000,
RCNT0_MODE = 0x10000010,
RCNT0_TARGET = 0x10000020,
RCNT0_HOLD = 0x10000030,
#define RCNT0_COUNT 0x10000000
#define RCNT0_MODE 0x10000010
#define RCNT0_TARGET 0x10000020
#define RCNT0_HOLD 0x10000030
RCNT1_COUNT = 0x10000800,
RCNT1_MODE = 0x10000810,
RCNT1_TARGET = 0x10000820,
RCNT1_HOLD = 0x10000830,
#define RCNT1_COUNT 0x10000800
#define RCNT1_MODE 0x10000810
#define RCNT1_TARGET 0x10000820
#define RCNT1_HOLD 0x10000830
RCNT2_COUNT = 0x10001000,
RCNT2_MODE = 0x10001010,
RCNT2_TARGET = 0x10001020,
#define RCNT2_COUNT 0x10001000
#define RCNT2_MODE 0x10001010
#define RCNT2_TARGET 0x10001020
RCNT3_COUNT = 0x10001800,
RCNT3_MODE = 0x10001810,
RCNT3_TARGET = 0x10001820,
#define RCNT3_COUNT 0x10001800
#define RCNT3_MODE 0x10001810
#define RCNT3_TARGET 0x10001820
IPU_CMD = 0x10002000,
IPU_CTRL = 0x10002010,
IPU_BP = 0x10002020,
IPU_TOP = 0x10002030,
#define IPU_CMD 0x10002000
#define IPU_CTRL 0x10002010
#define IPU_BP 0x10002020
#define IPU_TOP 0x10002030
GIF_CTRL = 0x10003000,
GIF_MODE = 0x10003010,
GIF_STAT = 0x10003020,
GIF_TAG0 = 0x10003040,
GIF_TAG1 = 0x10003050,
GIF_TAG2 = 0x10003060,
GIF_TAG3 = 0x10003070,
GIF_CNT = 0x10003080,
GIF_P3CNT = 0x10003090,
GIF_P3TAG = 0x100030A0,
GIF_FIFO = 0x10006000,
#define GIF_CTRL 0x10003000
#define GIF_MODE 0x10003010
#define GIF_STAT 0x10003020
#define GIF_TAG0 0x10003040
#define GIF_TAG1 0x10003050
#define GIF_TAG2 0x10003060
#define GIF_TAG3 0x10003070
#define GIF_CNT 0x10003080
#define GIF_P3CNT 0x10003090
#define GIF_P3TAG 0x100030A0
#define GIF_FIFO 0x10006000
#define IPUout_FIFO 0x10007000
#define IPUin_FIFO 0x10007010
IPUout_FIFO = 0x10007000,
IPUin_FIFO = 0x10007010,
//VIF0
#define D0_CHCR 0x10008000
#define D0_MADR 0x10008010
#define D0_QWC 0x10008020
D0_CHCR = 0x10008000,
D0_MADR = 0x10008010,
D0_QWC = 0x10008020,
//VIF1
#define D1_CHCR 0x10009000
#define D1_MADR 0x10009010
#define D1_QWC 0x10009020
#define D1_TADR 0x10009030
#define D1_ASR0 0x10009040
#define D1_ASR1 0x10009050
#define D1_SADR 0x10009080
D1_CHCR = 0x10009000,
D1_MADR = 0x10009010,
D1_QWC = 0x10009020,
D1_TADR = 0x10009030,
D1_ASR0 = 0x10009040,
D1_ASR1 = 0x10009050,
D1_SADR = 0x10009080,
//GS
#define D2_CHCR 0x1000A000
#define D2_MADR 0x1000A010
#define D2_QWC 0x1000A020
#define D2_TADR 0x1000A030
#define D2_ASR0 0x1000A040
#define D2_ASR1 0x1000A050
#define D2_SADR 0x1000A080
D2_CHCR = 0x1000A000,
D2_MADR = 0x1000A010,
D2_QWC = 0x1000A020,
D2_TADR = 0x1000A030,
D2_ASR0 = 0x1000A040,
D2_ASR1 = 0x1000A050,
D2_SADR = 0x1000A080,
//fromIPU
#define D3_CHCR 0x1000B000
#define D3_MADR 0x1000B010
#define D3_QWC 0x1000B020
#define D3_TADR 0x1000B030
#define D3_SADR 0x1000B080
D3_CHCR = 0x1000B000,
D3_MADR = 0x1000B010,
D3_QWC = 0x1000B020,
D3_TADR = 0x1000B030,
D3_SADR = 0x1000B080,
//toIPU
#define D4_CHCR 0x1000B400
#define D4_MADR 0x1000B410
#define D4_QWC 0x1000B420
#define D4_TADR 0x1000B430
#define D4_SADR 0x1000B480
D4_CHCR = 0x1000B400,
D4_MADR = 0x1000B410,
D4_QWC = 0x1000B420,
D4_TADR = 0x1000B430,
D4_SADR = 0x1000B480,
//SIF0
#define D5_CHCR 0x1000C000
#define D5_MADR 0x1000C010
#define D5_QWC 0x1000C020
D5_CHCR = 0x1000C000,
D5_MADR = 0x1000C010,
D5_QWC = 0x1000C020,
//SIF1
#define D6_CHCR 0x1000C400
#define D6_MADR 0x1000C410
#define D6_QWC 0x1000C420
D6_CHCR = 0x1000C400,
D6_MADR = 0x1000C410,
D6_QWC = 0x1000C420,
//SIF2
#define D7_CHCR 0x1000C800
#define D7_MADR 0x1000C810
#define D7_QWC 0x1000C820
D7_CHCR = 0x1000C800,
D7_MADR = 0x1000C810,
D7_QWC = 0x1000C820,
//fromSPR
#define D8_CHCR 0x1000D000
#define D8_MADR 0x1000D010
#define D8_QWC 0x1000D020
#define D8_SADR 0x1000D080
D8_CHCR = 0x1000D000,
D8_MADR = 0x1000D010,
D8_QWC = 0x1000D020,
D8_SADR = 0x1000D080,
DMAC_CTRL = 0x1000E000,
DMAC_STAT = 0x1000E010,
DMAC_PCR = 0x1000E020,
DMAC_SQWC = 0x1000E030,
DMAC_RBSR = 0x1000E040,
DMAC_RBOR = 0x1000E050,
DMAC_STADR = 0x1000E060,
#define DMAC_CTRL 0x1000E000
#define DMAC_STAT 0x1000E010
#define DMAC_PCR 0x1000E020
#define DMAC_SQWC 0x1000E030
#define DMAC_RBSR 0x1000E040
#define DMAC_RBOR 0x1000E050
#define DMAC_STADR 0x1000E060
INTC_STAT = 0x1000F000,
INTC_MASK = 0x1000F010,
#define INTC_STAT 0x1000F000
#define INTC_MASK 0x1000F010
SBUS_F220 = 0x1000F220,
SBUS_SMFLG = 0x1000F230,
SBUS_F240 = 0x1000F240,
#define SBUS_F220 0x1000F220
#define SBUS_SMFLG 0x1000F230
#define SBUS_F240 0x1000F240
DMAC_ENABLER = 0x1000F520,
DMAC_ENABLEW = 0x1000F590,
#define DMAC_ENABLER 0x1000F520
#define DMAC_ENABLEW 0x1000F590
GS_PMODE = 0x12000000,
GS_SMODE1 = 0x12000010,
GS_SMODE2 = 0x12000020,
GS_SRFSH = 0x12000030,
GS_SYNCH1 = 0x12000040,
GS_SYNCH2 = 0x12000050,
GS_SYNCV = 0x12000060,
GS_DISPFB1 = 0x12000070,
GS_DISPLAY1 = 0x12000080,
GS_DISPFB2 = 0x12000090,
GS_DISPLAY2 = 0x120000A0,
GS_EXTBUF = 0x120000B0,
GS_EXTDATA = 0x120000C0,
GS_EXTWRITE = 0x120000D0,
GS_BGCOLOR = 0x120000E0,
GS_CSR = 0x12001000,
GS_IMR = 0x12001010,
GS_BUSDIR = 0x12001040,
GS_SIGLBLID = 0x12001080
};
#define SBFLG_IOPALIVE 0x10000
#define SBFLG_IOPSYNC 0x40000
#define GS_PMODE 0x12000000
#define GS_SMODE1 0x12000010
#define GS_SMODE2 0x12000020
#define GS_SRFSH 0x12000030
#define GS_SYNCH1 0x12000040
#define GS_SYNCH2 0x12000050
#define GS_SYNCV 0x12000060
#define GS_DISPFB1 0x12000070
#define GS_DISPLAY1 0x12000080
#define GS_DISPFB2 0x12000090
#define GS_DISPLAY2 0x120000A0
#define GS_EXTBUF 0x120000B0
#define GS_EXTDATA 0x120000C0
#define GS_EXTWRITE 0x120000D0
#define GS_BGCOLOR 0x120000E0
#define GS_CSR 0x12001000
#define GS_IMR 0x12001010
#define GS_BUSDIR 0x12001040
#define GS_SIGLBLID 0x12001080
#define INTC_GS 0
#define INTC_SBUS 1
#define INTC_VBLANK_S 2
#define INTC_VBLANK_E 3
#define INTC_VIF0 4
#define INTC_VIF1 5
#define INTC_VU0 6
#define INTC_VU1 7
#define INTC_IPU 8
#define INTC_TIM0 9
#define INTC_TIM1 10
#define INTC_TIM2 11
#define INTC_TIM3 12
#define SBFLG_IOPALIVE 0x10000
#define SBFLG_IOPSYNC 0x40000
enum INTCIrqs
{
INTC_GS = 0,
INTC_SBUS,
INTC_VBLANK_S,
INTC_VBLANK_E,
INTC_VIF0,
INTC_VIF1,
INTC_VU0,
INTC_VU1,
INTC_IPU,
INTC_TIM0,
INTC_TIM1,
INTC_TIM2,
INTC_TIM3,
};
#define DMAC_STAT_SIS (1<<13) // stall condition
#define DMAC_STAT_MEIS (1<<14) // mfifo empty
#define DMAC_STAT_BEIS (1<<15) // bus error
#define DMAC_STAT_SIM (1<<29) // stall mask
#define DMAC_STAT_MEIM (1<<30) // mfifo mask
#define DMAC_VIF0 0
#define DMAC_VIF1 1
#define DMAC_GIF 2
#define DMAC_FROM_IPU 3
#define DMAC_TO_IPU 4
#define DMAC_SIF0 5
#define DMAC_SIF1 6
#define DMAC_SIF2 7
#define DMAC_FROM_SPR 8
#define DMAC_TO_SPR 9
#define DMAC_ERROR 15
enum DMACIrqs
{
DMAC_VIF0 = 0,
DMAC_VIF1,
DMAC_GIF,
DMAC_FROM_IPU,
DMAC_TO_IPU,
DMAC_SIF0,
DMAC_SIF1,
DMAC_SIF2,
DMAC_FROM_SPR,
DMAC_TO_SPR,
DMAC_ERROR = 15,
};
#define VIF0_STAT_VPS_W (1)
#define VIF0_STAT_VPS_D (2)
@ -266,20 +272,39 @@ struct DMACh {
#define VIF1_STAT_ER1 (1<<13)
#define VIF1_STAT_FDR (1<<23)
#define VIF_STAT_VPS_W (1)
#define VIF_STAT_VPS_D (2)
#define VIF_STAT_VPS_T (3)
#define VIF_STAT_VPS (3)
#define VIF_STAT_VEW (1<<2)
#define VIF_STAT_VGW (1<<3)
#define VIF_STAT_MRK (1<<6)
#define VIF_STAT_DBF (1<<7)
#define VIF_STAT_VSS (1<<8)
#define VIF_STAT_VFS (1<<9)
#define VIF_STAT_VIS (1<<10)
#define VIF_STAT_INT (1<<11)
#define VIF_STAT_ER0 (1<<12)
#define VIF_STAT_ER1 (1<<13)
#define VIF_STAT_FDR (1<<23)
//DMA interrupts & masks
#define BEISintr (0x8000)
#define VIF0intr (0x10001)
#define VIF1intr (0x20002)
#define GIFintr (0x40004)
#define IPU0intr (0x80008)
#define IPU1intr (0x100010)
#define SIF0intr (0x200020)
#define SIF1intr (0x400040)
#define SIF2intr (0x800080)
#define SPR0intr (0x1000100)
#define SPR1intr (0x2000200)
#define SISintr (0x20002000)
#define MEISintr (0x40004000)
enum DMAInter
{
BEISintr = 0x8000,
VIF0intr = 0x10001,
VIF1intr = 0x20002,
GIFintr = 0x40004,
IPU0intr = 0x80008,
IPU1intr = 0x100010,
SIF0intr = 0x200020,
SIF1intr =0x400040,
SIF2intr = 0x800080,
SPR0intr = 0x1000100,
SPR1intr = 0x2000200,
SISintr = 0x20002000,
MEISintr = 0x40004000
};
#ifdef PCSX2_VIRTUAL_MEM
@ -344,10 +369,10 @@ static __forceinline u32 *_dmaGetAddr(DMACh *dma, u32 addr, u32 num)
if (ptr == NULL)
{
// DMA Error
psHu32(DMAC_STAT)|= 1<<15; /* BUS error */
psHu32(DMAC_STAT) |= DMAC_STAT_BEIS; /* BUS error */
// DMA End
psHu32(DMAC_STAT)|= 1<<num;
psHu32(DMAC_STAT) |= 1<<num;
dma->chcr &= ~0x100;
}
@ -413,8 +438,8 @@ void hwDmacIrq(int n);
int hwMFIFORead(u32 addr, u8 *data, u32 size);
int hwMFIFOWrite(u32 addr, u8 *data, u32 size);
int hwDmacSrcChainWithStack(DMACh *dma, int id);
int hwDmacSrcChain(DMACh *dma, int id);
bool hwDmacSrcChainWithStack(DMACh *dma, int id);
bool hwDmacSrcChain(DMACh *dma, int id);
int hwConstRead8 (u32 x86reg, u32 mem, u32 sign);
int hwConstRead16(u32 x86reg, u32 mem, u32 sign);

6
pcsx2/HwWrite.cpp
View File

@ -199,7 +199,7 @@ void hwWrite8(u32 mem, u8 value) {
DevCon::Notice("8 bit VIF1 DMA Start while DMAC Disabled\n");
QueuedDMA |= 0x2;
}
if(value & 0x1) vif1.done = 0; //This must be done here! some games (ala Crash of the Titans) pause the dma to start MFIFO
if(value & 0x1) vif1.done = false; //This must be done here! some games (ala Crash of the Titans) pause the dma to start MFIFO
DmaExec8(dmaVIF1, mem, value);
break;
@ -356,7 +356,7 @@ __forceinline void hwWrite16(u32 mem, u16 value)
DevCon::Notice("16 bit VIF1 DMA Start while DMAC Disabled\n");
QueuedDMA |= 0x2;
}
if(value & 0x100) vif1.done = 0; //This must be done here! some games (ala Crash of the Titans) pause the dma to start MFIFO
if(value & 0x100) vif1.done = false; //This must be done here! some games (ala Crash of the Titans) pause the dma to start MFIFO
DmaExec16(dmaVIF1, mem, value);
break;
@ -859,7 +859,7 @@ void __fastcall hwWrite32_generic( u32 mem, u32 value )
}
if(value & 0x100)
{
vif1.done = 0; //This must be done here! some games (ala Crash of the Titans) pause the dma to start MFIFO
vif1.done = false; //This must be done here! some games (ala Crash of the Titans) pause the dma to start MFIFO
}
DmaExec(dmaVIF1, mem, value);
return;

9
pcsx2/Memory.h
View File

@ -146,15 +146,6 @@ extern u8 g_RealGSMem[Ps2MemSize::GSregs];
#define psSu32(mem) (*(u32*)&PS2MEM_SCRATCH[(mem) & 0x3fff])
#define psSu64(mem) (*(u64*)&PS2MEM_SCRATCH[(mem) & 0x3fff])
//#define PSMs8(mem) (*(s8 *)PSM(mem))
//#define PSMs16(mem) (*(s16*)PSM(mem))
//#define PSMs32(mem) (*(s32*)PSM(mem))
//#define PSMs64(mem) (*(s64*)PSM(mem))
//#define PSMu8(mem) (*(u8 *)PSM(mem))
//#define PSMu16(mem) (*(u16*)PSM(mem))
//#define PSMu32(mem) (*(u32*)PSM(mem))
//#define PSMu64(mem) (*(u64*)PSM(mem))
extern void memAlloc();
extern void memReset(); // clears PS2 ram and loads the bios. Throws Exception::FileNotFound on error.
extern void memShutdown();

32
pcsx2/Vif.cpp
View File

@ -37,7 +37,7 @@ PCSX2_ALIGNED16(u32 g_vifCol1[4]);
extern int g_vifCycles;
u16 vifqwc = 0;
bool mfifodmairq = FALSE;
bool mfifodmairq = false;
enum UnpackOffset
{
@ -357,7 +357,7 @@ static __forceinline int mfifoVIF1rbTransfer()
src = (u32*)PSM(vif1ch->madr);
if (src == NULL) return -1;
if (vif1.vifstalled == 1)
if (vif1.vifstalled)
ret = VIF1transfer(src + vif1.irqoffset, s1 - vif1.irqoffset, 0);
else
ret = VIF1transfer(src, s1, 0);
@ -379,7 +379,7 @@ static __forceinline int mfifoVIF1rbTransfer()
src = (u32*)PSM(vif1ch->madr);
if (src == NULL) return -1;
if (vif1.vifstalled == 1)
if (vif1.vifstalled)
ret = VIF1transfer(src + vif1.irqoffset, mfifoqwc * 4 - vif1.irqoffset, 0);
else
ret = VIF1transfer(src, mfifoqwc << 2, 0);
@ -395,7 +395,7 @@ static __forceinline int mfifo_VIF1chain()
int ret;
/* Is QWC = 0? if so there is nothing to transfer */
if (vif1ch->qwc == 0 && vif1.vifstalled == 0)
if ((vif1ch->qwc == 0) && (!vif1.vifstalled))
{
vif1.inprogress = 0;
return 0;
@ -414,7 +414,7 @@ static __forceinline int mfifo_VIF1chain()
SPR_LOG("Non-MFIFO Location");
if (pMem == NULL) return -1;
if (vif1.vifstalled == 1)
if (vif1.vifstalled)
ret = VIF1transfer(pMem + vif1.irqoffset, vif1ch->qwc * 4 - vif1.irqoffset, 0);
else
ret = VIF1transfer(pMem, vif1ch->qwc << 2, 0);
@ -448,7 +448,7 @@ void mfifoVIF1transfer(int qwc)
return;
}
mfifodmairq = FALSE; //Clear any previous TIE interrupt
mfifodmairq = false; //Clear any previous TIE interrupt
if (vif1ch->qwc == 0)
{
@ -456,7 +456,7 @@ void mfifoVIF1transfer(int qwc)
if (vif1ch->chcr & 0x40)
{
if (vif1.stallontag == 1)
if (vif1.stallontag)
ret = VIF1transfer(ptag + (2 + vif1.irqoffset), 2 - vif1.irqoffset, 1); //Transfer Tag on Stall
else
ret = VIF1transfer(ptag + 2, 2, 1); //Transfer Tag
@ -464,7 +464,7 @@ void mfifoVIF1transfer(int qwc)
if (ret == -2)
{
VIF_LOG("MFIFO Stallon tag");
vif1.stallontag = 1;
vif1.stallontag = true;
return; //IRQ set by VIFTransfer
}
}
@ -483,13 +483,13 @@ void mfifoVIF1transfer(int qwc)
{
case 0: // Refe - Transfer Packet According to ADDR field
vif1ch->tadr = psHu32(DMAC_RBOR) + ((vif1ch->tadr + 16) & psHu32(DMAC_RBSR));
vif1.done = 1; //End Transfer
vif1.done = true; //End Transfer
break;
case 1: // CNT - Transfer QWC following the tag.
vif1ch->madr = psHu32(DMAC_RBOR) + ((vif1ch->tadr + 16) & psHu32(DMAC_RBSR)); //Set MADR to QW after Tag
vif1ch->tadr = psHu32(DMAC_RBOR) + ((vif1ch->madr + (vif1ch->qwc << 4)) & psHu32(DMAC_RBSR)); //Set TADR to QW following the data
vif1.done = 0;
vif1.done = false;
break;
case 2: // Next - Transfer QWC following tag. TADR = ADDR
@ -498,28 +498,28 @@ void mfifoVIF1transfer(int qwc)
vif1ch->madr = psHu32(DMAC_RBOR) + ((vif1ch->tadr + 16) & psHu32(DMAC_RBSR)); //Set MADR to QW following the tag
vif1ch->tadr = temp; //Copy temporarily stored ADDR to Tag
if ((temp & psHu32(DMAC_RBSR)) != psHu32(DMAC_RBOR)) Console::WriteLn("Next tag = %x outside ring %x size %x", params temp, psHu32(DMAC_RBOR), psHu32(DMAC_RBSR));
vif1.done = 0;
vif1.done = false;
break;
}
case 3: // Ref - Transfer QWC from ADDR field
case 4: // Refs - Transfer QWC from ADDR field (Stall Control)
vif1ch->tadr = psHu32(DMAC_RBOR) + ((vif1ch->tadr + 16) & psHu32(DMAC_RBSR)); //Set TADR to next tag
vif1.done = 0;
vif1.done = false;
break;
case 7: // End - Transfer QWC following the tag
vif1ch->madr = psHu32(DMAC_RBOR) + ((vif1ch->tadr + 16) & psHu32(DMAC_RBSR)); //Set MADR to data following the tag
vif1ch->tadr = psHu32(DMAC_RBOR) + ((vif1ch->madr + (vif1ch->qwc << 4)) & psHu32(DMAC_RBSR)); //Set TADR to QW following the data
vif1.done = 1; //End Transfer
vif1.done = true; //End Transfer
break;
}
if ((vif1ch->chcr & 0x80) && (ptag[0] >> 31))
{
VIF_LOG("dmaIrq Set");
vif1.done = 1;
mfifodmairq = TRUE; //Let the handler know we have prematurely ended MFIFO
vif1.done = true;
mfifodmairq = true; //Let the handler know we have prematurely ended MFIFO
}
}
@ -547,7 +547,7 @@ void vifMFIFOInterrupt()
}
}
if (vif1.done != 1 || vif1.inprogress & 1)
if (!vif1.done || vif1.inprogress & 1)
{
if (vifqwc <= 0)
{

92
pcsx2/VifDma.cpp
View File

@ -59,8 +59,8 @@ static const unsigned int VIF0dmanum = 0;
static const unsigned int VIF1dmanum = 1;
int g_vifCycles = 0;
bool path3hack = FALSE;
bool Path3transfer = FALSE;
bool path3hack = false;
bool Path3transfer = false;
u32 splittransfer[4];
u32 splitptr = 0;
@ -1081,8 +1081,8 @@ int VIF0transfer(u32 *data, int size, int istag)
int transferred = vif0.vifstalled ? vif0.irqoffset : 0; // irqoffset necessary to add up the right qws, or else will spin (spiderman)
VIF_LOG("VIF0transfer: size %x (vif0.cmd %x)", size, vif0.cmd);
vif0.stallontag = 0;
vif0.vifstalled = 0;
vif0.stallontag = false;
vif0.vifstalled = false;
vif0.vifpacketsize = size;
while (vif0.vifpacketsize > 0)
@ -1144,7 +1144,7 @@ int VIF0transfer(u32 *data, int size, int istag)
++vif0.irq;
if (istag && vif0.tag.size <= vif0.vifpacketsize) vif0.stallontag = 1;
if (istag && vif0.tag.size <= vif0.vifpacketsize) vif0.stallontag = true;
if (vif0.tag.size == 0) break;
}
@ -1158,7 +1158,7 @@ int VIF0transfer(u32 *data, int size, int istag)
if (vif0.irq && (vif0.tag.size == 0))
{
vif0.vifstalled = 1;
vif0.vifstalled = true;
if (((vif0Regs->code >> 24) & 0x7f) != 0x7)vif0Regs->stat |= VIF0_STAT_VIS;
//else Console::WriteLn("VIF0 IRQ on MARK");
@ -1194,7 +1194,7 @@ int _VIF0chain()
u32 *pMem;
u32 ret;
if (vif0ch->qwc == 0 && vif0.vifstalled == 0) return 0;
if ((vif0ch->qwc == 0) && !vif0.vifstalled) return 0;
pMem = (u32*)dmaGetAddr(vif0ch->madr);
if (pMem == NULL) return -1;
@ -1207,7 +1207,7 @@ int _VIF0chain()
return ret;
}
int _chainVIF0()
bool _chainVIF0()
{
int id, ret;
@ -1232,8 +1232,10 @@ int _chainVIF0()
if (vif0ch->chcr & 0x40)
{
if (vif0.vifstalled == 1) ret = VIF0transfer(vif0ptag + (2 + vif0.irqoffset), 2 - vif0.irqoffset, 1); //Transfer Tag on stall
else ret = VIF0transfer(vif0ptag + 2, 2, 1); //Transfer Tag
if (vif0.vifstalled)
ret = VIF0transfer(vif0ptag + (2 + vif0.irqoffset), 2 - vif0.irqoffset, 1); //Transfer Tag on stall
else
ret = VIF0transfer(vif0ptag + 2, 2, 1); //Transfer Tag
if (ret == -1) return -1; //There has been an error
if (ret == -2) return -2; //IRQ set by VIFTransfer
}
@ -1249,7 +1251,7 @@ int _chainVIF0()
{
VIF_LOG("dmaIrq Set\n");
vif0.done = 1;
vif0.done = true;
return vif0.done; //End Transfer
}
return vif0.done; //Return Done
@ -1274,7 +1276,7 @@ void vif0Interrupt()
}
if (vif0ch->qwc > 0 || vif0.irqoffset > 0)
{
if (vif0.stallontag == 1)
if (vif0.stallontag)
_chainVIF0();
else
_VIF0chain();
@ -1286,7 +1288,7 @@ void vif0Interrupt()
if ((vif0ch->chcr & 0x100) == 0) Console::WriteLn("Vif0 running when CHCR = %x", params vif0ch->chcr);
if ((vif0ch->chcr & 0x4) && (vif0.done == 0) && (vif0.vifstalled == 0))
if ((vif0ch->chcr & 0x4) && (!vif0.done) && (!vif0.vifstalled))
{
if (!(psHu32(DMAC_CTRL) & 0x1))
@ -1363,16 +1365,16 @@ void dmaVIF0()
if (_VIF0chain() == -2)
{
Console::WriteLn("Stall on normal %x", params vif0Regs->stat);
vif0.vifstalled = 1;
vif0.vifstalled = true;
return;
}
vif0.done = 1;
vif0.done = true;
CPU_INT(0, g_vifCycles);
return;
}
// Chain Mode
vif0.done = 0;
vif0.done = false;
CPU_INT(0, 0);
}
@ -1400,7 +1402,7 @@ void vif0Write32(u32 mem, u32 value)
cpuRegs.interrupt &= ~1; //Stop all vif0 DMA's
psHu64(0x10004000) = 0;
psHu64(0x10004008) = 0;
vif0.done = 1;
vif0.done = true;
vif0Regs->err = 0;
vif0Regs->stat &= ~(0xF000000 | VIF0_STAT_INT | VIF0_STAT_VSS | VIF0_STAT_VIS | VIF0_STAT_VFS | VIF0_STAT_VPS); // FQC=0
}
@ -1411,7 +1413,7 @@ void vif0Write32(u32 mem, u32 value)
cpuRegs.interrupt &= ~1; //Stop all vif0 DMA's
vif0Regs->stat |= VIF0_STAT_VFS;
vif0Regs->stat &= ~VIF0_STAT_VPS;
vif0.vifstalled = 1;
vif0.vifstalled = true;
Console::WriteLn("vif0 force break");
}
if (value & 0x4)
@ -1421,15 +1423,15 @@ void vif0Write32(u32 mem, u32 value)
// just stoppin the VIF (linuz).
vif0Regs->stat |= VIF0_STAT_VSS;
vif0Regs->stat &= ~VIF0_STAT_VPS;
vif0.vifstalled = 1;
vif0.vifstalled = true;
}
if (value & 0x8)
{
bool cancel = FALSE;
bool cancel = false;
/* Cancel stall, first check if there is a stall to cancel, and then clear VIF0_STAT VSS|VFS|VIS|INT|ER0|ER1 bits */
if (vif0Regs->stat & (VIF0_STAT_VSS | VIF0_STAT_VIS | VIF0_STAT_VFS))
cancel = TRUE;
cancel = true;
vif0Regs->stat &= ~(VIF0_STAT_VSS | VIF0_STAT_VFS | VIF0_STAT_VIS |
VIF0_STAT_INT | VIF0_STAT_ER0 | VIF0_STAT_ER1);
@ -1440,7 +1442,7 @@ void vif0Write32(u32 mem, u32 value)
g_vifCycles = 0;
// loop necessary for spiderman
if (vif0.stallontag == 1)
if (vif0.stallontag)
_chainVIF0();
else
_VIF0chain();
@ -1490,7 +1492,7 @@ void vif0Reset()
psHu64(0x10004000) = 0;
psHu64(0x10004008) = 0;
vif0Regs->stat &= ~VIF0_STAT_VPS;
vif0.done = 1;
vif0.done = true;
vif0Regs->stat &= ~0xF000000; // FQC=0
}
@ -2027,8 +2029,8 @@ int VIF1transfer(u32 *data, int size, int istag)
VIF_LOG("VIF1transfer: size %x (vif1.cmd %x)", size, vif1.cmd);
vif1.irqoffset = 0;
vif1.vifstalled = 0;
vif1.stallontag = 0;
vif1.vifstalled = false;
vif1.stallontag = false;
vif1.vifpacketsize = size;
while (vif1.vifpacketsize > 0)
@ -2086,7 +2088,7 @@ int VIF1transfer(u32 *data, int size, int istag)
++vif1.irq;
if (istag && vif1.tag.size <= vif1.vifpacketsize) vif1.stallontag = 1;
if (istag && vif1.tag.size <= vif1.vifpacketsize) vif1.stallontag = true;
if (vif1.tag.size == 0) break;
}
@ -2100,7 +2102,7 @@ int VIF1transfer(u32 *data, int size, int istag)
if (vif1.irq && vif1.cmd == 0)
{
vif1.vifstalled = 1;
vif1.vifstalled = true;
if (((vif1Regs->code >> 24) & 0x7f) != 0x7)vif1Regs->stat |= VIF1_STAT_VIS; // Note: commenting this out fixes WALL-E
@ -2145,7 +2147,7 @@ void vif1TransferFromMemory()
{
Console::WriteLn("Vif1 Tag BUSERR");
psHu32(DMAC_STAT) |= 1 << 15; //If yes, set BEIS (BUSERR) in DMAC_STAT register
vif1.done = 1;
vif1.done = true;
vif1Regs->stat &= ~0x1f000000;
vif1ch->qwc = 0;
CPU_INT(1, 0);
@ -2221,7 +2223,7 @@ int _VIF1chain()
return ret;
}
int _chainVIF1()
bool _chainVIF1()
{
return vif1.done;//Return Done
}
@ -2233,7 +2235,7 @@ __forceinline void vif1SetupTransfer()
case 0: //Normal
case 1: //Normal (From memory)
vif1.inprogress = 1;
vif1.done = 1;
vif1.done = true;
break;
case 2: //Chain
@ -2278,7 +2280,7 @@ __forceinline void vif1SetupTransfer()
if (vif1ch->chcr & 0x40)
{
if (vif1.vifstalled == 1)
if (vif1.vifstalled)
ret = VIF1transfer(vif1ptag + (2 + vif1.irqoffset), 2 - vif1.irqoffset, 1); //Transfer Tag on stall
else
ret = VIF1transfer(vif1ptag + 2, 2, 1); //Transfer Tag
@ -2297,7 +2299,7 @@ __forceinline void vif1SetupTransfer()
{
VIF_LOG("dmaIrq Set");
vif1.done = 1;
vif1.done = true;
return; //End Transfer
}
break;
@ -2327,16 +2329,16 @@ __forceinline void vif1Interrupt()
}
else if ((vif1ch->qwc > 0) || (vif1.irqoffset > 0))
{
if (vif1.stallontag == 1)
if (vif1.stallontag)
vif1SetupTransfer();
else
_VIF1chain();//CPU_INT(13, vif1ch->qwc * BIAS);
}
}
if (vif1.inprogress == 1) _VIF1chain();
if (vif1.inprogress) _VIF1chain();
if ((vif1.done == 0) || (vif1.inprogress == 1))
if ((!vif1.done) || (vif1.inprogress))
{
if (!(psHu32(DMAC_CTRL) & 0x1))
@ -2351,7 +2353,7 @@ __forceinline void vif1Interrupt()
return;
}
if(vif1.vifstalled && vif1.irq)
if (vif1.vifstalled && vif1.irq)
{
CPU_INT(1, 0);
return; //Dont want to end if vif is stalled.
@ -2413,7 +2415,7 @@ void dmaVIF1()
}
// Chain Mode
vif1.done = 0;
vif1.done = false;
CPU_INT(1, 0);
}
@ -2441,7 +2443,7 @@ void vif1Write32(u32 mem, u32 value)
vif1ch->qwc = 0; //?
psHu64(0x10005000) = 0;
psHu64(0x10005008) = 0;
vif1.done = 1;
vif1.done = true;
vif1Regs->err = 0;
vif1.inprogress = 0;
vif1Regs->stat &= ~(0x1F800000 | VIF1_STAT_INT | VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS | VIF1_STAT_VPS); // FQC=0
@ -2453,7 +2455,7 @@ void vif1Write32(u32 mem, u32 value)
vif1Regs->stat |= VIF1_STAT_VFS;
vif1Regs->stat &= ~VIF1_STAT_VPS;
cpuRegs.interrupt &= ~((1 << 1) | (1 << 10)); //Stop all vif1 DMA's
vif1.vifstalled = 1;
vif1.vifstalled = true;
Console::WriteLn("vif1 force break");
}
if (value & 0x4)
@ -2464,16 +2466,16 @@ void vif1Write32(u32 mem, u32 value)
vif1Regs->stat |= VIF1_STAT_VSS;
vif1Regs->stat &= ~VIF1_STAT_VPS;
cpuRegs.interrupt &= ~((1 << 1) | (1 << 10)); //Stop all vif1 DMA's
vif1.vifstalled = 1;
vif1.vifstalled = true;
}
if (value & 0x8)
{
bool cancel = FALSE;
bool cancel = false;
/* Cancel stall, first check if there is a stall to cancel, and then clear VIF1_STAT VSS|VFS|VIS|INT|ER0|ER1 bits */
if (vif1Regs->stat & (VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS))
{
cancel = TRUE;
cancel = true;
}
vif1Regs->stat &= ~(VIF1_STAT_VSS | VIF1_STAT_VFS | VIF1_STAT_VIS |
@ -2531,8 +2533,8 @@ void vif1Write32(u32 mem, u32 value)
else
{
vif1ch->qwc = 0;
vif1.vifstalled = 0;
vif1.done = 1;
vif1.vifstalled = false;
vif1.done = true;
vif1Regs->stat &= ~0x1F000000; // FQC=0
}
break;
@ -2570,7 +2572,7 @@ void vif1Reset()
psHu64(0x10005000) = 0;
psHu64(0x10005008) = 0;
vif1Regs->stat &= ~VIF1_STAT_VPS;
vif1.done = 1;
vif1.done = true;
cpuRegs.interrupt &= ~((1 << 1) | (1 << 10)); //Stop all vif1 DMA's
vif1Regs->stat &= ~0x1F000000; // FQC=0
}

9
pcsx2/VifDma.h
View File

@ -35,13 +35,12 @@ struct vifStruct {
int qwcalign;
u8 usn;
// The next three should be boolean, and will be next time I break savestate compatability. --arcum42
u8 done;
u8 vifstalled;
u8 stallontag;
bool done;
bool vifstalled;
bool stallontag;
u8 irqoffset; // 32bit offset where next vif code is
u32 savedtag; // need this for backwards compat with save states
u32 savedtag; // need this for backwards compat with save states
u32 vifpacketsize;
u8 inprogress;
u8 dmamode;