mirror of https://github.com/PCSX2/pcsx2.git
Debugger Assembler: BC1(t|f) 24 bit immediates to 16 bit immediates
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@ -599,7 +599,11 @@ bool parsePostfixExpression(PostfixExpression& exp, IExpressionFunctions* funcs,
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}
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}
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}
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}
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if (valueStack.size() != 1) return false;
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if (valueStack.size() != 1)
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{
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error = TRANSLATE("ExpressionParser", "Invalid expression (Too many constants?)");
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return false;
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}
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dest = valueStack[0];
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dest = valueStack[0];
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return true;
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return true;
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}
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}
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@ -637,14 +637,14 @@ bool CMipsInstruction::Validate()
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immediate.value = (immediate.value >> 2) & 0x3FFFFFF;
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immediate.value = (immediate.value >> 2) & 0x3FFFFFF;
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} else if (Opcode.flags & MO_IPCR) // relative 16 bit value
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} else if (Opcode.flags & MO_IPCR) // relative 16 bit value
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{
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{
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int num = (immediate.value-RamPos-4);
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const int num = (immediate.value-RamPos-4) >> 2;
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if (num > 0x20000 || num < (-0x20000))
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if (num > std::numeric_limits<short>::max() || num < std::numeric_limits<short>::min())
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{
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{
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Logger::queueError(Logger::Error,L"Branch target %08X out of range",immediate.value);
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Logger::queueError(Logger::Error,L"Branch target %08X out of range",immediate.value);
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return false;
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return false;
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}
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}
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immediate.value = num >> 2;
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immediate.value = num;
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}
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}
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int immediateBits = getImmediateBits(immediateType);
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int immediateBits = getImmediateBits(immediateType);
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@ -596,10 +596,10 @@ const tMipsOpcode MipsOpcodes[] = {
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// 10 | --- | --- | --- | --- | --- | --- | --- | --- | 10..17
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// 10 | --- | --- | --- | --- | --- | --- | --- | --- | 10..17
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// 11 | --- | --- | --- | --- | --- | --- | --- | --- | 18..1F
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// 11 | --- | --- | --- | --- | --- | --- | --- | --- | 18..1F
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// hi |-------|-------|-------|-------|-------|-------|-------|-------|
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// hi |-------|-------|-------|-------|-------|-------|-------|-------|
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{ "bc1f", "I", MIPS_COP1BC(0x00), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
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{ "bc1f", "i", MIPS_COP1BC(0x00), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
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{ "bc1t", "I", MIPS_COP1BC(0x01), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
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{ "bc1t", "i", MIPS_COP1BC(0x01), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
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{ "bc1fl", "I", MIPS_COP1BC(0x02), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
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{ "bc1fl", "i", MIPS_COP1BC(0x02), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
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{ "bc1tl", "I", MIPS_COP1BC(0x03), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
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{ "bc1tl", "i", MIPS_COP1BC(0x03), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
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// 31---------21------------------------------------------5--------0
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// 31---------21------------------------------------------5--------0
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// |= COP1S | | function|
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// |= COP1S | | function|
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