mirror of https://github.com/PCSX2/pcsx2.git
microVU: more flag stuff (div/sqrt/rsqrt flags set at proper time)
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@960 96395faa-99c1-11dd-bbfe-3dabce05a288
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cottonvibes
parent
5b0d9b6723
commit
a3c1669024
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@ -54,6 +54,7 @@ struct microAllocInfo {
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microTempRegInfo regsTemp; // Temp Pipeline info (used so that new pipeline info isn't conflicting between upper and lower instructions in the same cycle)
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u8 branch; // 0 = No Branch, 1 = B. 2 = BAL, 3~8 = Conditional Branches, 9 = JALR, 10 = JR
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//u8 maxStall; // Helps in computing stalls (stores the max amount of cycles to stall for the current opcodes)
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//u8 divFlag;
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u32 cycles; // Cycles for current block
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u32 count; // Number of VU 64bit instructions ran (starts at 0 for each block)
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u32 curPC; // Current PC
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@ -49,6 +49,7 @@
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#define calcCycles(reg, x) { reg = ((reg > x) ? (reg - x) : 0); }
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#define incP() { mVU->p = (mVU->p+1) & 1; }
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#define incQ() { mVU->q = (mVU->q+1) & 1; }
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#define doUpperOp() { mVUopU<vuIndex, 1>(); mVUdivSet<vuIndex>(); }
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//------------------------------------------------------------------
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// Helper Functions
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@ -69,7 +70,7 @@ microVUt(void) mVUstatusFlagOp() {
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for (; i > 0; i--) {
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incPC2(-2);
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if (isSflag) break;
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mVUinfo &= ~_doStatus;
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mVUinfo &= ~(_doStatus|_doDivFlag);
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}
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iPC = curPC;
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}
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@ -96,13 +97,13 @@ microVUt(void) mVUsetFlags(int* bStatus, int* bMac) {
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iPC = mVUstartPC;
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for (int i = 0; i < xCount; i++) {
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if ((xCount - i) > aCount) mVUstatusFlagOp<vuIndex>(); // Don't Optimize out on the last ~4+ instructions
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if (doStatus||isFSSET) { mVUinfo |= xStatus << 12; } // _fsInstance
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if (doStatus||isFSSET||doDivFlag) { mVUinfo |= xStatus << 12; } // _fsInstance
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if (doMac) { mVUinfo |= xMac << 10; } // _fmInstance
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pStatus = (xStatus + ((mVUstall > 3) ? 3 : mVUstall)) & 3;
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pMac = (xMac + ((mVUstall > 3) ? 3 : mVUstall)) & 3;
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mVUinfo |= pStatus << 18; // _fvsInstance
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mVUinfo |= pMac << 16; // _fvmInstance
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if (doStatus||isFSSET) { xStatus = (xStatus+1) & 3; }
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if (doStatus||isFSSET||doDivFlag) { xStatus = (xStatus+1) & 3; }
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if (doMac) { xMac = (xMac+1) & 3; }
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incPC2(2);
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}
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@ -111,7 +112,7 @@ microVUt(void) mVUsetFlags(int* bStatus, int* bMac) {
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// Setup Last 4 instances of Status/Mac flags (needed for accurate block linking)
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iPC = endPC;
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for (int i = 3, int j = 3, int ii = 1, int jj = 3; aCount > 0; ii++, aCount--) {
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if (doStatus && (i >= 0)) {
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if ((doStatus||isFSSET||doDivFlag) && (i >= 0)) {
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for (; (ii > 0 && i >= 0); ii--) { xStatus = (xStatus-1) & 3; bStatus[i] = xStatus; i--; }
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}
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if (doMac && (j >= 0)) {
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@ -172,8 +173,9 @@ microVUt(void) mVUincCycles(int x) {
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calcCycles(mVUregs.VI[z], x);
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}
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if (mVUregs.q) {
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calcCycles(mVUregs.q, x);
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if (!mVUregs.q) { incQ(); } // Do Status Flag Merging Stuff?
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if (mVUregs.q > 4) { calcCycles(mVUregs.q, x); if (mVUregs.q <= 4) { mVUinfo |= _doDivFlag; } }
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else { calcCycles(mVUregs.q, x); }
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if (!mVUregs.q) { incQ(); }
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}
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if (mVUregs.p) {
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calcCycles(mVUregs.p, x);
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@ -202,6 +204,15 @@ microVUt(void) mVUsetCycles() {
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mVUregs.xgkick = mVUregsTemp.xgkick;
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}
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microVUt(void) mVUdivSet() {
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microVU* mVU = mVUx;
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int flagReg1, flagReg2;
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getFlagReg(flagReg1, fsInstance);
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if (!doStatus) { getFlagReg(flagReg2, fpsInstance); MOV16RtoR(flagReg1, flagReg2); }
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AND16ItoR(flagReg1, 0xfcf);
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OR16MtoR (flagReg1, (uptr)&mVU->divFlag);
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}
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//------------------------------------------------------------------
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// Recompiler
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//------------------------------------------------------------------
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@ -254,9 +265,9 @@ microVUx(void*) mVUcompile(u32 startPC, u32 pipelineState, microRegInfo* pState,
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if (isEOB) { x = 0; }
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//if (isBranch2) { mVUopU<vuIndex, 1>(); incPC(2); }
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if (isNop) { mVUopU<vuIndex, 1>(); if (curI & _Ibit_) { incPC(1); mVU->iReg = curI; } else { incPC(1); } }
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else if (!swapOps) { mVUopU<vuIndex, 1>(); incPC(1); mVUopL<vuIndex, 1>(); }
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else { incPC(1); mVUopL<vuIndex, 1>(); incPC(-1); mVUopU<vuIndex, 1>(); incPC(1); }
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if (isNop) { doUpperOp(); if (curI & _Ibit_) { incPC(1); mVU->iReg = curI; } else { incPC(1); } }
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else if (!swapOps) { doUpperOp(); incPC(1); mVUopL<vuIndex, 1>(); }
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else { incPC(1); mVUopL<vuIndex, 1>(); incPC(-1); doUpperOp(); incPC(1); }
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if (!isBdelay) { incPC(1); }
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else {
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@ -474,7 +474,7 @@ microVUf(void) mVU_FCSET() {
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microVUf(void) mVU_FMAND() {
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microVU* mVU = mVUx;
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if (!recPass) {}
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if (!recPass) { mVUanalyzeMflag<vuIndex>(_Fs_, _Ft_); }
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else {
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mVUallocMFLAGa<vuIndex>(gprT1, fvmInstance);
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mVUallocVIa<vuIndex>(gprT2, _Fs_);
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@ -485,7 +485,7 @@ microVUf(void) mVU_FMAND() {
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microVUf(void) mVU_FMEQ() {
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microVU* mVU = mVUx;
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if (!recPass) {}
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if (!recPass) { mVUanalyzeMflag<vuIndex>(_Fs_, _Ft_); }
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else {
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mVUallocMFLAGa<vuIndex>(gprT1, fvmInstance);
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mVUallocVIa<vuIndex>(gprT2, _Fs_);
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@ -498,7 +498,7 @@ microVUf(void) mVU_FMEQ() {
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microVUf(void) mVU_FMOR() {
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microVU* mVU = mVUx;
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if (!recPass) {}
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if (!recPass) { mVUanalyzeMflag<vuIndex>(_Fs_, _Ft_); }
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else {
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mVUallocMFLAGa<vuIndex>(gprT1, fvmInstance);
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mVUallocVIa<vuIndex>(gprT2, _Fs_);
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@ -547,12 +547,11 @@ microVUf(void) mVU_FSSET() {
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microVU* mVU = mVUx;
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if (!recPass) { mVUanalyzeFSSET<vuIndex>(); }
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else {
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int flagReg = gprT1;
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if (doStatus) { getFlagReg(flagReg, fsInstance); } // Get status result from upper instruction
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else { mVUallocSFLAGa<vuIndex>(flagReg, fpsInstance); } // Get status result from last status setting instruction
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AND16ItoR(flagReg, 0x03f); // Remember not to modify upper 16 bits because of mac flag
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OR16ItoR(flagReg, (_Imm12_ & 0xfc0));
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if (!doStatus) { mVUallocSFLAGb<vuIndex>(flagReg, fsInstance); }
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int flagReg1, flagReg2;
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getFlagReg(flagReg1, fsInstance);
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if (!(doStatus||doDivFlag)) { getFlagReg(flagReg2, fpsInstance); MOV16RtoR(flagReg1, flagReg2); } // Get status result from last status setting instruction
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AND16ItoR(flagReg1, 0x03f); // Remember not to modify upper 16 bits because of mac flag
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OR16ItoR (flagReg1, (_Imm12_ & 0xfc0));
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}
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}
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@ -185,7 +185,9 @@ declareAllVariables
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#define _writesVI (1<<25) // Current Instruction writes to VI
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#define _swapOps (1<<26) // Runs Lower Instruction Before Upper Instruction
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#define _isFSSSET (1<<27) // Cur Instruction is FSSET
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//#define _isBranch2 (1<<28) // Cur Instruction is a Branch that writes VI regs (BAL/JALR)
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#define _doDivFlag (1<<28) // Transfer Div flag to Status Flag
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//#define _isBranch2 (1<<31) // Cur Instruction is a Branch that writes VI regs (BAL/JALR)
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#define isNOP (mVUinfo & (1<<0))
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#define isBranch (mVUinfo & (1<<1))
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@ -214,7 +216,8 @@ declareAllVariables
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#define writesVI (mVUinfo & (1<<25))
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#define swapOps (mVUinfo & (1<<26))
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#define isFSSET (mVUinfo & (1<<27))
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//#define isBranch2 (mVUinfo & (1<<28))
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#define doDivFlag (mVUinfo & (1<<28))
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//#define isBranch2 (mVUinfo & (1<<31))
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#define isMMX(_VIreg_) (_VIreg_ >= 1 && _VIreg_ <=9)
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#define mmVI(_VIreg_) (_VIreg_ - 1)
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