From a2a1d58b4ba4bd45746e95c964098b7e73fea09b Mon Sep 17 00:00:00 2001 From: cottonvibes Date: Sun, 19 Apr 2009 02:54:56 +0000 Subject: [PATCH] backup git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1012 96395faa-99c1-11dd-bbfe-3dabce05a288 --- pcsx2/x86/microVU_Analyze.inl | 21 ++++++++++++++++- pcsx2/x86/microVU_Compile.inl | 26 ++++++++++----------- pcsx2/x86/microVU_Execute.inl | 4 ++-- pcsx2/x86/microVU_Lower.inl | 34 ++++++++++++++++++++++----- pcsx2/x86/microVU_Upper.inl | 44 +++++++++++++++++------------------ 5 files changed, 84 insertions(+), 45 deletions(-) diff --git a/pcsx2/x86/microVU_Analyze.inl b/pcsx2/x86/microVU_Analyze.inl index 9381c317bf..4581d937fd 100644 --- a/pcsx2/x86/microVU_Analyze.inl +++ b/pcsx2/x86/microVU_Analyze.inl @@ -51,6 +51,7 @@ microVUt(void) mVUanalyzeFMAC1(int Fd, int Fs, int Ft) { microVU* mVU = mVUx; + mVUlog("microVU: FMAC1 Opcode"); mVUinfo |= _doStatus; analyzeReg1(Fs); analyzeReg1(Ft); @@ -63,6 +64,7 @@ microVUt(void) mVUanalyzeFMAC1(int Fd, int Fs, int Ft) { microVUt(void) mVUanalyzeFMAC2(int Fs, int Ft) { microVU* mVU = mVUx; + mVUlog("microVU: FMAC2 Opcode"); analyzeReg1(Fs); analyzeReg2(Ft); } @@ -82,6 +84,7 @@ microVUt(void) mVUanalyzeFMAC2(int Fs, int Ft) { microVUt(void) mVUanalyzeFMAC3(int Fd, int Fs, int Ft) { microVU* mVU = mVUx; + mVUlog("microVU: FMAC3 Opcode"); mVUinfo |= _doStatus; analyzeReg1(Fs); analyzeReg3(Ft); @@ -98,6 +101,7 @@ microVUt(void) mVUanalyzeFMAC3(int Fd, int Fs, int Ft) { microVUt(void) mVUanalyzeFMAC4(int Fs, int Ft) { microVU* mVU = mVUx; + mVUlog("microVU: FMAC4 Opcode"); analyzeReg1(Fs); analyzeReg4(Ft); } @@ -111,6 +115,7 @@ microVUt(void) mVUanalyzeFMAC4(int Fs, int Ft) { microVUt(void) mVUanalyzeIALU1(int Id, int Is, int It) { microVU* mVU = mVUx; + //mVUlog("microVU: IALU1 Opcode"); if (!Id) { mVUinfo |= _isNOP; } analyzeVIreg1(Is); analyzeVIreg1(It); @@ -119,6 +124,7 @@ microVUt(void) mVUanalyzeIALU1(int Id, int Is, int It) { microVUt(void) mVUanalyzeIALU2(int Is, int It) { microVU* mVU = mVUx; + //mVUlog("microVU: IALU2 Opcode"); if (!It) { mVUinfo |= _isNOP; } analyzeVIreg1(Is); analyzeVIreg2(It, 1); @@ -140,6 +146,7 @@ microVUt(void) mVUanalyzeIALU2(int Is, int It) { microVUt(void) mVUanalyzeMR32(int Fs, int Ft) { microVU* mVU = mVUx; + mVUlog("microVU: MR32 Opcode"); if (!Ft) { mVUinfo |= _isNOP; } analyzeReg6(Fs); analyzeReg2(Ft); @@ -165,6 +172,7 @@ microVUt(void) mVUanalyzeMR32(int Fs, int Ft) { microVUt(void) mVUanalyzeFDIV(int Fs, int Fsf, int Ft, int Ftf, u8 xCycles) { microVU* mVU = mVUx; + mVUlog("microVU: DIV Opcode"); analyzeReg5(Fs, Fsf); analyzeReg5(Ft, Ftf); analyzeQreg(xCycles); @@ -176,12 +184,14 @@ microVUt(void) mVUanalyzeFDIV(int Fs, int Fsf, int Ft, int Ftf, u8 xCycles) { microVUt(void) mVUanalyzeEFU1(int Fs, int Fsf, u8 xCycles) { microVU* mVU = mVUx; + mVUlog("microVU: EFU Opcode"); analyzeReg5(Fs, Fsf); analyzePreg(xCycles); } microVUt(void) mVUanalyzeEFU2(int Fs, u8 xCycles) { microVU* mVU = mVUx; + mVUlog("microVU: EFU Opcode"); analyzeReg1(Fs); analyzePreg(xCycles); } @@ -191,7 +201,8 @@ microVUt(void) mVUanalyzeEFU2(int Fs, u8 xCycles) { //------------------------------------------------------------------ microVUt(void) mVUanalyzeMFP(int Ft) { - microVU* mVU = mVUx; // ToDo: Needs special info for P reg? + microVU* mVU = mVUx; + mVUlog("microVU: MFP Opcode"); if (!Ft) { mVUinfo |= _isNOP; } analyzeReg2(Ft); } @@ -202,6 +213,7 @@ microVUt(void) mVUanalyzeMFP(int Ft) { microVUt(void) mVUanalyzeLQ(int Ft, int Is, bool writeIs) { microVU* mVU = mVUx; + //mVUlog("microVU: LQ Opcode"); analyzeVIreg1(Is); analyzeReg2(Ft); if (!Ft) { mVUinfo |= (writeIs && Is) ? _noWriteVF : _isNOP; } @@ -214,6 +226,7 @@ microVUt(void) mVUanalyzeLQ(int Ft, int Is, bool writeIs) { microVUt(void) mVUanalyzeSQ(int Fs, int It, bool writeIt) { microVU* mVU = mVUx; + mVUlog("microVU: SQ Opcode"); analyzeReg1(Fs); analyzeVIreg1(It); if (writeIt) { analyzeVIreg2(It, 1); } @@ -227,12 +240,14 @@ microVUt(void) mVUanalyzeSQ(int Fs, int It, bool writeIt) { microVUt(void) mVUanalyzeR1(int Fs, int Fsf) { microVU* mVU = mVUx; + mVUlog("microVU: R-reg Opcode"); analyzeReg5(Fs, Fsf); analyzeRreg(); } microVUt(void) mVUanalyzeR2(int Ft, bool canBeNOP) { microVU* mVU = mVUx; + mVUlog("microVU: R-reg Opcode"); if (!Ft) { mVUinfo |= ((canBeNOP) ? _isNOP : _noWriteVF); } analyzeReg2(Ft); analyzeRreg(); @@ -244,6 +259,7 @@ microVUt(void) mVUanalyzeR2(int Ft, bool canBeNOP) { microVUt(void) mVUanalyzeSflag(int It) { microVU* mVU = mVUx; + mVUlog("microVU: Sflag Opcode"); if (!It) { mVUinfo |= _isNOP; } else { // Sets _isSflag at instruction that FSxxx opcode reads it's status flag from mVUinfo |= _swapOps; @@ -259,6 +275,7 @@ microVUt(void) mVUanalyzeSflag(int It) { microVUt(void) mVUanalyzeFSSET() { microVU* mVU = mVUx; mVUinfo |= _isFSSET; + mVUlog("microVU: FSSET Opcode"); // mVUinfo &= ~_doStatus; // Note: I'm not entirely sure if the non-sticky flags // should be taken from the current upper instruction @@ -272,6 +289,7 @@ microVUt(void) mVUanalyzeFSSET() { microVUt(void) mVUanalyzeMflag(int Is, int It) { microVU* mVU = mVUx; + mVUlog("microVU: Mflag Opcode"); if (!It) { mVUinfo |= _isNOP; } else { // Need set _doMac for 4 previous Ops (need to do all 4 because stalls could change the result needed) mVUinfo |= _swapOps; @@ -296,6 +314,7 @@ microVUt(void) mVUanalyzeMflag(int Is, int It) { microVUt(void) mVUanalyzeXGkick(int Fs, int xCycles) { microVU* mVU = mVUx; + mVUlog("microVU: XGkick Opcode"); analyzeVIreg1(Fs); analyzeXGkick1(); analyzeXGkick2(xCycles); diff --git a/pcsx2/x86/microVU_Compile.inl b/pcsx2/x86/microVU_Compile.inl index b7699d1db2..ad468e62f7 100644 --- a/pcsx2/x86/microVU_Compile.inl +++ b/pcsx2/x86/microVU_Compile.inl @@ -207,9 +207,9 @@ microVUt(void) mVUincCycles(int x) { microVUt(void) mVUsetCycles() { microVU* mVU = mVUx; incCycles(mVUstall); - if (mVUregsTemp.VFreg[0] == mVUregsTemp.VFreg[1] && mVUregsTemp.VFreg[0]) { // If upper Op && lower Op write to same VF reg - mVUinfo |= (mVUregsTemp.r || mVUregsTemp.VI) ? _noWriteVF : _isNOP; // If lower Op doesn't modify anything else, then make it a NOP - mVUregsTemp.VF[1].x = aMax(mVUregsTemp.VF[0].x, mVUregsTemp.VF[1].x); // Use max cycles from each vector + if (mVUregsTemp.VFreg[0] == mVUregsTemp.VFreg[1] && mVUregsTemp.VFreg[0]) { // If upper Op && lower Op write to same VF reg + mVUinfo |= (mVUregsTemp.r || mVUregsTemp.VI) ? _noWriteVF : _isNOP; // If lower Op doesn't modify anything else, then make it a NOP + mVUregsTemp.VF[1].x = aMax(mVUregsTemp.VF[0].x, mVUregsTemp.VF[1].x); // Use max cycles from each vector mVUregsTemp.VF[1].y = aMax(mVUregsTemp.VF[0].y, mVUregsTemp.VF[1].y); mVUregsTemp.VF[1].z = aMax(mVUregsTemp.VF[0].z, mVUregsTemp.VF[1].z); mVUregsTemp.VF[1].w = aMax(mVUregsTemp.VF[0].w, mVUregsTemp.VF[1].w); @@ -251,14 +251,14 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) { microBlock* pBlock = mVUblocks[startPC/8]->search((microRegInfo*)pState); if (pBlock) { return pBlock->x86ptrStart; } - mVUlog("mVUcompile First Pass"); + //mVUlog("mVUcompile First Pass"); // First Pass iPC = startPC / 4; mVUbranch = 0; mVUstartPC = iPC; mVUcount = 0; - mVUcycles = 1; // Skips "M" phase, and starts counting cycles at "T" stage + mVUcycles = 0; // Skips "M" phase, and starts counting cycles at "T" stage mVU->p = 0; // All blocks start at p index #0 mVU->q = 0; // All blocks start at q index #0 memcpy_fast(&mVUregs, (microRegInfo*)pState, sizeof(microRegInfo)); // Loads up Pipeline State Info @@ -267,6 +267,7 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) { for (int branch = 0;; ) { incPC(1); + incCycles(1); startLoop(); mVUopU(); if (curI & _Ebit_) { branch = 1; } @@ -281,32 +282,28 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) { else if (branch == 1) { branch = 2; } if (mVUbranch) { branch = 3; mVUbranch = 0; mVUinfo |= _isBranch; } incPC(1); - incCycles(1); mVUcount++; } - mVUlog("mVUcompile mVUsetFlags"); + //mVUlog("mVUcompile mVUsetFlags"); // Sets Up Flag instances int bStatus[4]; int bMac[4]; mVUsetFlags(bStatus, bMac); - mVUlog("mVUcompile Second Pass"); + //mVUlog("mVUcompile Second Pass"); //write8(0xcc); // Second Pass iPC = mVUstartPC; mVUbranch = 0; - int test = 0; - for (bool x = 1; x; ) { - if (isEOB) { x = 0; } + int x; + for (x = 0; x < (vuIndex ? (0x3fff/8) : (0xfff/8)); x++) { + if (isEOB) { x = 0xffff; } if (isNOP) { incPC(1); doUpperOp(); if (curI & _Ibit_) { incPC(-1); mVU->iReg = curI; incPC(-1); } } else if (!swapOps) { incPC(1); doUpperOp(); incPC(-1); mVUopL(); incPC(1); } else { mVUopL(); incPC(1); doUpperOp(); } - - test++; - if (test > 0x3ff) { mVUlog("microVU: Possible infinite compiling loop!"); x = 0; test = 0; } if (!isBdelay) { incPC(1); } else { @@ -371,6 +368,7 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) { } } mVUlog("mVUcompile ebit"); + if (x == (vuIndex?(0x3fff/8):(0xfff/8))) { mVUlog("microVU: Possible infinite compiling loop!"); } // Do E-bit end stuff here incCycles(55); // Ensures Valid P/Q instances diff --git a/pcsx2/x86/microVU_Execute.inl b/pcsx2/x86/microVU_Execute.inl index 1fdf4c7929..45998cc3e7 100644 --- a/pcsx2/x86/microVU_Execute.inl +++ b/pcsx2/x86/microVU_Execute.inl @@ -157,7 +157,7 @@ void __fastcall startVU0(u32 startPC, u32 cycles) { ((mVUrecCall)microVU0.start void __fastcall startVU1(u32 startPC, u32 cycles) { ((mVUrecCall)microVU1.startFunct)(startPC, cycles); } void* __fastcall mVUexecuteVU0(u32 startPC, u32 cycles) { return mVUexecute<0>(startPC, cycles); } void* __fastcall mVUexecuteVU1(u32 startPC, u32 cycles) { return mVUexecute<1>(startPC, cycles); } -void __fastcall mVUcleanUpVU0() { mVUcleanUp<0>(); } -void __fastcall mVUcleanUpVU1() { mVUcleanUp<1>(); } +void __fastcall mVUcleanUpVU0() { mVUcleanUp<0>(); } +void __fastcall mVUcleanUpVU1() { mVUcleanUp<1>(); } #endif //PCSX2_MICROVU diff --git a/pcsx2/x86/microVU_Lower.inl b/pcsx2/x86/microVU_Lower.inl index ef63010029..7c00a6b7a6 100644 --- a/pcsx2/x86/microVU_Lower.inl +++ b/pcsx2/x86/microVU_Lower.inl @@ -563,6 +563,7 @@ microVUf(void) mVU_IADD() { microVU* mVU = mVUx; if (!recPass) { mVUanalyzeIALU1(_Fd_, _Fs_, _Ft_); } else { + mVUlog("IADD"); mVUallocVIa(gprT1, _Fs_); if (_Ft_ != _Fs_) { mVUallocVIa(gprT2, _Ft_); @@ -577,6 +578,7 @@ microVUf(void) mVU_IADDI() { microVU* mVU = mVUx; if (!recPass) { mVUanalyzeIALU2(_Fs_, _Ft_); } else { + mVUlog("IADDI"); mVUallocVIa(gprT1, _Fs_); ADD16ItoR(gprT1, _Imm5_); mVUallocVIb(gprT1, _Ft_); @@ -587,8 +589,9 @@ microVUf(void) mVU_IADDIU() { microVU* mVU = mVUx; if (!recPass) { mVUanalyzeIALU2(_Fs_, _Ft_); } else { + mVUlog("IADDIU"); mVUallocVIa(gprT1, _Fs_); - ADD16ItoR(gprT1, _Imm12_); + ADD16ItoR(gprT1, _Imm15_); mVUallocVIb(gprT1, _Ft_); } } @@ -597,6 +600,7 @@ microVUf(void) mVU_IAND() { microVU* mVU = mVUx; if (!recPass) { mVUanalyzeIALU1(_Fd_, _Fs_, _Ft_); } else { + mVUlog("IAND"); mVUallocVIa(gprT1, _Fs_); if (_Ft_ != _Fs_) { mVUallocVIa(gprT2, _Ft_); @@ -610,6 +614,7 @@ microVUf(void) mVU_IOR() { microVU* mVU = mVUx; if (!recPass) { mVUanalyzeIALU1(_Fd_, _Fs_, _Ft_); } else { + mVUlog("IOR"); mVUallocVIa(gprT1, _Fs_); if (_Ft_ != _Fs_) { mVUallocVIa(gprT2, _Ft_); @@ -623,6 +628,7 @@ microVUf(void) mVU_ISUB() { microVU* mVU = mVUx; if (!recPass) { mVUanalyzeIALU1(_Fd_, _Fs_, _Ft_); } else { + mVUlog("ISUB"); if (_Ft_ != _Fs_) { mVUallocVIa(gprT1, _Fs_); mVUallocVIa(gprT2, _Ft_); @@ -640,8 +646,9 @@ microVUf(void) mVU_ISUBIU() { microVU* mVU = mVUx; if (!recPass) { mVUanalyzeIALU2(_Fs_, _Ft_); } else { + mVUlog("ISUBIU"); mVUallocVIa(gprT1, _Fs_); - SUB16ItoR(gprT1, _Imm12_); + SUB16ItoR(gprT1, _Imm15_); mVUallocVIb(gprT1, _Ft_); } } @@ -654,6 +661,7 @@ microVUf(void) mVU_MFIR() { microVU* mVU = mVUx; if (!recPass) { if (!_Ft_) { mVUinfo |= _isNOP; } analyzeVIreg1(_Fs_); analyzeReg2(_Ft_); } else { + mVUlog("MFIR"); mVUallocVIa(gprT1, _Fs_); MOVSX32R16toR(gprT1, gprT1); SSE2_MOVD_R_to_XMM(xmmT1, gprT1); @@ -666,6 +674,7 @@ microVUf(void) mVU_MFP() { microVU* mVU = mVUx; if (!recPass) { mVUanalyzeMFP(_Ft_); } else { + mVUlog("MFP"); getPreg(xmmFt); mVUsaveReg(xmmFt, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W); } @@ -675,6 +684,7 @@ microVUf(void) mVU_MOVE() { microVU* mVU = mVUx; if (!recPass) { if (!_Ft_ || (_Ft_ == _Fs_)) { mVUinfo |= _isNOP; } analyzeReg1(_Fs_); analyzeReg2(_Ft_); } else { + mVUlog("MOVE"); mVUloadReg(xmmT1, (uptr)&mVU->regs->VF[_Fs_].UL[0], _X_Y_Z_W); mVUsaveReg(xmmT1, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W); } @@ -684,6 +694,7 @@ microVUf(void) mVU_MR32() { microVU* mVU = mVUx; if (!recPass) { mVUanalyzeMR32(_Fs_, _Ft_); } else { + mVUlog("MR32"); mVUloadReg(xmmT1, (uptr)&mVU->regs->VF[_Fs_].UL[0], (_X_Y_Z_W == 8) ? 4 : 15); if (_X_Y_Z_W != 8) { SSE2_PSHUFD_XMM_to_XMM(xmmT1, xmmT1, 0x39); } mVUsaveReg(xmmT1, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W); @@ -694,6 +705,7 @@ microVUf(void) mVU_MTIR() { microVU* mVU = mVUx; if (!recPass) { if (!_Ft_) { mVUinfo |= _isNOP; } analyzeReg5(_Fs_, _Fsf_); analyzeVIreg2(_Ft_, 1); } else { + mVUlog("MTIR"); MOVZX32M16toR(gprT1, (uptr)&mVU->regs->VF[_Fs_].UL[_Fsf_]); mVUallocVIb(gprT1, _Ft_); } @@ -707,6 +719,7 @@ microVUf(void) mVU_ILW() { microVU* mVU = mVUx; if (!recPass) { if (!_Ft_) { mVUinfo |= _isNOP; } analyzeVIreg1(_Fs_); analyzeVIreg2(_Ft_, 4); } else { + mVUlog("ILW"); if (!_Fs_) { MOVZX32M16toR( gprT1, (uptr)mVU->regs->Mem + getVUmem(_Imm11_) + offsetSS ); mVUallocVIb(gprT1, _Ft_); @@ -726,6 +739,7 @@ microVUf(void) mVU_ILWR() { microVU* mVU = mVUx; if (!recPass) { if (!_Ft_) { mVUinfo |= _isNOP; } analyzeVIreg1(_Fs_); analyzeVIreg2(_Ft_, 4); } else { + mVUlog("ILWR"); if (!_Fs_) { MOVZX32M16toR(gprT1, (uptr)mVU->regs->Mem + offsetSS); mVUallocVIb(gprT1, _Ft_); @@ -748,6 +762,7 @@ microVUf(void) mVU_ISW() { microVU* mVU = mVUx; if (!recPass) { analyzeVIreg1(_Fs_); analyzeVIreg1(_Ft_); } else { + mVUlog("ISW"); if (!_Fs_) { int imm = getVUmem(_Imm11_); mVUallocVIa(gprT1, _Ft_); @@ -773,6 +788,7 @@ microVUf(void) mVU_ISWR() { microVU* mVU = mVUx; if (!recPass) { analyzeVIreg1(_Fs_); analyzeVIreg1(_Ft_); } else { + mVUlog("ISWR"); if (!_Fs_) { mVUallocVIa(gprT1, _Ft_); if (_X) MOV32RtoM((uptr)mVU->regs->Mem, gprT1); @@ -801,10 +817,12 @@ microVUf(void) mVU_LQ() { if (!recPass) { mVUanalyzeLQ(_Ft_, _Fs_, 0); } else { if (!_Fs_) { + mVUlog("LQ1"); mVUloadReg(xmmFt, (uptr)mVU->regs->Mem + getVUmem(_Imm11_), _X_Y_Z_W); mVUsaveReg(xmmFt, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W); } else { + mVUlog("LQ2"); mVUallocVIa(gprT1, _Fs_); ADD32ItoR(gprT1, _Imm11_); mVUaddrFix(gprT1); @@ -819,13 +837,15 @@ microVUf(void) mVU_LQD() { if (!recPass) { mVUanalyzeLQ(_Ft_, _Fs_, 1); } else { if (!_Fs_ && !noWriteVF) { + mVUlog("LQD1"); mVUloadReg(xmmFt, (uptr)mVU->regs->Mem, _X_Y_Z_W); mVUsaveReg(xmmFt, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W); } else { + mVUlog("LQD2"); mVUallocVIa(gprT1, _Fs_); SUB16ItoR(gprT1, 1); - mVUallocVIb(gprT1, _Fs_); // ToDo: Backup to memory check. + mVUallocVIb(gprT1, _Fs_); if (!noWriteVF) { mVUaddrFix(gprT1); mVUloadReg2(xmmFt, gprT1, (uptr)mVU->regs->Mem, _X_Y_Z_W); @@ -840,11 +860,13 @@ microVUf(void) mVU_LQI() { if (!recPass) { mVUanalyzeLQ(_Ft_, _Fs_, 1); } else { if (!_Fs_ && !noWriteVF) { + mVUlog("LQI1"); mVUloadReg(xmmFt, (uptr)mVU->regs->Mem, _X_Y_Z_W); mVUsaveReg(xmmFt, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W); } else { - mVUallocVIa((_Ft_) ? gprT1 : gprT2, _Fs_); + mVUlog("LQI2"); + mVUallocVIa((!noWriteVF) ? gprT1 : gprT2, _Fs_); if (!noWriteVF) { MOV32RtoR(gprT2, gprT1); mVUaddrFix(gprT1); @@ -852,7 +874,7 @@ microVUf(void) mVU_LQI() { mVUsaveReg(xmmFt, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W); } ADD16ItoR(gprT2, 1); - mVUallocVIb(gprT2, _Fs_); // ToDo: Backup to memory check. + mVUallocVIb(gprT2, _Fs_); } } } @@ -890,7 +912,7 @@ microVUf(void) mVU_SQD() { else { mVUallocVIa(gprT1, _Ft_); SUB16ItoR(gprT1, 1); - mVUallocVIb(gprT1, _Ft_); // ToDo: Backup to memory check. + mVUallocVIb(gprT1, _Ft_); mVUaddrFix(gprT1); getReg7(xmmFs, _Fs_); mVUsaveReg2(xmmFs, gprT1, (uptr)mVU->regs->Mem, _X_Y_Z_W); diff --git a/pcsx2/x86/microVU_Upper.inl b/pcsx2/x86/microVU_Upper.inl index ab084d824b..94582273f9 100644 --- a/pcsx2/x86/microVU_Upper.inl +++ b/pcsx2/x86/microVU_Upper.inl @@ -87,7 +87,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX mVUallocFMAC1a(Fd, Fs, Ft); \ if (_XYZW_SS) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \ else SSE_##operation##PS_XMM_to_XMM(Fs, Ft); \ - mVUupdateFlags(Fd, xmmT1, Ft, _X_Y_Z_W, 1); \ + mVUupdateFlags(Fd, xmmT1, xmmT2, _X_Y_Z_W, 1); \ mVUallocFMAC1b(Fd); \ } \ } @@ -100,7 +100,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX mVUallocFMAC3a(Fd, Fs, Ft); \ if (_XYZW_SS) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \ else SSE_##operation##PS_XMM_to_XMM(Fs, Ft); \ - mVUupdateFlags(Fd, xmmT1, Ft, _X_Y_Z_W, 1); \ + mVUupdateFlags(Fd, xmmT1, xmmT2, _X_Y_Z_W, 1); \ mVUallocFMAC3b(Fd); \ } \ } @@ -113,7 +113,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX mVUallocFMAC4a(ACC, Fs, Ft); \ if (_X_Y_Z_W == 8) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \ else SSE_##operation##PS_XMM_to_XMM(Fs, Ft); \ - mVUupdateFlags(Fs, xmmT1, Ft, _X_Y_Z_W, 0); \ + mVUupdateFlags(Fs, xmmT1, xmmT2, _X_Y_Z_W, 0); \ mVUallocFMAC4b(ACC, Fs); \ } \ } @@ -126,7 +126,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX mVUallocFMAC5a(ACC, Fs, Ft); \ if (_X_Y_Z_W == 8) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \ else SSE_##operation##PS_XMM_to_XMM(Fs, Ft); \ - mVUupdateFlags(Fs, xmmT1, Ft, _X_Y_Z_W, 0); \ + mVUupdateFlags(Fs, xmmT1, xmmT2, _X_Y_Z_W, 0); \ mVUallocFMAC5b(ACC, Fs); \ } \ } @@ -139,7 +139,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX mVUallocFMAC6a(Fd, Fs, Ft); \ if (_XYZW_SS) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \ else SSE_##operation##PS_XMM_to_XMM(Fs, Ft); \ - mVUupdateFlags(Fd, xmmT1, Ft, _X_Y_Z_W, 1); \ + mVUupdateFlags(Fd, xmmT1, xmmT2, _X_Y_Z_W, 1); \ mVUallocFMAC6b(Fd); \ } \ } @@ -152,7 +152,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX mVUallocFMAC7a(ACC, Fs, Ft); \ if (_X_Y_Z_W == 8) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \ else SSE_##operation##PS_XMM_to_XMM(Fs, Ft); \ - mVUupdateFlags(Fs, xmmT1, Ft, _X_Y_Z_W, 0); \ + mVUupdateFlags(Fs, xmmT1, xmmT2, _X_Y_Z_W, 0); \ mVUallocFMAC7b(ACC, Fs); \ } \ } @@ -171,7 +171,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX SSE_MULPS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##PS_XMM_to_XMM(Fs, ACC); \ } \ - mVUupdateFlags(Fd, xmmT1, Ft, _X_Y_Z_W, 0); \ + mVUupdateFlags(Fd, xmmT1, xmmT2, _X_Y_Z_W, 0); \ mVUallocFMAC8b(Fd); \ } \ } @@ -190,7 +190,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX SSE_MULPS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##PS_XMM_to_XMM(ACC, Fs); \ } \ - mVUupdateFlags(Fd, Fs, Ft, _X_Y_Z_W, 0); \ + mVUupdateFlags(Fd, Fs, xmmT2, _X_Y_Z_W, 0); \ mVUallocFMAC9b(Fd); \ } \ } @@ -209,7 +209,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX SSE_MULPS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##PS_XMM_to_XMM(Fs, ACC); \ } \ - mVUupdateFlags(Fd, xmmT1, Ft, _X_Y_Z_W, 0); \ + mVUupdateFlags(Fd, xmmT1, xmmT2, _X_Y_Z_W, 0); \ mVUallocFMAC10b(Fd); \ } \ } @@ -228,7 +228,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX SSE_MULPS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##PS_XMM_to_XMM(ACC, Fs); \ } \ - mVUupdateFlags(Fd, Fs, Ft, _X_Y_Z_W, 0); \ + mVUupdateFlags(Fd, Fs, xmmT2, _X_Y_Z_W, 0); \ mVUallocFMAC11b(Fd); \ } \ } @@ -247,7 +247,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX SSE_MULPS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##PS_XMM_to_XMM(Fs, ACC); \ } \ - mVUupdateFlags(Fd, xmmT1, Ft, _X_Y_Z_W, 0); \ + mVUupdateFlags(Fd, xmmT1, xmmT2, _X_Y_Z_W, 0); \ mVUallocFMAC12b(Fd); \ } \ } @@ -266,7 +266,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX SSE_MULPS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##PS_XMM_to_XMM(ACC, Fs); \ } \ - mVUupdateFlags(Fd, Fs, Ft, _X_Y_Z_W, 0); \ + mVUupdateFlags(Fd, Fs, xmmT2, _X_Y_Z_W, 0); \ mVUallocFMAC13b(Fd); \ } \ } @@ -285,7 +285,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX SSE_MULPS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##PS_XMM_to_XMM(ACCr, Fs); \ } \ - mVUupdateFlags(ACCr, Fs, Ft, _X_Y_Z_W, 0); \ + mVUupdateFlags(ACCr, Fs, xmmT2, _X_Y_Z_W, 0); \ mVUallocFMAC14b(ACCw, ACCr); \ } \ } @@ -304,7 +304,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX SSE_MULPS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##PS_XMM_to_XMM(ACCr, Fs); \ } \ - mVUupdateFlags(ACCr, Fs, Ft, _X_Y_Z_W, 0); \ + mVUupdateFlags(ACCr, Fs, xmmT2, _X_Y_Z_W, 0); \ mVUallocFMAC15b(ACCw, ACCr); \ } \ } @@ -323,7 +323,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX SSE_MULPS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##PS_XMM_to_XMM(ACCr, Fs); \ } \ - mVUupdateFlags(ACCr, Fs, Ft, _X_Y_Z_W, 0); \ + mVUupdateFlags(ACCr, Fs, xmmT2, _X_Y_Z_W, 0); \ mVUallocFMAC16b(ACCw, ACCr); \ } \ } @@ -335,7 +335,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX int ACC, Fs, Ft; \ mVUallocFMAC18a(ACC, Fs, Ft); \ SSE_##operation##PS_XMM_to_XMM(Fs, Ft); \ - mVUupdateFlags(Fs, xmmT1, Ft, _X_Y_Z_W, 0); \ + mVUupdateFlags(Fs, xmmT1, xmmT2, _X_Y_Z_W, 0); \ mVUallocFMAC18b(ACC, Fs); \ } \ } @@ -348,7 +348,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX mVUallocFMAC19a(Fd, ACC, Fs, Ft); \ SSE_MULPS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##PS_XMM_to_XMM(ACC, Fs); \ - mVUupdateFlags(Fd, Fs, Ft, _X_Y_Z_W, 0); \ + mVUupdateFlags(Fd, Fs, xmmT2, _X_Y_Z_W, 0); \ mVUallocFMAC19b(Fd); \ } \ } @@ -361,7 +361,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX mVUallocFMAC22a(Fd, Fs, Ft); \ if (_XYZW_SS) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \ else SSE_##operation##PS_XMM_to_XMM(Fs, Ft); \ - mVUupdateFlags(Fd, xmmT1, Ft, _X_Y_Z_W, 1); \ + mVUupdateFlags(Fd, xmmT1, xmmT2, _X_Y_Z_W, 1); \ mVUallocFMAC22b(Fd); \ } \ } @@ -374,7 +374,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX mVUallocFMAC23a(ACC, Fs, Ft); \ if (_X_Y_Z_W == 8) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \ else SSE_##operation##PS_XMM_to_XMM(Fs, Ft); \ - mVUupdateFlags(Fs, xmmT1, Ft, _X_Y_Z_W, 0); \ + mVUupdateFlags(Fs, xmmT1, xmmT2, _X_Y_Z_W, 0); \ mVUallocFMAC23b(ACC, Fs); \ } \ } @@ -393,7 +393,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX SSE_MULPS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##PS_XMM_to_XMM(Fs, ACC); \ } \ - mVUupdateFlags(Fd, xmmT1, Ft, _X_Y_Z_W, 0); \ + mVUupdateFlags(Fd, xmmT1, xmmT2, _X_Y_Z_W, 0); \ mVUallocFMAC24b(Fd); \ } \ } @@ -412,7 +412,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX SSE_MULPS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##PS_XMM_to_XMM(ACC, Fs); \ } \ - mVUupdateFlags(Fd, Fs, Ft, _X_Y_Z_W, 0); \ + mVUupdateFlags(Fd, Fs, xmmT2, _X_Y_Z_W, 0); \ mVUallocFMAC25b(Fd); \ } \ } @@ -431,7 +431,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX SSE_MULPS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##PS_XMM_to_XMM(ACCr, Fs); \ } \ - mVUupdateFlags(ACCr, Fs, Ft, _X_Y_Z_W, 0); \ + mVUupdateFlags(ACCr, Fs, xmmT2, _X_Y_Z_W, 0); \ mVUallocFMAC26b(ACCw, ACCr); \ } \ }