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x86: Warning fixes for clang-cl

This commit is contained in:
Stenzek 2022-12-25 15:58:55 +10:00 committed by refractionpcsx2
parent f407bc12df
commit a1ffe4deff
8 changed files with 20 additions and 81 deletions
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8
pcsx2/x86/iCore.cpp
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@ -291,13 +291,10 @@ int _allocFPtoXMMreg(int fpreg, int mode)
return xmmreg; return xmmreg;
} }
static const char* GetModeString(int mode)
{
return ((mode & MODE_READ)) ? ((mode & MODE_WRITE) ? "readwrite" : "read") : "write";
}
int _allocGPRtoXMMreg(int gprreg, int mode) int _allocGPRtoXMMreg(int gprreg, int mode)
{ {
#define MODE_STRING(x) ((((x) & MODE_READ)) ? (((x)&MODE_WRITE) ? "readwrite" : "read") : "write")
// is this already in a gpr? // is this already in a gpr?
const int hostx86reg = _checkX86reg(X86TYPE_GPR, gprreg, MODE_READ); const int hostx86reg = _checkX86reg(X86TYPE_GPR, gprreg, MODE_READ);
@ -409,6 +406,7 @@ int _allocGPRtoXMMreg(int gprreg, int mode)
} }
return xmmreg; return xmmreg;
#undef MODE_STRING
} }
// Same code as _allocFPtoXMMreg but for the FPU ACC register // Same code as _allocFPtoXMMreg but for the FPU ACC register

29
pcsx2/x86/iR3000A.cpp
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@ -1611,33 +1611,10 @@ void psxRecompileNextInstruction(bool delayslot, bool swapped_delayslot)
#endif #endif
} }
#ifdef TRACE_BLOCKS
static void PreBlockCheck(u32 blockpc) static void PreBlockCheck(u32 blockpc)
{ {
#if 0 #if 0
extern void iDumpPsxRegisters(u32 startpc, u32 temp);
static u32 lastrec = 0;
//*(int*)PSXM(0x27990) = 1; // enables cdvd bios output for scph10000
if ((psxdump & 2) && lastrec != blockpc)
{
static int curcount = 0;
constexpr int skip = 0;
curcount++;
if (curcount > skip)
{
iDumpPsxRegisters(blockpc, 1);
curcount = 0;
}
lastrec = blockpc;
}
#endif
#ifdef TRACE_BLOCKS
#if 1
static FILE* fp = nullptr; static FILE* fp = nullptr;
static bool fp_opened = false; static bool fp_opened = false;
if (!fp_opened && psxRegs.cycle >= 0) if (!fp_opened && psxRegs.cycle >= 0)
@ -1666,8 +1643,8 @@ static void PreBlockCheck(u32 blockpc)
if (psxRegs.cycle == 0) if (psxRegs.cycle == 0)
__debugbreak(); __debugbreak();
#endif #endif
#endif
} }
#endif
static void iopRecRecompile(const u32 startpc) static void iopRecRecompile(const u32 startpc)
{ {
@ -1775,7 +1752,7 @@ static void iopRecRecompile(const u32 startpc)
case 2: // J case 2: // J
case 3: // JAL case 3: // JAL
s_branchTo = _InstrucTarget_ << 2 | (i + 4) & 0xf0000000; s_branchTo = (_InstrucTarget_ << 2) | ((i + 4) & 0xf0000000);
s_nEndBlock = i + 8; s_nEndBlock = i + 8;
goto StartRecomp; goto StartRecomp;

7
pcsx2/x86/ix86-32/iCore-32.cpp
View File

@ -176,14 +176,10 @@ void _flushConstRegs()
} }
} }
static const char* GetModeString(int mode)
{
return ((mode & MODE_READ)) ? ((mode & MODE_WRITE) ? "readwrite" : "read") : "write";
}
void _validateRegs() void _validateRegs()
{ {
#ifdef PCSX2_DEVBUILD #ifdef PCSX2_DEVBUILD
#define MODE_STRING(x) ((((x) & MODE_READ)) ? (((x)&MODE_WRITE) ? "readwrite" : "read") : "write")
// check that no two registers are in write mode in both fprs and gprs // check that no two registers are in write mode in both fprs and gprs
for (s8 guestreg = 0; guestreg < 32; guestreg++) for (s8 guestreg = 0; guestreg < 32; guestreg++)
{ {
@ -216,6 +212,7 @@ void _validateRegs()
if (fprmode & MODE_WRITE) if (fprmode & MODE_WRITE)
pxAssertMsg(gprmode == 0, "when writing to the fpr, gpr is invalid"); pxAssertMsg(gprmode == 0, "when writing to the fpr, gpr is invalid");
} }
#undef MODE_STRING
#endif #endif
} }

35
pcsx2/x86/ix86-32/iR5900-32.cpp
View File

@ -80,7 +80,7 @@ bool s_nBlockInterlocked = false; // Block is VU0 interlocked
u32 pc; // recompiler pc u32 pc; // recompiler pc
int g_branch; // set for branch int g_branch; // set for branch
alignas(16) GPR_reg64 g_cpuConstRegs[32] = {0}; alignas(16) GPR_reg64 g_cpuConstRegs[32] = {};
u32 g_cpuHasConstReg = 0, g_cpuFlushedConstReg = 0; u32 g_cpuHasConstReg = 0, g_cpuFlushedConstReg = 0;
bool g_cpuFlushedPC, g_cpuFlushedCode, g_recompilingDelaySlot, g_maySignalException; bool g_cpuFlushedPC, g_cpuFlushedCode, g_recompilingDelaySlot, g_maySignalException;
@ -809,7 +809,7 @@ void recClear(u32 addr, u32 size)
int toRemoveLast = blockidx; int toRemoveLast = blockidx;
while (pexblock = recBlocks[blockidx]) while ((pexblock = recBlocks[blockidx]))
{ {
u32 blockstart = pexblock->startpc; u32 blockstart = pexblock->startpc;
u32 blockend = pexblock->startpc + pexblock->size * 4; u32 blockend = pexblock->startpc + pexblock->size * 4;
@ -847,12 +847,12 @@ void recClear(u32 addr, u32 size)
upperextent = std::min(upperextent, ceiling); upperextent = std::min(upperextent, ceiling);
for (int i = 0; pexblock = recBlocks[i]; i++) for (int i = 0; (pexblock = recBlocks[i]); i++)
{ {
if (s_pCurBlock == PC_GETBLOCK(pexblock->startpc)) if (s_pCurBlock == PC_GETBLOCK(pexblock->startpc))
continue; continue;
u32 blockend = pexblock->startpc + pexblock->size * 4; u32 blockend = pexblock->startpc + pexblock->size * 4;
if (pexblock->startpc >= addr && pexblock->startpc < addr + size * 4 || pexblock->startpc < addr && blockend > addr) if ((pexblock->startpc >= addr && pexblock->startpc < addr + size * 4) || (pexblock->startpc < addr && blockend > addr))
{ {
if (!IsDevBuild) if (!IsDevBuild)
Console.Error("[EE] Impossible block clearing failure"); Console.Error("[EE] Impossible block clearing failure");
@ -1957,7 +1957,7 @@ void recompileNextInstruction(bool delayslot, bool swapped_delay_slot)
cpuRegs.code = memRead32(p); cpuRegs.code = memRead32(p);
if (_Opcode_ == 022 && _Rs_ == 2) // CFC2 if (_Opcode_ == 022 && _Rs_ == 2) // CFC2
// rd is fs // rd is fs
if (_Rd_ == 16 && s & 1 || _Rd_ == 17 && s & 2 || _Rd_ == 18 && s & 4) if ((_Rd_ == 16 && s & 1) || (_Rd_ == 17 && s & 2) || (_Rd_ == 18 && s & 4))
{ {
std::string disasm; std::string disasm;
Console.Warning("Possible old value used in COP2 code. If the game is broken, please report to http://github.com/pcsx2/pcsx2."); Console.Warning("Possible old value used in COP2 code. If the game is broken, please report to http://github.com/pcsx2/pcsx2.");
@ -1994,24 +1994,9 @@ void recompileNextInstruction(bool delayslot, bool swapped_delay_slot)
// (Called from recompiled code)] // (Called from recompiled code)]
// This function is called from the recompiler prior to starting execution of *every* recompiled block. // This function is called from the recompiler prior to starting execution of *every* recompiled block.
// Calling of this function can be enabled or disabled through the use of EmuConfig.Recompiler.PreBlockChecks // Calling of this function can be enabled or disabled through the use of EmuConfig.Recompiler.PreBlockChecks
#ifdef TRACE_BLOCKS
static void PreBlockCheck(u32 blockpc) static void PreBlockCheck(u32 blockpc)
{ {
/*static int lastrec = 0;
static int curcount = 0;
const int skip = 0;
if( blockpc != 0x81fc0 ) {//&& lastrec != g_lastpc ) {
curcount++;
if( curcount > skip ) {
iDumpRegisters(blockpc, 1);
curcount = 0;
}
lastrec = blockpc;
}*/
#ifdef TRACE_BLOCKS
#if 0 #if 0
static FILE* fp = nullptr; static FILE* fp = nullptr;
static bool fp_opened = false; static bool fp_opened = false;
@ -2060,8 +2045,8 @@ static void PreBlockCheck(u32 blockpc)
if (cpuRegs.cycle == 0) if (cpuRegs.cycle == 0)
pauseAAA(); pauseAAA();
#endif #endif
#endif
} }
#endif
#ifdef PCSX2_DEBUG #ifdef PCSX2_DEBUG
// Array of cpuRegs.pc block addresses to dump. USeful for selectively dumping potential // Array of cpuRegs.pc block addresses to dump. USeful for selectively dumping potential
@ -2383,7 +2368,7 @@ static void recRecompile(const u32 startpc)
case 2: // J case 2: // J
case 3: // JAL case 3: // JAL
s_branchTo = _InstrucTarget_ << 2 | (i + 4) & 0xf0000000; s_branchTo = (_InstrucTarget_ << 2) | ((i + 4) & 0xf0000000);
s_nEndBlock = i + 8; s_nEndBlock = i + 8;
goto StartRecomp; goto StartRecomp;
@ -2463,7 +2448,7 @@ StartRecomp:
if (cpuRegs.code == 0) if (cpuRegs.code == 0)
continue; continue;
// cache, sync // cache, sync
else if (_Opcode_ == 057 || _Opcode_ == 0 && _Funct_ == 017) else if (_Opcode_ == 057 || (_Opcode_ == 0 && _Funct_ == 017))
continue; continue;
// imm arithmetic // imm arithmetic
else if ((_Opcode_ & 070) == 010 || (_Opcode_ & 076) == 030) else if ((_Opcode_ & 070) == 010 || (_Opcode_ & 076) == 030)
@ -2655,7 +2640,7 @@ StartRecomp:
int i; int i;
i = recBlocks.LastIndex(HWADDR(pc) - 4); i = recBlocks.LastIndex(HWADDR(pc) - 4);
while (oldBlock = recBlocks[i--]) while ((oldBlock = recBlocks[i--]))
{ {
if (oldBlock == s_pCurBlockEx) if (oldBlock == s_pCurBlockEx)
continue; continue;

6
pcsx2/x86/ix86-32/iR5900Move.cpp
View File

@ -49,12 +49,6 @@ REC_FUNC_DEL(MOVN, _Rd_);
#else #else
static void xCopy64(u64* dst, u64* src)
{
xMOV(rax, ptr64[src]);
xMOV(ptr64[dst], rax);
}
/********************************************************* /*********************************************************
* Load higher 16 bits of the first word in GPR with imm * * Load higher 16 bits of the first word in GPR with imm *
* Format: OP rt, immediate * * Format: OP rt, immediate *

12
pcsx2/x86/ix86-32/recVTLB.cpp
View File

@ -391,18 +391,6 @@ void vtlb_dynarec_init()
Perf::any.map((uptr)m_IndirectDispatchers, __pagesize, "TLB Dispatcher"); Perf::any.map((uptr)m_IndirectDispatchers, __pagesize, "TLB Dispatcher");
} }
static void vtlb_SetWriteback(u32* writeback)
{
uptr val = (uptr)xGetPtr();
if (wordsize == 8)
{
pxAssertMsg(*((u8*)writeback - 2) == 0x8d, "Expected codegen to be an LEA");
val -= ((uptr)writeback + 4);
}
pxAssertMsg((sptr)val == (s32)val, "Writeback too far away!");
*writeback = val;
}
////////////////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////////////////
// Dynarec Load Implementations // Dynarec Load Implementations
// ------------------------------------------------------------------------ // ------------------------------------------------------------------------

2
pcsx2/x86/microVU_IR.h
View File

@ -324,7 +324,7 @@ public:
if (pxmmregs[i].reg >= 0) if (pxmmregs[i].reg >= 0)
{ {
MVURALOG("Preserving VF reg %d in host reg %d across instruction\n", pxmmregs[i].reg, i); MVURALOG("Preserving VF reg %d in host reg %d across instruction\n", pxmmregs[i].reg, i);
pxAssert(pxmmregs[i].reg != 255); pxAssert(pxmmregs[i].reg >= 0);
pxmmregs[i].needed = false; pxmmregs[i].needed = false;
xmmMap[i].isNeeded = false; xmmMap[i].isNeeded = false;
xmmMap[i].VFreg = pxmmregs[i].reg; xmmMap[i].VFreg = pxmmregs[i].reg;

2
pcsx2/x86/newVif_Unpack.cpp
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@ -32,7 +32,7 @@ alignas(16) nVifCall nVifUpk[(2 * 2 * 16) * 4];
// This is used by the interpreted SSE unpacks only. Recompiled SSE unpacks // This is used by the interpreted SSE unpacks only. Recompiled SSE unpacks
// and the interpreted C unpacks use the vif.MaskRow/MaskCol members directly. // and the interpreted C unpacks use the vif.MaskRow/MaskCol members directly.
// [MaskNumber][CycleNumber][Vector] // [MaskNumber][CycleNumber][Vector]
alignas(16) u32 nVifMask[3][4][4] = {0}; alignas(16) u32 nVifMask[3][4][4] = {};
// Number of bytes of data in the source stream needed for each vector. // Number of bytes of data in the source stream needed for each vector.
// [equivalent to ((32 >> VL) * (VN+1)) / 8] // [equivalent to ((32 >> VL) * (VN+1)) / 8]