From a10b0c5dc5fc717794979fa7cc32183805432a2e Mon Sep 17 00:00:00 2001 From: refractionpcsx2 Date: Wed, 28 Dec 2022 17:23:56 +0000 Subject: [PATCH] VIF: Make sure VU's are updated when waiting --- pcsx2/Vif0_Dma.cpp | 4 ++++ pcsx2/Vif1_Dma.cpp | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/pcsx2/Vif0_Dma.cpp b/pcsx2/Vif0_Dma.cpp index 121900e352..61187283f4 100644 --- a/pcsx2/Vif0_Dma.cpp +++ b/pcsx2/Vif0_Dma.cpp @@ -136,6 +136,10 @@ __fi void vif0SetupTransfer() __fi void vif0VUFinish() { + // Sync up VU0 so we don't errantly wait. + while ((static_cast(cpuRegs.cycle) - static_cast(VU0.cycle)) > 0 && (VU0.VI[REG_VPU_STAT].UL & 0x1)) + CpuVU0->ExecuteBlock(); + if (VU0.VI[REG_VPU_STAT].UL & 0x5) { CPU_INT(VIF_VU0_FINISH, 128); diff --git a/pcsx2/Vif1_Dma.cpp b/pcsx2/Vif1_Dma.cpp index b76b91e4d4..f7c2761eb4 100644 --- a/pcsx2/Vif1_Dma.cpp +++ b/pcsx2/Vif1_Dma.cpp @@ -229,6 +229,10 @@ __fi void vif1SetupTransfer() __fi void vif1VUFinish() { + // Sync up VU1 so we don't errantly wait. + while (!THREAD_VU1 && (static_cast(cpuRegs.cycle) - static_cast(VU1.cycle)) > 0 && (VU0.VI[REG_VPU_STAT].UL & 0x100)) + CpuVU1->ExecuteBlock(); + if (VU0.VI[REG_VPU_STAT].UL & 0x500) { vu1Thread.Get_MTVUChanges();