mirror of https://github.com/PCSX2/pcsx2.git
Update analyst to use new flags
This commit is contained in:
Kingcom
parent
72c2158b17
commit
9fde236512
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@ -20,6 +20,7 @@
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#include "SymbolMap.h"
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#include "DebugInterface.h"
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#include "../R5900.h"
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#include "../R5900OpcodeTables.h"
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static std::vector<MIPSAnalyst::AnalyzedFunction> functions;
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@ -160,296 +161,182 @@ namespace MIPSAnalyst
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}
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}
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enum BranchType { NONE, JUMP, BRANCH };
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struct BranchInfo
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{
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BranchType type;
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bool link;
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bool likely;
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bool toRegister;
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};
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bool getBranchInfo(MipsOpcodeInfo& info)
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{
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BranchType type = NONE;
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bool link = false;
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bool likely = false;
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bool toRegister = false;
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bool met = false;
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u32 op = info.encodedOpcode;
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u32 opNum = MIPS_GET_OP(op);
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u32 rsNum = MIPS_GET_RS(op);
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u32 rtNum = MIPS_GET_RT(op);
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u32 rs = info.cpu->getRegister(0,rsNum);
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u32 rt = info.cpu->getRegister(0,rtNum);
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switch (MIPS_GET_OP(op))
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{
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case 0x00: // special
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switch (MIPS_GET_FUNC(op))
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{
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case 0x08: // jr
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type = JUMP;
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toRegister = true;
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break;
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case 0x09: // jalr
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type = JUMP;
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toRegister = true;
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link = true;
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break;
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}
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break;
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case 0x01: // regimm
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switch (MIPS_GET_RT(op))
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{
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case 0x00: // bltz
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case 0x02: // bltzl
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case 0x10: // bltzal
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case 0x12: // bltzall
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type = BRANCH;
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met = (((s32)rs) < 0);
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likely = (rt & 2) != 0;
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link = rt >= 0x10;
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break;
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case 0x01: // bgez
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case 0x03: // bgezl
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case 0x11: // bgezal
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case 0x13: // bgezall
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type = BRANCH;
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met = (((s32)rs) >= 0);
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likely = (rt & 2) != 0;
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link = rt >= 0x10;
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break;
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}
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break;
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case 0x02: // j
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type = JUMP;
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break;
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case 0x03: // jal
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type = JUMP;
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link = true;
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break;
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case 0x04: // beq
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case 0x14: // beql
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type = BRANCH;
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met = (rt == rs);
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if (MIPS_GET_RT(op) == MIPS_GET_RS(op)) // always true
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info.isConditional = false;
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likely = opNum >= 0x10;
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break;
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case 0x05: // bne
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case 0x15: // bnel
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type = BRANCH;
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met = (rt != rs);
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if (MIPS_GET_RT(op) == MIPS_GET_RS(op)) // always false
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info.isConditional = false;
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likely = opNum >= 0x10;
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break;
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case 0x06: // blez
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case 0x16: // blezl
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type = BRANCH;
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met = (((s32)rs) <= 0);
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likely = opNum >= 0x10;
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break;
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case 0x07: // bgtz
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case 0x17: // bgtzl
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type = BRANCH;
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met = (((s32)rs) > 0);
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likely = opNum >= 0x10;
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break;
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}
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if (type == NONE)
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return false;
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info.isBranch = true;
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info.isLinkedBranch = link;
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info.isLikelyBranch = true;
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info.isBranchToRegister = toRegister;
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info.isConditional = type == BRANCH;
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info.conditionMet = met;
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switch (type)
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{
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case JUMP:
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if (toRegister)
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{
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info.branchRegisterNum = (int)MIPS_GET_RS(op);
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info.branchTarget = info.cpu->getRegister(0,info.branchRegisterNum)._u32[0];
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} else {
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info.branchTarget = (info.opcodeAddress & 0xF0000000) | ((op&0x03FFFFFF) << 2);
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}
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break;
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case BRANCH:
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info.branchTarget = info.opcodeAddress + 4 + ((signed short)(op&0xFFFF)<<2);
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break;
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case NONE:
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return false;
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}
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return true;
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}
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bool getDataAccessInfo(MipsOpcodeInfo& info)
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{
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int size = 0;
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u32 op = info.encodedOpcode;
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int off = 0;
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switch (MIPS_GET_OP(op))
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{
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case 0x20: // lb
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case 0x24: // lbu
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case 0x28: // sb
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size = 1;
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break;
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case 0x21: // lh
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case 0x25: // lhu
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case 0x29: // sh
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size = 2;
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break;
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case 0x23: // lw
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case 0x2B: // sw
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size = 4;
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break;
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case 0x26: // lwr
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case 0x2E: // swr
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size = 4;
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info.lrType = LOADSTORE_RIGHT;
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break;
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case 0x22: // lwl
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case 0x2A: // swl
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size = 4;
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off = -3;
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info.lrType = LOADSTORE_LEFT;
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break;
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case 0x37: // ld
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case 0x3F: // sd
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size = 8;
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break;
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case 0x1B: // ldr
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case 0x2D: // sdr
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size = 8;
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info.lrType = LOADSTORE_RIGHT;
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break;
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case 0x1A: // ldl
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case 0x2C: // sdl
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size = 8;
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off = -7;
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info.lrType = LOADSTORE_LEFT;
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break;
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case 0x1E: // lq
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case 0x1F: // sq
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size = 16;
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break;
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}
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if (size == 0)
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return false;
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info.isDataAccess = true;
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info.dataSize = size;
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u32 rs = info.cpu->getRegister(0, (int)MIPS_GET_RS(op));
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s16 imm16 = op & 0xFFFF;
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info.dataAddress = rs + imm16 + off;
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info.hasRelevantAddress = true;
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info.releventAddress = info.dataAddress;
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return true;
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}
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MipsOpcodeInfo GetOpcodeInfo(DebugInterface* cpu, u32 address) {
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MipsOpcodeInfo info;
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memset(&info, 0, sizeof(info));
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if (cpu->isValidAddress(address) == false) {
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if (cpu->isValidAddress(address) == false)
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return info;
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}
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info.cpu = cpu;
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info.opcodeAddress = address;
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info.encodedOpcode = cpu->read32(address);
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u32 op = info.encodedOpcode;
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const R5900::OPCODE& opcode = R5900::GetInstruction(op);
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if (getBranchInfo(info) == true)
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return info;
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// extract all the branch related information
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info.isBranch = (opcode.flags & IS_BRANCH) != 0;
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if (info.isBranch)
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{
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info.isLinkedBranch = (opcode.flags & IS_LINKED) != 0;
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info.isLikelyBranch = (opcode.flags & IS_LIKELY) != 0;
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if (getDataAccessInfo(info) == true)
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return info;
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// gather relevant address for alu operations
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// that's usually the value of the dest register
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switch (MIPS_GET_OP(op)) {
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case 0: // special
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switch (MIPS_GET_FUNC(op)) {
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case 0x0C: // syscall
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u64 rs,rt;
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u32 value;
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switch (opcode.flags & BRANCHTYPE_MASK)
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{
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case BRANCHTYPE_JUMP:
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info.isConditional = false;
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info.branchTarget = (info.opcodeAddress & 0xF0000000) | ((op&0x03FFFFFF) << 2);
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break;
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case BRANCHTYPE_BRANCH:
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info.isConditional = true;
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info.branchTarget = info.opcodeAddress + 4 + ((s16)(op&0xFFFF)<<2);
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rs = info.cpu->getRegister(0,MIPS_GET_RS(op))._u64[0];
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rt = info.cpu->getRegister(0,MIPS_GET_RT(op))._u64[0];
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switch (opcode.flags & CONDTYPE_MASK)
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{
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case CONDTYPE_EQ:
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info.conditionMet = (rt == rs);
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if (MIPS_GET_RT(op) == MIPS_GET_RS(op)) // always true
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info.isConditional = false;
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break;
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case CONDTYPE_NE:
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info.conditionMet = (rt != rs);
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if (MIPS_GET_RT(op) == MIPS_GET_RS(op)) // always false
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info.isConditional = false;
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break;
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case CONDTYPE_LEZ:
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info.conditionMet = (((s64)rs) <= 0);
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break;
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case CONDTYPE_GTZ:
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info.conditionMet = (((s64)rs) > 0);
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break;
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case CONDTYPE_LTZ:
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info.conditionMet = (((s64)rs) < 0);
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break;
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case CONDTYPE_GEZ:
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info.conditionMet = (((s64)rs) >= 0);
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break;
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}
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break;
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case BRANCHTYPE_REGISTER:
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info.isConditional = false;
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info.isBranchToRegister = true;
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info.branchRegisterNum = (int)MIPS_GET_RS(op);
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info.branchTarget = info.cpu->getRegister(0,info.branchRegisterNum)._u32[0];
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break;
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case BRANCHTYPE_SYSCALL:
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info.isConditional = false;
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info.isSyscall = true;
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info.branchTarget = 0x80000000+0x180;
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break;
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case 0x20: // add
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case 0x21: // addu
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info.hasRelevantAddress = true;
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info.releventAddress = cpu->getRegister(0,MIPS_GET_RS(op))._u32[0]+cpu->getRegister(0,MIPS_GET_RT(op))._u32[0];
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break;
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case 0x22: // sub
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case 0x23: // subu
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info.hasRelevantAddress = true;
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info.releventAddress = cpu->getRegister(0,MIPS_GET_RS(op))._u32[0]-cpu->getRegister(0,MIPS_GET_RT(op))._u32[0];
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break;
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}
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break;
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case 0x08: // addi
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case 0x09: // adiu
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info.hasRelevantAddress = true;
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info.releventAddress = cpu->getRegister(0,MIPS_GET_RS(op))._u32[0]+((s16)(op & 0xFFFF));
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break;
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case 0x10: // cop0
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switch (MIPS_GET_RS(op))
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{
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case 0x10: // tlb
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switch (MIPS_GET_FUNC(op))
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case BRANCHTYPE_ERET:
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info.isConditional = false;
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// probably shouldn't be hard coded like this...
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if (cpuRegs.CP0.n.Status.b.ERL)
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{
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case 0x18: // eret
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info.isBranch = true;
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info.isConditional = false;
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info.branchTarget = cpuRegs.CP0.n.ErrorEPC;
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} else {
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info.branchTarget = cpuRegs.CP0.n.EPC;
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}
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break;
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case BRANCHTYPE_BC1:
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info.isConditional = true;
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value = info.cpu->getRegister(EECAT_FCR,31)._u32[0] & 0x00800000;
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info.branchTarget = info.opcodeAddress + 4 + ((s16)(op&0xFFFF)<<2);
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// probably shouldn't be hard coded like this...
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if (cpuRegs.CP0.n.Status.b.ERL) {
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info.branchTarget = cpuRegs.CP0.n.ErrorEPC;
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} else {
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info.branchTarget = cpuRegs.CP0.n.EPC;
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}
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switch (opcode.flags & CONDTYPE_MASK)
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{
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case CONDTYPE_EQ:
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info.conditionMet = value == 0;
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break;
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case CONDTYPE_NE:
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info.conditionMet = value != 0;
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break;
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}
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break;
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}
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break;
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}
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// TODO: rest
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/* // movn, movz
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if (opInfo & IS_CONDMOVE) {
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info.isConditional = true;
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// extract the accessed memory address
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info.isDataAccess = opcode.flags & IS_MEMORY;
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if (info.isDataAccess)
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{
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if (opcode.flags & IS_LEFT)
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info.lrType = LOADSTORE_LEFT;
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else if (opcode.flags & IS_RIGHT)
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info.lrType = LOADSTORE_RIGHT;
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u32 rs = info.cpu->getRegister(0, (int)MIPS_GET_RS(op));
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s16 imm16 = op & 0xFFFF;
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info.dataAddress = rs + imm16;
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u32 rt = cpu->GetRegValue(0, (int)MIPS_GET_RT(op));
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switch (opInfo & CONDTYPE_MASK) {
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case CONDTYPE_EQ:
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info.conditionMet = (rt == 0);
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switch (opcode.flags & MEMTYPE_MASK)
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{
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case MEMTYPE_BYTE:
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info.dataSize = 1;
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break;
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case CONDTYPE_NE:
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info.conditionMet = (rt != 0);
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case MEMTYPE_HALF:
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info.dataSize = 2;
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break;
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case MEMTYPE_WORD:
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info.dataSize = 4;
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if (info.lrType == LOADSTORE_LEFT)
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info.dataAddress -= 3;
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break;
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case MEMTYPE_DWORD:
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info.dataSize = 8;
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if (info.lrType == LOADSTORE_LEFT)
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info.dataAddress -= 7;
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break;
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case MEMTYPE_QWORD:
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info.dataSize = 16;
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break;
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}
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}*/
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info.hasRelevantAddress = true;
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info.releventAddress = info.dataAddress;
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}
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// gather relevant address for alu operations
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if (opcode.flags & IS_ALU)
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{
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u64 rs,rt;
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rs = info.cpu->getRegister(0,MIPS_GET_RS(op))._u64[0];
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rt = info.cpu->getRegister(0,MIPS_GET_RT(op))._u64[0];
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switch (opcode.flags & ALUTYPE_MASK)
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{
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case ALUTYPE_ADDI:
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info.hasRelevantAddress = true;
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info.releventAddress = rs+((s16)(op & 0xFFFF));
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break;
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case ALUTYPE_ADD:
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info.hasRelevantAddress = true;
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info.releventAddress = rs+rt;
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break;
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case ALUTYPE_SUB:
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info.hasRelevantAddress = true;
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info.releventAddress = rs-rt;
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break;
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case ALUTYPE_CONDMOVE:
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info.isConditional = true;
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switch (opcode.flags & CONDTYPE_MASK)
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{
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case CONDTYPE_EQ:
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info.conditionMet = (rt == 0);
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break;
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case CONDTYPE_NE:
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info.conditionMet = (rt != 0);
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break;
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}
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break;
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}
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}
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return info;
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}
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