microVU: fixed a few problems...

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1172 96395faa-99c1-11dd-bbfe-3dabce05a288

pcsx2/x86/microVU_Analyze.inl

@@ -28,7 +28,7 @@
 //------------------------------------------------------------------
 
 #define aReg(x) mVUregs.VF[x]
-#define bReg(x) mVUregsTemp.VFreg[0] = x; mVUregsTemp.VF[0]
+#define bReg(x, y) mVUregsTemp.VFreg[y] = x; mVUregsTemp.VF[0]
 #define aMax(x, y) ((x > y) ? x : y)
 
 #define analyzeReg1(reg) {									\
@@ -40,12 +40,12 @@
 	}														\
 }
 
-#define analyzeReg2(reg) {				\
+#define analyzeReg2(reg, isLowOp) {				\
 	if (reg) {									\
-		if (_X) { bReg(reg).x = 4; }	\
-		if (_Y) { bReg(reg).y = 4; }	\
-		if (_Z) { bReg(reg).z = 4; }	\
-		if (_W) { bReg(reg).w = 4; }	\
+		if (_X) { bReg(reg, isLowOp).x = 4; }	\
+		if (_Y) { bReg(reg, isLowOp).y = 4; }	\
+		if (_Z) { bReg(reg, isLowOp).z = 4; }	\
+		if (_W) { bReg(reg, isLowOp).w = 4; }	\
 	}											\
 }
 
@@ -54,7 +54,7 @@ microVUt(void) mVUanalyzeFMAC1(int Fd, int Fs, int Ft) {
 	mVUinfo |= _doStatus;
 	analyzeReg1(Fs);
 	analyzeReg1(Ft);
-	analyzeReg2(Fd);
+	analyzeReg2(Fd, 0);
 }
 
 //------------------------------------------------------------------
@@ -64,7 +64,7 @@ microVUt(void) mVUanalyzeFMAC1(int Fd, int Fs, int Ft) {
 microVUt(void) mVUanalyzeFMAC2(int Fs, int Ft) {
 	microVU* mVU = mVUx;
 	analyzeReg1(Fs);
-	analyzeReg2(Ft);
+	analyzeReg2(Ft, 0);
 }
 
 //------------------------------------------------------------------
@@ -85,7 +85,7 @@ microVUt(void) mVUanalyzeFMAC3(int Fd, int Fs, int Ft) {
 	mVUinfo |= _doStatus;
 	analyzeReg1(Fs);
 	analyzeReg3(Ft);
-	analyzeReg2(Fd);
+	analyzeReg2(Fd, 0);
 }
 
 //------------------------------------------------------------------
@@ -143,7 +143,7 @@ microVUt(void) mVUanalyzeMR32(int Fs, int Ft) {
 	microVU* mVU = mVUx;
 	if (!Ft) { mVUinfo |= _isNOP; }
 	analyzeReg6(Fs);
-	analyzeReg2(Ft);
+	analyzeReg2(Ft, 1);
 }
 
 //------------------------------------------------------------------
@@ -197,9 +197,22 @@ microVUt(void) mVUanalyzeEFU2(int Fs, u8 xCycles) {
 microVUt(void) mVUanalyzeMFP(int Ft) {
 	microVU* mVU = mVUx;
 	if (!Ft) { mVUinfo |= _isNOP; }
-	analyzeReg2(Ft);
+	analyzeReg2(Ft, 1);
 }
 
+//------------------------------------------------------------------
+// MOVE - MOVE Opcode
+//------------------------------------------------------------------
+
+microVUt(void) mVUanalyzeMOVE(int Fs, int Ft) {
+	microVU* mVU = mVUx;
+	if (!Ft || (Ft == Fs)) { mVUinfo |= _isNOP; }
+	if (mVUregsTemp.VFreg[0] == Fs) { mVUinfo |= _swapOps; } 
+	analyzeReg1(Fs);
+	analyzeReg2(Ft, 1);
+}
+
+
 //------------------------------------------------------------------
 // LQx - LQ/LQD/LQI Opcodes
 //------------------------------------------------------------------
@@ -207,7 +220,7 @@ microVUt(void) mVUanalyzeMFP(int Ft) {
 microVUt(void) mVUanalyzeLQ(int Ft, int Is, bool writeIs) {
 	microVU* mVU = mVUx;
 	analyzeVIreg1(Is);
-	analyzeReg2(Ft);
+	analyzeReg2(Ft, 1);
 	if (!Ft)	 { mVUinfo |= (writeIs && Is) ? _noWriteVF : _isNOP; }
 	if (writeIs) { analyzeVIreg2(Is, 1); }
 }
@@ -238,7 +251,7 @@ microVUt(void) mVUanalyzeR1(int Fs, int Fsf) {
 microVUt(void) mVUanalyzeR2(int Ft, bool canBeNOP) {
 	microVU* mVU = mVUx;
 	if (!Ft) { mVUinfo |= ((canBeNOP) ? _isNOP : _noWriteVF); }
-	analyzeReg2(Ft);
+	analyzeReg2(Ft, 1);
 	analyzeRreg();
 }
 

pcsx2/x86/microVU_Execute.inl

@@ -27,7 +27,6 @@ void testFunction() { mVUprint("microVU: Entered Execution Mode"); }
 
 // Generates the code for entering recompiled blocks
 microVUt(void) mVUdispatcherA() {
-	static u32 PCSX2_ALIGNED16(vuMXCSR);
 	microVU* mVU = mVUx;
 	mVU->startFunct = x86Ptr;
 
@@ -42,8 +41,7 @@ microVUt(void) mVUdispatcherA() {
 	PUSH32R(EDI);
 
 	// Load VU's MXCSR state
-	vuMXCSR = g_sseVUMXCSR;
-	SSE_LDMXCSR((uptr)&vuMXCSR);
+	SSE_LDMXCSR((uptr)&g_sseVUMXCSR);
 
 	// Load Regs
 	MOV32MtoR(gprR,  (uptr)&mVU->regs->VI[REG_R].UL);
@@ -83,13 +81,11 @@ microVUt(void) mVUdispatcherA() {
 
 // Generates the code to exit from recompiled blocks
 microVUt(void) mVUdispatcherB() {
-	static u32 PCSX2_ALIGNED16(eeMXCSR);
 	microVU* mVU = mVUx;
 	mVU->exitFunct = x86Ptr;
 
 	// Load EE's MXCSR state
-	eeMXCSR = g_sseMXCSR;
-	SSE_LDMXCSR((uptr)&eeMXCSR);
+	SSE_LDMXCSR((uptr)&g_sseMXCSR);
 	
 	// Save Regs (Other Regs Saved in mVUcompile)
 	MOV32RtoM((uptr)&mVU->regs->VI[REG_R].UL, gprR);

pcsx2/x86/microVU_Lower.inl

@@ -699,7 +699,7 @@ microVUf(void) mVU_ISUBIU() {
 
 microVUf(void) mVU_MFIR() {
 	microVU* mVU = mVUx;
-	pass1 { if (!_Ft_) { mVUinfo |= _isNOP; } analyzeVIreg1(_Is_); analyzeReg2(_Ft_); }
+	pass1 { if (!_Ft_) { mVUinfo |= _isNOP; } analyzeVIreg1(_Is_); analyzeReg2(_Ft_, 1); }
 	pass2 { 
 		mVUallocVIa<vuIndex>(gprT1, _Is_);
 		MOVSX32R16toR(gprT1, gprT1);
@@ -722,7 +722,7 @@ microVUf(void) mVU_MFP() {
 
 microVUf(void) mVU_MOVE() {
 	microVU* mVU = mVUx;
-	pass1 { if (!_Ft_ || (_Ft_ == _Fs_)) { mVUinfo |= _isNOP; } analyzeReg1(_Fs_); analyzeReg2(_Ft_); }
+	pass1 { mVUanalyzeMOVE<vuIndex>(_Fs_, _Ft_); }
 	pass2 { 
 		mVUloadReg<vuIndex>(xmmT1, (uptr)&mVU->regs->VF[_Fs_].UL[0], _X_Y_Z_W);
 		mVUsaveReg<vuIndex>(xmmT1, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 1);

pcsx2/x86/microVU_Upper.inl

@@ -37,7 +37,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
 	//SysPrintf("doStatus = %d; doMac = %d\n", doStatus>>9, doMac>>8);
 	if (mVUflagHack) { mVUinfo &= ~_doStatus; }
 	if (!doFlags) return;
-	if (!doMac) { regT1 = reg; }
+	if (!doMac || (_XYZW_SS && modXYZW)) { regT1 = reg; }
 	else { SSE2_PSHUFD_XMM_to_XMM(regT1, reg, 0x1B); } // Flip wzyx to xyzw
 	if (doStatus) {
 		getFlagReg(sReg, fsInstance); // Set sReg to valid GPR by Cur Flag Instance