mirror of https://github.com/PCSX2/pcsx2.git
microVU: Now properly supports E-bit set on branch delay slot instructions.
(Gets rid of "Unknown Micro VU opcode called" errors in Dark Cloud 2, and possibly fixes some other games) git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1647 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
cottonvibes
parent
4509e085c6
commit
9da4a53929
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@ -89,6 +89,7 @@ public:
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&& (linkI->block->pState.flags == pState->flags)
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&& (linkI->block->pState.xgkick == pState->xgkick)
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&& (linkI->block->pState.viBackUp == pState->viBackUp)
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&& (linkI->block->pState.blockType == pState->blockType)
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&& !(linkI->block->pState.needExactMatch & 5)) { return linkI->block; }
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linkI = linkI->next;
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}
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@ -108,7 +108,7 @@ void normBranch(mV, microFlagCycles& mFC) {
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normBranchCompile(mVU, branchAddr);
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}
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void condBranch(mV, microFlagCycles& mFC, microBlock* &pBlock, int JMPcc) {
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void condBranch(mV, microFlagCycles& mFC, int JMPcc) {
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using namespace x86Emitter;
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mVUsetupBranch(mVU, mFC);
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xCMP(ptr16[&mVU->branch], 0);
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@ -138,8 +138,8 @@ void condBranch(mV, microFlagCycles& mFC, microBlock* &pBlock, int JMPcc) {
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}
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else {
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s32* ajmp = xJcc32((JccComparisonType)JMPcc);
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uptr jumpAddr;
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u32 bPC = iPC; // mVUcompile can modify iPC and mVUregs so back them up
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u32 bPC = iPC; // mVUcompile can modify iPC, mVUpBlock, and mVUregs so back them up
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microBlock* pBlock = mVUpBlock;
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memcpy_fast(&pBlock->pStateEnd, &mVUregs, sizeof(microRegInfo));
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incPC2(1); // Get PC for branch not-taken
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@ -147,13 +147,13 @@ void condBranch(mV, microFlagCycles& mFC, microBlock* &pBlock, int JMPcc) {
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iPC = bPC;
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incPC(-3); // Go back to branch opcode (to get branch imm addr)
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jumpAddr = (uptr)mVUblockFetch(mVU, branchAddr, (uptr)&pBlock->pStateEnd);
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uptr jumpAddr = (uptr)mVUblockFetch(mVU, branchAddr, (uptr)&pBlock->pStateEnd);
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*ajmp = (jumpAddr - ((uptr)ajmp + 4));
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}
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}
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}
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void normJump(mV, microFlagCycles& mFC, microBlock* &pBlock) {
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void normJump(mV, microFlagCycles& mFC) {
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using namespace x86Emitter;
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mVUprint("mVUcompile JR/JALR");
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incPC(-3); // Go back to jump opcode
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@ -178,12 +178,12 @@ void normJump(mV, microFlagCycles& mFC, microBlock* &pBlock) {
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return;
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}
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memcpy_fast(&pBlock->pStateEnd, &mVUregs, sizeof(microRegInfo));
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memcpy_fast(&mVUpBlock->pStateEnd, &mVUregs, sizeof(microRegInfo));
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mVUsetupBranch(mVU, mFC);
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mVUbackupRegs(mVU);
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MOV32MtoR(gprT2, (uptr)&mVU->branch); // Get startPC (ECX 1st argument for __fastcall)
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MOV32ItoR(gprR, (u32)&pBlock->pStateEnd); // Get pState (EDX 2nd argument for __fastcall)
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MOV32MtoR(gprT2, (uptr)&mVU->branch); // Get startPC (ECX 1st argument for __fastcall)
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MOV32ItoR(gprR, (u32)&mVUpBlock->pStateEnd); // Get pState (EDX 2nd argument for __fastcall)
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if (!mVU->index) xCALL(mVUcompileJIT<0>); //(u32 startPC, uptr pState)
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else xCALL(mVUcompileJIT<1>);
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@ -170,10 +170,19 @@ microVUt(void) branchWarning(mV) {
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}
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}
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microVUt(void) eBitWarning(mV) {
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microVUt(void) eBitPass1(mV, int& branch) {
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if (!mVUregs.blockType) {
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branch = 1;
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mVUup.eBit = 1;
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}
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}
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microVUt(void) eBitWarning(mV, u32 endCount) {
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if (endCount == 1) Console::Error("microVU%d Warning: Branch, E-bit, Branch! [%04x]", params mVU->index, xPC);
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incPC(2);
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if (curI & _Ebit_) {
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Console::Error("microVU%d Warning: E-bit in Branch delay slot! [%04x]", params mVU->index, xPC);
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DevCon::Status("microVU%d: E-bit in Branch delay slot! [%04x]", params mVU->index, xPC);
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mVUregs.blockType = 1;
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}
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incPC(-2);
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}
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@ -297,21 +306,21 @@ microVUt(void) mVUinitConstValues(microVU* mVU) {
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}
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// Initialize Variables
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microVUt(void) mVUinitFirstPass(microVU* mVU, microBlock* &pBlock, uptr pState, u8* thisPtr) {
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mVUstartPC = iPC; // Block Start PC
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mVUbranch = 0; // Branch Type
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mVUcount = 0; // Number of instructions ran
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mVUcycles = 0; // Skips "M" phase, and starts counting cycles at "T" stage
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mVU->p = 0; // All blocks start at p index #0
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mVU->q = 0; // All blocks start at q index #0
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microVUt(void) mVUinitFirstPass(microVU* mVU, uptr pState, u8* thisPtr) {
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mVUstartPC = iPC; // Block Start PC
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mVUbranch = 0; // Branch Type
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mVUcount = 0; // Number of instructions ran
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mVUcycles = 0; // Skips "M" phase, and starts counting cycles at "T" stage
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mVU->p = 0; // All blocks start at p index #0
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mVU->q = 0; // All blocks start at q index #0
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memcpy_fast(&mVUregs, (microRegInfo*)pState, sizeof(microRegInfo)); // Loads up Pipeline State Info
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mVUblock.x86ptrStart = thisPtr;
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pBlock = mVUblocks[mVUstartPC/2]->add(&mVUblock); // Add this block to block manager
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mVUpBlock = pBlock;
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mVUregs.viBackUp= 0;
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mVUregs.flags = 0;
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mVUflagInfo = 0;
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mVUsFlagHack = CHECK_VU_FLAGHACK;
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mVUblock.x86ptrStart = thisPtr;
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mVUpBlock = mVUblocks[mVUstartPC/2]->add(&mVUblock); // Add this block to block manager
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mVUregs.blockType = 0;
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mVUregs.viBackUp = 0;
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mVUregs.flags = 0;
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mVUregs.needExactMatch = 0;
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mVUsFlagHack = CHECK_VU_FLAGHACK;
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mVUinitConstValues(mVU);
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}
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@ -323,22 +332,21 @@ microVUr(void*) mVUcompile(microVU* mVU, u32 startPC, uptr pState) {
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using namespace x86Emitter;
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microFlagCycles mFC;
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microBlock* pBlock = NULL;
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u8* thisPtr = x86Ptr;
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const u32 endCount = (mVU->microMemSize / 8) - 1;
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const u32 endCount = (((microRegInfo*)pState)->blockType) ? 1 : (mVU->microMemSize / 8);
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// First Pass
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iPC = startPC / 4;
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mVUsetupRange(mVU, startPC, 1); // Setup Program Bounds/Range
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mVU->regAlloc->reset(); // Reset regAlloc
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mVUinitFirstPass(mVU, pBlock, pState, thisPtr);
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mVUinitFirstPass(mVU, pState, thisPtr);
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for (int branch = 0; mVUcount < endCount; mVUcount++) {
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incPC(1);
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startLoop(mVU);
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mVUincCycles(mVU, 1);
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mVUopU(mVU, 0);
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if (curI & _Ebit_) { branch = 1; mVUup.eBit = 1; }
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if (curI & _Ebit_) { eBitPass1(mVU, branch); }
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if (curI & _DTbit_) { branch = 4; }
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if (curI & _Mbit_) { mVUup.mBit = 1; }
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if (curI & _Ibit_) { mVUlow.isNOP = 1; mVUup.iBit = 1; }
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@ -350,7 +358,7 @@ microVUr(void*) mVUcompile(microVU* mVU, u32 startPC, uptr pState) {
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mVUinfo.writeP = !mVU->p;
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if (branch >= 2) { mVUinfo.isEOB = 1; if (branch == 3) { mVUinfo.isBdelay = 1; } mVUcount++; branchWarning(mVU); break; }
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else if (branch == 1) { branch = 2; }
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if (mVUbranch) { mVUsetFlagInfo(mVU); eBitWarning(mVU); branch = 3; mVUbranch = 0; }
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if (mVUbranch) { mVUsetFlagInfo(mVU); eBitWarning(mVU, endCount); branch = 3; mVUbranch = 0; }
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incPC(1);
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}
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@ -379,18 +387,18 @@ microVUr(void*) mVUcompile(microVU* mVU, u32 startPC, uptr pState) {
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mVUsetupRange(mVU, xPC, 0);
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mVUdebugNOW(1);
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switch (mVUbranch) {
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case 3: condBranch(mVU, mFC, pBlock, Jcc_Equal); return thisPtr; // IBEQ
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case 4: condBranch(mVU, mFC, pBlock, Jcc_GreaterOrEqual); return thisPtr; // IBGEZ
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case 5: condBranch(mVU, mFC, pBlock, Jcc_Greater); return thisPtr; // IBGTZ
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case 6: condBranch(mVU, mFC, pBlock, Jcc_LessOrEqual); return thisPtr; // IBLEQ
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case 7: condBranch(mVU, mFC, pBlock, Jcc_Less); return thisPtr; // IBLTZ
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case 8: condBranch(mVU, mFC, pBlock, Jcc_NotEqual); return thisPtr; // IBNEQ
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case 1: case 2: normBranch(mVU, mFC); return thisPtr; // B/BAL
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case 9: case 10: normJump (mVU, mFC, pBlock); return thisPtr; // JR/JALR
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case 1: case 2: normBranch(mVU, mFC); return thisPtr; // B/BAL
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case 9: case 10: normJump (mVU, mFC); return thisPtr; // JR/JALR
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case 3: condBranch(mVU, mFC, Jcc_Equal); return thisPtr; // IBEQ
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case 4: condBranch(mVU, mFC, Jcc_GreaterOrEqual); return thisPtr; // IBGEZ
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case 5: condBranch(mVU, mFC, Jcc_Greater); return thisPtr; // IBGTZ
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case 6: condBranch(mVU, mFC, Jcc_LessOrEqual); return thisPtr; // IBLEQ
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case 7: condBranch(mVU, mFC, Jcc_Less); return thisPtr; // IBLTZ
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case 8: condBranch(mVU, mFC, Jcc_NotEqual); return thisPtr; // IBNEQ
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}
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}
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}
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if (x == endCount) { Console::Error("microVU%d: Possible infinite compiling loop!", params mVU->index); }
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if ((x == endCount) && (x!=1)) { Console::Error("microVU%d: Possible infinite compiling loop!", params mVU->index); }
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// E-bit End
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mVUsetupRange(mVU, xPC-8, 0);
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@ -248,7 +248,7 @@ void mVUflagPass(mV, u32 startPC, u32 xCount) {
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if (mVUbranch) { branch = ((mVUbranch>8)?(5):((mVUbranch<3)?3:4)); aBranchAddr = branchAddr; mVUbranch = 0; }
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incPC(1);
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}
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if (mVUcount < 4) { mVUflagInfo |= 0x7; }
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if (mVUcount < 4) { mVUregs.needExactMatch |= 0x7; }
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iPC = oldPC;
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mVUcount = oldCount;
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mVUbranch = oldBranch;
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@ -263,18 +263,18 @@ void mVUflagPass(mV, u32 startPC, u32 xCount) {
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microVUt(void) mVUsetFlagInfo(mV) {
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branchType1 { incPC(-1); mVUflagPass(mVU, branchAddr, 4); incPC(1); }
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branchType2 {
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if (!mVUlow.constJump.isValid) { mVUflagInfo |= 0x7; }
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if (!mVUlow.constJump.isValid) { mVUregs.needExactMatch |= 0x7; }
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else { mVUflagPass(mVU, (mVUlow.constJump.regValue*8)&(mVU->microMemSize-8), 4); }
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}
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branchType3 {
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incPC(-1);
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mVUflagPass(mVU, branchAddr, 4);
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int backupFlagInfo = mVUflagInfo;
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mVUflagInfo = 0;
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int backupFlagInfo = mVUregs.needExactMatch;
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mVUregs.needExactMatch = 0;
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incPC(4); // Branch Not Taken
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mVUflagPass(mVU, xPC, 4);
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incPC(-3);
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mVUflagInfo |= backupFlagInfo;
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mVUregs.needExactMatch |= backupFlagInfo;
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}
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}
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@ -44,7 +44,8 @@ __declspec(align(16)) struct microRegInfo { // Ordered for Faster Compares
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u8 VI[16];
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regInfo VF[32];
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u8 flags; // clip x2 :: status x2
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u8 padding[6]; // 160 bytes
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u8 blockType; // 0 = Normal; 1 = Compile one instruction with E-bit termination
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u8 padding[5]; // 160 bytes
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#if defined(_MSC_VER)
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};
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#else
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@ -458,7 +458,7 @@ mVUop(mVU_FCAND) {
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mVUallocVIb(mVU, gprT1, 1);
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}
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pass3 { mVUlog("FCAND vi01, $%x", _Imm24_); }
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pass4 { mVUflagInfo |= 4; }
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pass4 { mVUregs.needExactMatch |= 4; }
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}
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mVUop(mVU_FCEQ) {
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@ -471,7 +471,7 @@ mVUop(mVU_FCEQ) {
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mVUallocVIb(mVU, gprT1, 1);
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}
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pass3 { mVUlog("FCEQ vi01, $%x", _Imm24_); }
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pass4 { mVUflagInfo |= 4; }
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pass4 { mVUregs.needExactMatch |= 4; }
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}
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mVUop(mVU_FCGET) {
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@ -482,7 +482,7 @@ mVUop(mVU_FCGET) {
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mVUallocVIb(mVU, gprT1, _It_);
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}
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pass3 { mVUlog("FCGET vi%02d", _Ft_); }
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pass4 { mVUflagInfo |= 4; }
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pass4 { mVUregs.needExactMatch |= 4; }
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}
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mVUop(mVU_FCOR) {
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@ -495,7 +495,7 @@ mVUop(mVU_FCOR) {
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mVUallocVIb(mVU, gprT1, 1);
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}
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pass3 { mVUlog("FCOR vi01, $%x", _Imm24_); }
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pass4 { mVUflagInfo |= 4; }
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pass4 { mVUregs.needExactMatch |= 4; }
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}
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mVUop(mVU_FCSET) {
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@ -520,7 +520,7 @@ mVUop(mVU_FMAND) {
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mVUallocVIb(mVU, gprT1, _It_);
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}
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pass3 { mVUlog("FMAND vi%02d, vi%02d", _Ft_, _Fs_); }
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pass4 { mVUflagInfo |= 2; }
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pass4 { mVUregs.needExactMatch |= 2; }
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}
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mVUop(mVU_FMEQ) {
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@ -534,7 +534,7 @@ mVUop(mVU_FMEQ) {
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mVUallocVIb(mVU, gprT1, _It_);
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}
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pass3 { mVUlog("FMEQ vi%02d, vi%02d", _Ft_, _Fs_); }
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pass4 { mVUflagInfo |= 2; }
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pass4 { mVUregs.needExactMatch |= 2; }
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}
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mVUop(mVU_FMOR) {
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@ -546,7 +546,7 @@ mVUop(mVU_FMOR) {
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mVUallocVIb(mVU, gprT1, _It_);
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}
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pass3 { mVUlog("FMOR vi%02d, vi%02d", _Ft_, _Fs_); }
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pass4 { mVUflagInfo |= 2; }
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pass4 { mVUregs.needExactMatch |= 2; }
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}
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//------------------------------------------------------------------
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@ -561,7 +561,7 @@ mVUop(mVU_FSAND) {
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mVUallocVIb(mVU, gprT1, _It_);
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}
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pass3 { mVUlog("FSAND vi%02d, $%x", _Ft_, _Imm12_); }
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pass4 { mVUflagInfo |= 1; }
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pass4 { mVUregs.needExactMatch |= 1; }
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}
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mVUop(mVU_FSOR) {
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@ -572,7 +572,7 @@ mVUop(mVU_FSOR) {
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mVUallocVIb(mVU, gprT1, _It_);
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}
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pass3 { mVUlog("FSOR vi%02d, $%x", _Ft_, _Imm12_); }
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pass4 { mVUflagInfo |= 1; }
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pass4 { mVUregs.needExactMatch |= 1; }
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}
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mVUop(mVU_FSEQ) {
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@ -604,7 +604,7 @@ mVUop(mVU_FSEQ) {
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mVUallocVIb(mVU, gprT1, _It_);
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}
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pass3 { mVUlog("FSEQ vi%02d, $%x", _Ft_, _Imm12_); }
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pass4 { mVUflagInfo |= 1; }
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pass4 { mVUregs.needExactMatch |= 1; }
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}
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mVUop(mVU_FSSET) {
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@ -205,7 +205,6 @@ typedef u32 (__fastcall *mVUCall)(void*, void*);
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#define sFLAG mVUinfo.sFlag
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#define mFLAG mVUinfo.mFlag
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#define cFLAG mVUinfo.cFlag
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#define mVUflagInfo mVUregs.needExactMatch
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#define mVUrange mVUcurProg.ranges.range[mVUcurProg.ranges.total]
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#define xPC ((iPC / 2) * 8)
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#define curI ((u32*)mVU->regs->Micro)[iPC] //mVUcurProg.data[iPC]
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@ -222,9 +221,9 @@ typedef u32 (__fastcall *mVUCall)(void*, void*);
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#define shuffleSS(x) ((x==1)?(0x27):((x==2)?(0xc6):((x==4)?(0xe1):(0xe4))))
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// Flag Info
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#define __Status (mVUflagInfo & 1)
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#define __Mac (mVUflagInfo & 2)
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#define __Clip (mVUflagInfo & 4)
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#define __Status (mVUregs.needExactMatch & 1)
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#define __Mac (mVUregs.needExactMatch & 2)
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#define __Clip (mVUregs.needExactMatch & 4)
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// Pass 3 Helper Macros
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#define _Fsf_String ((_Fsf_ == 3) ? "w" : ((_Fsf_ == 2) ? "z" : ((_Fsf_ == 1) ? "y" : "x")))
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