mirror of https://github.com/PCSX2/pcsx2.git
IOP Counter/IRQ: Misc Counter and IRQ handling changes based on NoCash documents for PS1.
This commit is contained in:
refractionpcsx2
parent
d01f8f9252
commit
9a2212c86e
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@ -49,9 +49,13 @@ u8 psxvblankgate = 0;
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#define IOPCNT_FUTURE_TARGET (0x1000000000ULL)
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#define IOPCNT_ENABLE_GATE (1<<0) // enables gate-based counters
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#define IOPCNT_MODE_GATE (3<<1) // 0x6 Gate mode (dependant on counter)
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#define IOPCNT_MODE_RESET (1<<3) // 0x8 resets the counter on target (if interrupt only?)
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#define IOPCNT_INT_TARGET (1<<4) // 0x10 triggers an interrupt on targets
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#define IOPCNT_INT_OVERFLOW (1<<5) // 0x20 triggers an interrupt on overflows
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#define IOPCNT_INT_TOGGLE (1<<7) // 0x80 0=Pulse (reset on read), 1=toggle each interrupt condition (in 1 shot not reset after fired)
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#define IOPCNT_ALT_SOURCE (1<<8) // 0x100 uses hblank on counters 1 and 3, and PSXCLOCK on counter 0
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#define IOPCNT_INT_REQ (1<<10) // 0x400 1=Can fire interrupt, 0=Interrupt Fired (reset on read if not 1 shot)
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// Use an arbitrary value to flag HBLANK counters.
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// These counters will be counted by the hblank gates coming from the EE,
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@ -163,6 +167,34 @@ void psxRcntInit() {
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psxNextsCounter = psxRegs.cycle;
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}
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static bool __fastcall _rcntFireInterrupt(int i, bool isOverflow) {
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bool ret;
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if ((psxCounters[i].mode & 0x400)) { //IRQ fired
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//DevCon.Warning("Counter %d %s IRQ Fired count %x", i, isOverflow == true ? "Overflow" : "Target", psxCounters[i].count);
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psxHu32(0x1070) |= psxCounters[i].interrupt;
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iopTestIntc();
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ret = true;
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}
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else {
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//DevCon.Warning("Counter %d IRQ not fired count %x", i, psxCounters[i].count);
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ret = false;
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if (!(psxCounters[i].mode & 0x40)) //One shot
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{
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Console.WriteLn("Counter %x repeat intr not set on zero ret, ignoring target", i);
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return ret;
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}
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}
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if (psxCounters[i].mode & 0x80) { //Toggle mode
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psxCounters[i].mode ^= 0x400; // Interrupt flag inverted
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}
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else {
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psxCounters[i].mode &= ~0x0400; // Interrupt flag set low
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}
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return ret;
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}
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static void __fastcall _rcntTestTarget( int i )
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{
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if( psxCounters[i].count < psxCounters[i].target ) return;
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@ -173,24 +205,19 @@ static void __fastcall _rcntTestTarget( int i )
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if (psxCounters[i].mode & IOPCNT_INT_TARGET)
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{
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// Target interrupt
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if(psxCounters[i].mode & 0x80)
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psxCounters[i].mode &= ~0x0400; // Interrupt flag
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psxCounters[i].mode |= 0x0800; // Target flag
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psxHu32(0x1070) |= psxCounters[i].interrupt;
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if(_rcntFireInterrupt(i, false))
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psxCounters[i].mode |= 0x0800; // Target flag
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}
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if (psxCounters[i].mode & 0x08)
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{
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// Reset on target
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psxCounters[i].count -= psxCounters[i].target;
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if(!(psxCounters[i].mode & 0x40))
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{
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Console.WriteLn("Counter %x repeat intr not set on zero ret, ignoring target", i);
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psxCounters[i].target |= IOPCNT_FUTURE_TARGET;
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}
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} else psxCounters[i].target |= IOPCNT_FUTURE_TARGET;
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}
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else
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psxCounters[i].target |= IOPCNT_FUTURE_TARGET;
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}
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@ -201,23 +228,37 @@ static __fi void _rcntTestOverflow( int i )
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PSXCNT_LOG("IOP Counter[%d] overflow 0x%I64x >= 0x%I64x (mode: %x)",
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i, psxCounters[i].count, maxTarget, psxCounters[i].mode );
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if (!(psxCounters[i].mode & 0x40)) //One shot, whichever condition is met first
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{
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if (psxCounters[i].target < IOPCNT_FUTURE_TARGET) { //Target didn't trigger so we can overflow
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// Overflow interrupt
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if ((psxCounters[i].mode & IOPCNT_INT_OVERFLOW)) {
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if (_rcntFireInterrupt(i, true))
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psxCounters[i].mode |= 0x1000; // Overflow flag
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}
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}
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psxCounters[i].target |= IOPCNT_FUTURE_TARGET;
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if(psxCounters[i].mode & IOPCNT_INT_OVERFLOW)
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}
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else
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{
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// Overflow interrupt
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psxHu32(0x1070) |= psxCounters[i].interrupt;
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psxCounters[i].mode |= 0x1000; // Overflow flag
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if(psxCounters[i].mode & 0x80)
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psxCounters[i].mode &= ~0x0400; // Interrupt flag
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if ((psxCounters[i].mode & IOPCNT_INT_OVERFLOW)) {
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if (_rcntFireInterrupt(i, true))
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psxCounters[i].mode |= 0x1000; // Overflow flag
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}
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psxCounters[i].target &= maxTarget;
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}
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// Update count and target.
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// Count wraps around back to zero, while the target is restored (if needed).
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// Update count.
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// Count wraps around back to zero, while the target is restored (if not in one shot mode).
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// (high bit of the target gets set by rcntWtarget when the target is behind
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// the counter value, and thus should not be flagged until after an overflow)
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psxCounters[i].count &= maxTarget;
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psxCounters[i].target &= maxTarget;
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psxCounters[i].count -= maxTarget;
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}
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/*
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@ -403,9 +444,15 @@ void psxRcntUpdate()
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// don't count disabled or hblank counters...
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// We can't check the ALTSOURCE flag because the PSXCLOCK source *should*
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// be counted here.
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if( psxCounters[i].mode & IOPCNT_STOPPED ) continue;
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if ((psxCounters[i].mode & 0x40) && !(psxCounters[i].mode & 0x80)) { //Repeat IRQ mode Pulsed, resets a few cycles after the interrupt, this should do.
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psxCounters[i].mode |= 0x400;
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}
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if( psxCounters[i].rate == PSXHBLANK ) continue;
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if( change <= 0 ) continue;
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psxCounters[i].count += change / psxCounters[i].rate;
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@ -500,7 +547,7 @@ void psxRcntWcount16(int index, u16 value)
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u32 change;
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pxAssert( index < 3 );
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PSXCNT_LOG("IOP Counter[%d] writeCount16 = %x", index, value);
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//DevCon.Warning("16bit IOP Counter[%d] writeCount16 = %x", index, value);
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if(psxCounters[index].rate != PSXHBLANK)
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{
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@ -512,7 +559,13 @@ void psxRcntWcount16(int index, u16 value)
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}
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psxCounters[index].count = value & 0xffff;
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psxCounters[index].target &= 0xffff;
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if ((psxCounters[index].mode & 0x400) == 1 || (psxCounters[index].mode & 0x40)) {
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psxCounters[index].target &= 0xffff;
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}
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if (value > psxCounters[index].target) {//Count already higher than Target
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// DevCon.Warning("16bit Count already higher than target");
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psxCounters[index].target |= IOPCNT_FUTURE_TARGET;
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}
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_rcntSet( index );
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}
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@ -523,7 +576,7 @@ void psxRcntWcount32(int index, u32 value)
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u32 change;
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pxAssert( index >= 3 && index < 6 );
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PSXCNT_LOG("IOP Counter[%d] writeCount32 = %x", index, value);
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PSXCNT_LOG("32bit IOP Counter[%d] writeCount32 = %x", index, value);
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if(psxCounters[index].rate != PSXHBLANK)
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{
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@ -534,23 +587,49 @@ void psxRcntWcount32(int index, u32 value)
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psxCounters[index].sCycleT = psxRegs.cycle - (change % psxCounters[index].rate);
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}
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psxCounters[index].count = value & 0xffffffff;
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psxCounters[index].target &= 0xffffffff;
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psxCounters[index].count = value;
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if ((psxCounters[index].mode & 0x400) == 1 || (psxCounters[index].mode & 0x40)) { //IRQ not triggered (one shot) or toggle
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psxCounters[index].target &= 0xffffffff;
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}
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if (value > psxCounters[index].target) {//Count already higher than Target
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//DevCon.Warning("32bit Count already higher than target");
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psxCounters[index].target |= IOPCNT_FUTURE_TARGET;
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}
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_rcntSet( index );
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}
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//////////////////////////////////////////////////////////////////////////////////////////
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//
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__fi void psxRcntWmode16( int index, u32 value )
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__fi void psxRcntWmode16(int index, u32 value)
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{
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PSXCNT_LOG( "IOP Counter[%d] writeMode = 0x%04X", index, value );
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int irqmode = 0;
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PSXCNT_LOG("16bit IOP Counter[%d] writeMode = 0x%04X", index, value);
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pxAssume( index >= 0 && index < 3 );
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pxAssume(index >= 0 && index < 3);
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psxCounter& counter = psxCounters[index];
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counter.mode = value;
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counter.mode |= 0x0400;
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counter.mode = value;
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counter.mode |= 0x0400; //IRQ Enable
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if (value & (1 << 4)) {
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irqmode += 1;
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}
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if (value & (1 << 5)) {
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irqmode += 2;
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}
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if (value & (1 << 7)) {
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PSXCNT_LOG("16 Counter %d Toggle IRQ on %s", index, (irqmode & 3) == 1 ? "Target" : ((irqmode & 3) == 2 ? "Overflow" : "Target and Overflow"));
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}
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else
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{
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PSXCNT_LOG("16 Counter %d Pulsed IRQ on %s", index, (irqmode & 3) == 1 ? "Target" : ((irqmode & 3) == 2 ? "Overflow" : "Target and Overflow"));
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}
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if (!(value & (1 << 6))) {
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PSXCNT_LOG("16 Counter %d One Shot", index);
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}
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else {
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PSXCNT_LOG("16 Counter %d Repeat", index);
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}
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if( index == 2 )
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{
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switch(value & 0x200)
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@ -595,8 +674,9 @@ __fi void psxRcntWmode16( int index, u32 value )
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counter.count = 0;
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counter.sCycleT = psxRegs.cycle;
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counter.target &= 0xffff;
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counter.target &= 0xffff;
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_rcntSet( index );
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}
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@ -604,14 +684,33 @@ __fi void psxRcntWmode16( int index, u32 value )
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//
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__fi void psxRcntWmode32( int index, u32 value )
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{
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PSXCNT_LOG( "IOP Counter[%d] writeMode = 0x%04x", index, value );
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PSXCNT_LOG("32bit IOP Counter[%d] writeMode = 0x%04x", index, value );
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int irqmode = 0;
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pxAssume( index >= 3 && index < 6 );
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psxCounter& counter = psxCounters[index];
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counter.mode = value;
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counter.mode |= 0x0400;
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counter.mode |= 0x0400; //IRQ enable
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if (value & (1 << 4)) {
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irqmode += 1;
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}
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if (value & (1 << 5)) {
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irqmode += 2;
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}
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if (value & (1 << 7)) {
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PSXCNT_LOG("32 Counter %d Toggle IRQ on %s", index, (irqmode & 3) == 1 ? "Target" : ((irqmode & 3) == 2 ? "Overflow" : "Target and Overflow"));
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}
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else
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{
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PSXCNT_LOG("32 Counter %d Pulsed IRQ on %s", index, (irqmode & 3) == 1 ? "Target" : ((irqmode & 3) == 2 ? "Overflow" : "Target and Overflow"));
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}
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if (!(value & (1 << 6))) {
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PSXCNT_LOG("32 Counter %d One Shot", index);
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}
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else {
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PSXCNT_LOG("32 Counter %d Repeat", index);
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}
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if( index == 3 )
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{
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// Counter 3 has the HBlank as an alternate source.
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@ -656,14 +755,14 @@ __fi void psxRcntWmode32( int index, u32 value )
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void psxRcntWtarget16(int index, u32 value)
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{
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pxAssert( index < 3 );
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PSXCNT_LOG("IOP Counter[%d] writeTarget16 = %lx", index, value);
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//DevCon.Warning("IOP Counter[%d] writeTarget16 = %lx", index, value);
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psxCounters[index].target = value & 0xffff;
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// protect the target from an early arrival.
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// if the target is behind the current count, then set the target overflow
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// flag, so that the target won't be active until after the next overflow.
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if(psxCounters[index].target <= psxRcntCycles(index))
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if(psxCounters[index].target <= psxRcntCycles(index) || ((psxCounters[index].mode & 0x400) == 0 && !(psxCounters[index].mode & 0x40)))
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psxCounters[index].target |= IOPCNT_FUTURE_TARGET;
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_rcntSet( index );
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@ -672,15 +771,17 @@ void psxRcntWtarget16(int index, u32 value)
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void psxRcntWtarget32(int index, u32 value)
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{
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pxAssert( index >= 3 && index < 6);
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PSXCNT_LOG("IOP Counter[%d] writeTarget32 = %lx", index, value);
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//DevCon.Warning("IOP Counter[%d] writeTarget32 = %lx mode %x", index, value, psxCounters[index].mode);
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psxCounters[index].target = value;
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if (!(psxCounters[index].mode & 0x80)) { //Toggle mode
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psxCounters[index].mode |= 0x0400; // Interrupt flag set low
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}
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// protect the target from an early arrival.
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// if the target is behind the current count, then set the target overflow
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// flag, so that the target won't be active until after the next overflow.
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if(psxCounters[index].target <= psxRcntCycles(index))
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if (psxCounters[index].target <= psxRcntCycles(index) || ((psxCounters[index].mode & 0x400) == 0 && !(psxCounters[index].mode & 0x40)))
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psxCounters[index].target |= IOPCNT_FUTURE_TARGET;
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_rcntSet( index );
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@ -54,17 +54,44 @@ __fi void psxHw4Write8(u32 add, u8 value)
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void psxDmaInterrupt(int n)
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{
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if (HW_DMA_ICR & (1 << (16 + n)))
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if(n == 33) {
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for (int i = 0; i < 6; i++) {
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if (HW_DMA_ICR & (1 << (16 + i))) {
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if (HW_DMA_ICR & (1 << (24 + i))) {
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if (HW_DMA_ICR & (1 << 23)) {
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HW_DMA_ICR |= 0x80000000; //Set master IRQ condition met
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}
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psxRegs.CP0.n.Cause &= ~0x7C;
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iopIntcIrq(3);
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break;
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}
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}
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}
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} else if (HW_DMA_ICR & (1 << (16 + n)))
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{
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HW_DMA_ICR|= (1 << (24 + n));
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psxRegs.CP0.n.Cause |= 1 << (9 + n);
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iopIntcIrq( 3 );
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HW_DMA_ICR |= (1 << (24 + n));
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if (HW_DMA_ICR & (1 << 23)) {
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HW_DMA_ICR |= 0x80000000; //Set master IRQ condition met
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}
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iopIntcIrq(3);
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}
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}
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void psxDmaInterrupt2(int n)
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{
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if (HW_DMA_ICR2 & (1 << (16 + n)))
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if (n == 33) {
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for (int i = 0; i < 6; i++) {
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if (HW_DMA_ICR2 & (1 << (16 + i))) {
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if (HW_DMA_ICR2 & (1 << (24 + i))) {
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if (HW_DMA_ICR2 & (1 << 23)) {
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HW_DMA_ICR2 |= 0x80000000; //Set master IRQ condition met
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}
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iopIntcIrq(3);
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break;
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}
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}
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}
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} else if (HW_DMA_ICR2 & (1 << (16 + n)))
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{
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/* if (HW_DMA_ICR2 & (1 << (24 + n))) {
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Console.WriteLn("*PCSX2*: HW_DMA_ICR2 n=%d already set", n);
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@ -73,7 +100,9 @@ void psxDmaInterrupt2(int n)
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Console.WriteLn("*PCSX2*: psxHu32(0x1070) 8 already set (n=%d)", n);
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}*/
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HW_DMA_ICR2|= (1 << (24 + n));
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psxRegs.CP0.n.Cause |= 1 << (16 + n);
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iopIntcIrq( 3 );
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if (HW_DMA_ICR2 & (1 << 23)) {
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HW_DMA_ICR2 |= 0x80000000; //Set master IRQ condition met
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}
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iopIntcIrq(3);
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}
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}
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@ -148,14 +148,14 @@ static __fi T _HwRead_16or32_Page1( u32 addr )
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// should it do the logic for both 16 and 32, or not do logic at all?
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psxCounters[cntidx].mode &= ~0x1800;
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psxCounters[cntidx].mode |= 0x400;
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break;
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case 0x8:
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ret = psxCounters[cntidx].target;
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break;
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default:
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DevCon.Warning("Unknown 16bit counter read %x", addr);
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ret = psxHu32(addr);
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break;
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}
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@ -184,7 +184,6 @@ static __fi T _HwRead_16or32_Page1( u32 addr )
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// should it do the logic for both 16 and 32, or not do logic at all?
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psxCounters[cntidx].mode &= ~0x1800;
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psxCounters[cntidx].mode |= 0x400;
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break;
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case 0x8:
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|
@ -196,6 +195,7 @@ static __fi T _HwRead_16or32_Page1( u32 addr )
|
|||
break;
|
||||
|
||||
default:
|
||||
DevCon.Warning("Unknown 32bit counter read %x", addr);
|
||||
ret = psxHu32(addr);
|
||||
break;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -429,13 +429,34 @@ static __fi void _HwWrite_16or32_Page1( u32 addr, T val )
|
|||
|
||||
mcase(0x1f8010f4):
|
||||
{
|
||||
u32 tmp = (~val) & HW_DMA_ICR;
|
||||
psxHu(addr) = ((tmp ^ val) & 0xffffff) ^ tmp;
|
||||
}
|
||||
//u32 tmp = (~val) & HW_DMA_ICR;
|
||||
//u32 old = ((tmp ^ val) & 0xffffff) ^ tmp;
|
||||
///psxHu(addr) = ((tmp ^ val) & 0xffffff) ^ tmp;
|
||||
u32 newtmp = (HW_DMA_ICR & 0xff000000) | (val & 0xffffff);
|
||||
newtmp &= ~(val & 0x7F000000);
|
||||
if (((newtmp >> 15) & 0x1) || (((newtmp >> 23) & 0x1) == 0x1 && (((newtmp & 0x7F000000) >> 8) & (newtmp & 0x7F0000)) != 0)) {
|
||||
newtmp |= 0x80000000;
|
||||
}
|
||||
else {
|
||||
newtmp &= ~0x80000000;
|
||||
}
|
||||
//if (newtmp != old)
|
||||
// DevCon.Warning("ICR Old %x New %x", old, newtmp);
|
||||
psxHu(addr) = newtmp;
|
||||
if ((HW_DMA_ICR >> 15) & 0x1) {
|
||||
DevCon.Warning("Force ICR IRQ!");
|
||||
psxRegs.CP0.n.Cause &= ~0x7C;
|
||||
iopIntcIrq(3);
|
||||
}
|
||||
else {
|
||||
psxDmaInterrupt(33);
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
|
||||
mcase(0x1f8010f6): // ICR_hi (16 bit?) [dunno if it ever happens]
|
||||
{
|
||||
DevCon.Warning("High ICR Write!!");
|
||||
const u32 val2 = (u32)val << 16;
|
||||
const u32 tmp = (~val2) & HW_DMA_ICR;
|
||||
psxHu(addr) = (((tmp ^ val2) & 0xffffff) ^ tmp) >> 16;
|
||||
|
|
@ -444,13 +465,36 @@ static __fi void _HwWrite_16or32_Page1( u32 addr, T val )
|
|||
|
||||
mcase(0x1f801574):
|
||||
{
|
||||
u32 tmp = (~val) & HW_DMA_ICR2;
|
||||
psxHu(addr) = ((tmp ^ val) & 0xffffff) ^ tmp;
|
||||
/*u32 tmp = (~val) & HW_DMA_ICR2;
|
||||
psxHu(addr) = ((tmp ^ val) & 0xffffff) ^ tmp;*/
|
||||
//u32 tmp = (~val) & HW_DMA_ICR2;
|
||||
//u32 old = ((tmp ^ val) & 0xffffff) ^ tmp;
|
||||
///psxHu(addr) = ((tmp ^ val) & 0xffffff) ^ tmp;
|
||||
u32 newtmp = (HW_DMA_ICR2 & 0xff000000) | (val & 0xffffff);
|
||||
newtmp &= ~(val & 0x7F000000);
|
||||
if (((newtmp >> 15) & 0x1) || (((newtmp >> 23) & 0x1) == 0x1 && (((newtmp & 0x7F000000) >> 8) & (newtmp & 0x7F0000)) != 0)) {
|
||||
newtmp |= 0x80000000;
|
||||
}
|
||||
else {
|
||||
newtmp &= ~0x80000000;
|
||||
}
|
||||
//if (newtmp != old)
|
||||
// DevCon.Warning("ICR2 Old %x New %x", old, newtmp);
|
||||
psxHu(addr) = newtmp;
|
||||
if ((HW_DMA_ICR2 >> 15) & 0x1) {
|
||||
DevCon.Warning("Force ICR2 IRQ!");
|
||||
psxRegs.CP0.n.Cause &= ~0x7C;
|
||||
iopIntcIrq(3);
|
||||
}
|
||||
else {
|
||||
psxDmaInterrupt2(33);
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
mcase(0x1f801576): // ICR2_hi (16 bit?) [dunno if it ever happens]
|
||||
{
|
||||
DevCon.Warning("ICR2 high write!");
|
||||
const u32 val2 = (u32)val << 16;
|
||||
const u32 tmp = (~val2) & HW_DMA_ICR2;
|
||||
psxHu(addr) = (((tmp ^ val2) & 0xffffff) ^ tmp) >> 16;
|
||||
|
|
|
|||
Loading…
Reference in New Issue