diff --git a/pcsx2/PsxDma.c b/pcsx2/PsxDma.c
index da718d7e36..7497ee1f4b 100644
--- a/pcsx2/PsxDma.c
+++ b/pcsx2/PsxDma.c
@@ -152,7 +152,7 @@ void psxDma9(u32 madr, u32 bcr, u32 chcr) {
 	iopsifbusy[0] = 1;
 	psHu32(0x1000F240) |= 0x2000;
 	
-	if (eesifbusy[0] == 1 && iopsifbusy[0] == 1) {
+	if (eesifbusy[0] == 1) {
 		SIF0Dma();
 		psHu32(0x1000F240) &= ~0x20;
 		psHu32(0x1000F240) &= ~0x2000;
@@ -165,7 +165,7 @@ void psxDma10(u32 madr, u32 bcr, u32 chcr) {
 	iopsifbusy[1] = 1;
 	psHu32(0x1000F240) |= 0x4000;
 	
-	if (eesifbusy[1] == 1 && iopsifbusy[1] == 1) {
+	if (eesifbusy[1] == 1) {
 		FreezeXMMRegs(1);
 		SIF1Dma();
 		psHu32(0x1000F240) &= ~0x40;
diff --git a/pcsx2/Sif.c b/pcsx2/Sif.c
index 5515eab67f..c553da51c3 100644
--- a/pcsx2/Sif.c
+++ b/pcsx2/Sif.c
@@ -237,7 +237,7 @@ _inline void SIF0Dma()
 		{
 			int size = sif0dma->qwc;
 			if ((psHu32(DMAC_CTRL) & 0x30) == 0x10) { // STS == fromSIF0
-				SysPrintf("SIF0 stall control\n");
+				SIF_LOG("SIF0 stall control\n");
 			}
 			if(size > 0) // If we're reading something continue to do so
 			{
@@ -332,7 +332,7 @@ _inline void SIF1Dma()
 		if(eesifbusy[1] == 1) // If EE SIF1 is enabled
 		{
 			
-			if ((psHu32(DMAC_CTRL) & 0xC0) == 0xC0) SysPrintf("SIF1 stall control\n"); // STS == fromSIF1
+			if ((psHu32(DMAC_CTRL) & 0xC0) == 0xC0) SIF_LOG("SIF1 stall control\n"); // STS == fromSIF1
 
 			if(sif1dma->qwc == 0) // If there's no more to transfer
 			{
@@ -546,7 +546,7 @@ _inline void dmaSIF0() {
 			sif0dma->chcr, sif0dma->madr, sif0dma->qwc, sif0dma->tadr);
 
 	if (sif0.fifoReadPos != sif0.fifoWritePos) {
-		SysPrintf("warning, sif0.fifoReadPos != sif0.fifoWritePos\n");
+		SIF_LOG("warning, sif0.fifoReadPos != sif0.fifoWritePos\n");
 	}
 //    if(sif0dma->qwc > 0 & (sif0dma->chcr & 0x4) == 0x4) {
 //        sif0dma->chcr &= ~4; //Halflife sets a QWC amount in chain mode, no tadr set.
@@ -570,7 +570,7 @@ _inline void dmaSIF1() {
 			sif1dma->chcr, sif1dma->madr, sif1dma->qwc, sif1dma->tadr);
 
 	if (sif1.fifoReadPos != sif1.fifoWritePos) {
-		SysPrintf("warning, sif1.fifoReadPos != sif1.fifoWritePos\n");
+		SIF_LOG("warning, sif1.fifoReadPos != sif1.fifoWritePos\n");
 	}
 
 //    if(sif1dma->qwc > 0 & (sif1dma->chcr & 0x4) == 0x4) {
diff --git a/pcsx2/windows/pcsx2.rc b/pcsx2/windows/pcsx2.rc
index 79789d198d..e689484091 100644
--- a/pcsx2/windows/pcsx2.rc
+++ b/pcsx2/windows/pcsx2.rc
@@ -1049,7 +1049,7 @@ BEGIN
     CONTROL         "Disable VU Overflow Checks - *Checked = Disables overflow checks. ( Speedup! ) *Greyed = Extra overflow checks. ( Helps SPS, Slow! )",IDC_VU_OVERFLOWHACK,
                     "Button",BS_AUTO3STATE | WS_TABSTOP,15,49,475,10
     CTEXT           "These hacks will affect the speed of PCSX2 but possibly compromise compatibility.",IDC_HACKDESC,7,7,497,8
-    CONTROL         "Tighter SPU2 Sync ( FFXII vids) - Slower, not very useful anymore.",IDC_SOUNDHACK,
+    CONTROL         "Tighter SPU2 Sync (Dawn of Mana FMV) - a bit slower",IDC_SOUNDHACK,
                     "Button",BS_AUTOCHECKBOX | WS_TABSTOP,15,245,421,10
     CONTROL         "IOP Sync Hack (x2) - Doubles the cycle rate of the IOP. ( Speedup but breaks some games. )",IDC_SYNCHACK2,
                     "Button",BS_AUTOCHECKBOX | WS_TABSTOP,15,176,410,10
diff --git a/plugins/spu2ghz/dma.cpp b/plugins/spu2ghz/dma.cpp
index 67273ac0a0..b2b3ecd5ce 100644
--- a/plugins/spu2ghz/dma.cpp
+++ b/plugins/spu2ghz/dma.cpp
@@ -316,7 +316,7 @@ void DoDMAWrite(int core,u16 *pMem,u32 size)
 
 void SPU2readDMA(int core, u16* pMem, u32 size) 
 {
-	if(hasPtr) TimeUpdate(*cPtr,1);
+	if(hasPtr) TimeUpdate(*cPtr);
 
 	u32 i;
 	Cores[core].TSA&=~7;
@@ -342,7 +342,7 @@ void SPU2readDMA(int core, u16* pMem, u32 size)
 
 void SPU2writeDMA(int core, u16* pMem, u32 size) 
 {
-	if(hasPtr) TimeUpdate(*cPtr,1);
+	if(hasPtr) TimeUpdate(*cPtr);
 
 	Cores[core].DMAPtr=pMem;
 
diff --git a/plugins/spu2ghz/spu2.cpp b/plugins/spu2ghz/spu2.cpp
index 094e82a2cb..60907ed915 100644
--- a/plugins/spu2ghz/spu2.cpp
+++ b/plugins/spu2ghz/spu2.cpp
@@ -700,7 +700,7 @@ static DWORD CALLBACK TimeThread(PVOID /* unused param */)
 	return 0;
 }
 
-void __fastcall TimeUpdate(u32 cClocks, u32 syncType)
+void __fastcall TimeUpdate(u32 cClocks)
 {
 	u32 dClocks = cClocks-lClocks;
 
@@ -831,12 +831,12 @@ EXPORT_C_(void) SPU2async(u32 cycles)
 
 	if(hasPtr)
 	{
-		TimeUpdate(*cPtr,0); 
+		TimeUpdate(*cPtr); 
 	}
 	else
 	{
 		pClocks+=cycles;
-		TimeUpdate(pClocks,0);
+		TimeUpdate(pClocks);
 	}
 }
 
@@ -1645,7 +1645,7 @@ EXPORT_C_(void) SPU2write(u32 rmem, u16 value)
 	}
 	else
 	{
-		if(hasPtr) TimeUpdate(*cPtr,0);
+		if(hasPtr) TimeUpdate(*cPtr);
 
 		if (rmem>>16 == 0x1f80)
 			SPU_ps1_write(rmem,value);
@@ -1659,7 +1659,7 @@ EXPORT_C_(u16) SPU2read(u32 rmem)
 //	if(!replay_mode)
 //		s2r_readreg(Cycles,rmem);
 
-	if(hasPtr) TimeUpdate(*cPtr,1);
+	if(hasPtr) TimeUpdate(*cPtr);
 
 	u16 ret=0xDEAD; u32 core=0, mem=rmem&0xFFFF, omem=mem;
 	if (mem & 0x400) { omem^=0x400; core=1; }
diff --git a/plugins/spu2ghz/spu2.h b/plugins/spu2ghz/spu2.h
index a7d6994f8d..839118563d 100644
--- a/plugins/spu2ghz/spu2.h
+++ b/plugins/spu2ghz/spu2.h
@@ -196,7 +196,7 @@ extern bool hasPtr;
 
 extern bool disableFreezes;
 
-void __fastcall TimeUpdate(u32 cClocks, u32 syncType);
+void __fastcall TimeUpdate(u32 cClocks);
 
 void TimestretchUpdate(int bufferusage,int buffersize);