mirror of https://github.com/PCSX2/pcsx2.git
microVU:
- Implemented the case where an Unconditional branch has the E-bit Set. This solves a few games from getting stuck in infinite loops. (I still need to handle conditional branches and jumps). - Max/Mini Opcodes shouldn't set status/mac flags. This should be a minor speedup. - Minor Changes/Cleanups... git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1241 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
cottonvibes
parent
3ff7f2f191
commit
995b9d1eaa
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@ -41,6 +41,15 @@
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} \
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}
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#define branchEbit() { \
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if (branch == 2) { \
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if (!((mVUbranch == 1) || (mVUbranch == 2))) { \
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Console::Error("microVU%d Warning: Jump with E-bit not Implemented [%04x]", params vuIndex, xPC); \
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} \
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else { eBitBranch = 1; } \
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} \
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}
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#define startLoop() { mVUdebug1(); mVUstall = 0; memset(&mVUregsTemp, 0, sizeof(mVUregsTemp)); }
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#define calcCycles(reg, x) { reg = ((reg > x) ? (reg - x) : 0); }
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#define tCycles(dest, src) { dest = aMax(dest, src); }
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@ -163,9 +172,7 @@ microVUt(void) mVUendProgram(int qInst, int pInst, int fStatus, int fMac, int fC
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MOV32RtoM((uptr)&mVU->regs->VI[REG_MAC_FLAG].UL, gprT1);
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MOV32RtoM((uptr)&mVU->regs->VI[REG_CLIP_FLAG].UL, gprT2);
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//memcpy_fast(&pBlock->pStateEnd, &mVUregs, sizeof(microRegInfo));
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//MOV32ItoM((uptr)&mVU->prog.lpState, (int)&mVUblock.pState); // Save pipeline state (clipflag instance)
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//AND32ItoM((uptr)µVU0.regs->VI[REG_VPU_STAT].UL, (vuIndex ? ~0x100 : ~0x001)); // VBS0/VBS1 flag
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// Clear 'is busy' Flags, Save PC, and Jump to Exit Point
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AND32ItoM((uptr)&VU0.VI[REG_VPU_STAT].UL, (vuIndex ? ~0x100 : ~0x001)); // VBS0/VBS1 flag
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AND32ItoM((uptr)&mVU->regs->vifRegs->stat, ~0x4); // Clear VU 'is busy' signal for vif
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MOV32ItoM((uptr)&mVU->regs->VI[REG_TPC].UL, xPC);
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@ -175,7 +182,8 @@ microVUt(void) mVUendProgram(int qInst, int pInst, int fStatus, int fMac, int fC
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#define sI ((mVUpBlock->pState.needExactMatch & 0x000f) ? 0 : ((mVUpBlock->pState.flags >> 0) & 3))
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#define cI ((mVUpBlock->pState.needExactMatch & 0x0f00) ? 0 : ((mVUpBlock->pState.flags >> 2) & 3))
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void mVUwarning() { Console::Error("microVU Warning: Exiting Execution Early (Possible Infinite Loop)"); }
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void __fastcall mVUwarning0(u32 PC) { Console::Error("microVU0 Warning: Exiting from Possible Infinite Loop [%04x]", params PC); }
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void __fastcall mVUwarning1(u32 PC) { Console::Error("microVU1 Warning: Exiting from Possible Infinite Loop [%04x]", params PC); }
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microVUt(void) mVUtestCycles() {
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microVU* mVU = mVUx;
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@ -183,7 +191,9 @@ microVUt(void) mVUtestCycles() {
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CMP32ItoM((uptr)&mVU->cycles, 0);
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u8* jmp8 = JG8(0);
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PUSH32R(gprR);
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CALLFunc((uptr)mVUwarning);
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MOV32ItoR(gprT2, xPC);
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if (!vuIndex) CALLFunc((uptr)mVUwarning0);
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else CALLFunc((uptr)mVUwarning1);
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POP32R(gprR);
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mVUendProgram<vuIndex>(0, 0, sI, 0, cI);
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x86SetJ8(jmp8);
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@ -224,9 +234,10 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) {
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memcpy_fast(&mVUregs, (microRegInfo*)pState, sizeof(microRegInfo)); // Loads up Pipeline State Info
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mVUblock.x86ptrStart = thisPtr;
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pBlock = mVUblocks[startPC/8]->add(&mVUblock); // Add this block to block manager
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mVUpBlock = pBlock;
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mVUregs.flags = 0;
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mVUflagInfo = 0;
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mVUpBlock = pBlock;
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mVUregs.flags = 0;
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mVUflagInfo = 0;
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bool eBitBranch = 0; // E-bit Set on Branch
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for (int branch = 0; mVUcount < (vuIndex ? (0x3fff/8) : (0xfff/8)); ) {
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incPC(1);
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@ -235,7 +246,7 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) {
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startLoop();
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mVUopU<vuIndex, 0>();
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if (curI & _Ebit_) { branch = 1; }
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if (curI & _MDTbit_) { branch = 2; }
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if (curI & _MDTbit_) { branch = 4; }
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if (curI & _Ibit_) { mVUinfo |= _isNOP; }
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else { incPC(-1); mVUopL<vuIndex, 0>(); incPC(1); }
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mVUsetCycles<vuIndex>();
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@ -244,7 +255,7 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) {
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else { mVUinfo |= _writeQ; }
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if (branch >= 2) { mVUinfo |= _isEOB | ((branch == 3) ? _isBdelay : 0); mVUcount++; branchWarning(); break; }
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else if (branch == 1) { branch = 2; }
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if (mVUbranch) { mVUsetFlagInfo<vuIndex>(); branch = 3; mVUbranch = 0; mVUinfo |= _isBranch; }
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if (mVUbranch) { mVUsetFlagInfo<vuIndex>(); branchEbit(); branch = 3; mVUbranch = 0; mVUinfo |= _isBranch; }
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incPC(1);
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mVUcount++;
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}
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@ -253,10 +264,6 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) {
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int xStatus[4], xMac[4], xClip[4];
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int xCycles = mVUsetFlags<vuIndex>(xStatus, xMac, xClip);
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mVUtestCycles<vuIndex>();
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//SysPrintf("bS[0] = %08x, bS[1] = %08x, bS[2] = %08x, bS[3] = %08x\n", bStatus[0], bStatus[1], bStatus[2], bStatus[3]);
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//SysPrintf("bM[0] = %08x, bM[1] = %08x, bM[2] = %08x, bM[3] = %08x\n", bMac[0], bMac[1], bMac[2], bMac[3]);
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//SysPrintf("mVUcount = %d\n", mVUcount);
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//SysPrintf("mVUflagInfo = %d\n", mVUflagInfo);
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// Second Pass
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iPC = mVUstartPC;
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@ -286,6 +293,8 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) {
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mVUprint("mVUcompile B/BAL");
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incPC(-3); // Go back to branch opcode (to get branch imm addr)
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if (eBitBranch) { iPC = branchAddr/4; goto eBitTemination; } // E-bit Was Set on Branch
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mVUsetupBranch<vuIndex>(xStatus, xMac, xClip, xCycles);
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if (mVUblocks[branchAddr/8] == NULL)
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@ -347,10 +356,11 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) {
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return thisPtr;
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}
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}
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mVUprint("mVUcompile ebit");
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if (x == (vuIndex?(0x3fff/8):(0xfff/8))) { Console::Error("microVU%d: Possible infinite compiling loop!", params vuIndex); }
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eBitTemination:
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mVUprint("mVUcompile ebit");
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incCycles(100); // Ensures Valid P/Q instances (And sets all cycle data to 0)
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mVUcycles -= 100;
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@ -358,7 +368,7 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) {
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mVUsetupRange<vuIndex>(xPC - 8);
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mVUendProgram<vuIndex>(mVU->q, mVU->p, findFlagInst(xStatus, 0x7fffffff), findFlagInst(xMac, 0x7fffffff), findFlagInst(xClip, 0x7fffffff));
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return thisPtr; //ToDo: Save pipeline state?
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return thisPtr;
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}
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void* __fastcall mVUcompileVU0(u32 startPC, uptr pState) { return mVUcompile<0>(startPC, pState); }
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@ -23,8 +23,6 @@
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// Dispatcher Functions
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//------------------------------------------------------------------
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void testFunction() { mVUprint("microVU: Entered Execution Mode"); }
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// Generates the code for entering recompiled blocks
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microVUt(void) mVUdispatcherA() {
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microVU* mVU = mVUx;
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@ -70,11 +68,6 @@ microVUt(void) mVUdispatcherA() {
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if (isMMX(i)) { MOVQMtoR(mmVI(i), (uptr)&mVU->regs->VI[i].UL); }
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}
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//PUSH32R(EAX);
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//CALLFunc((uptr)testFunction);
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//write8(0xcc);
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//POP32R(EAX);
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// Jump to Recompiled Code Block
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JMPR(EAX);
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}
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@ -202,7 +202,7 @@ microVUt(void) mVUpass4(int startPC) {
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if (mVUbranch) { branch = 3; mVUbranch = 0; }
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incPC(1);
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}
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//if (mVUcount == 4) { mVUflagInfo |= 0xfff; } // Is this Too Slow? 99% of games probably don't need this.
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//if (mVUcount < 4) { mVUflagInfo |= 0xfff; } // Is this Too Slow? 99% of games probably don't need this.
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iPC = oldPC;
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mVUcount = oldCount;
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mVUbranch = oldBranch;
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@ -590,8 +590,8 @@ microVUf(void) mVU_FSSET() {
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int flagReg1, flagReg2;
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getFlagReg(flagReg1, fsInstance);
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if (!(doStatus||doDivFlag)) { getFlagReg(flagReg2, fpsInstance); MOV32RtoR(flagReg1, flagReg2); } // Get status result from last status setting instruction
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AND16ItoR(flagReg1, 0x03f); // Remember not to modify upper 16 bits because of mac flag
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OR16ItoR (flagReg1, (_Imm12_ & 0xfc0));
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AND32ItoR(flagReg1, 0x03f);
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OR32ItoR (flagReg1, (_Imm12_ & 0xfc0));
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}
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pass3 { mVUlog("FSSET $%x", _Imm12_); }
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pass4 { mVUsFlagHack = 0; }
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@ -461,6 +461,11 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
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pass3 { mVUlog(OPname); mVUlogACC(); mVUlogQ(); } \
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}
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// FMAC27~29 - MAX/MINI FMAC Opcodes
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#define mVU_FMAC27(operation, OPname) { mVU_FMAC1 (operation, OPname); pass1 { microVU* mVU = mVUx; mVUinfo &= ~_doStatus; } }
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#define mVU_FMAC28(operation, OPname) { mVU_FMAC6 (operation, OPname); pass1 { microVU* mVU = mVUx; mVUinfo &= ~_doStatus; } }
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#define mVU_FMAC29(operation, OPname) { mVU_FMAC3 (operation, OPname); pass1 { microVU* mVU = mVUx; mVUinfo &= ~_doStatus; } }
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//------------------------------------------------------------------
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// Micro VU Micromode Upper instructions
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//------------------------------------------------------------------
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@ -546,21 +551,21 @@ microVUf(void) mVU_MSUBAx() { mVU_FMAC15(SUB, "MSUBAx"); }
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microVUf(void) mVU_MSUBAy() { mVU_FMAC15(SUB, "MSUBAy"); }
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microVUf(void) mVU_MSUBAz() { mVU_FMAC15(SUB, "MSUBAz"); }
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microVUf(void) mVU_MSUBAw() { mVU_FMAC15(SUB, "MSUBAw"); }
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microVUf(void) mVU_MAX() { mVU_FMAC1 (MAX2, "MAX"); }
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microVUf(void) mVU_MAXi() { mVU_FMAC6 (MAX2, "MAXi"); }
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microVUf(void) mVU_MAXx() { mVU_FMAC3 (MAX2, "MAXx"); }
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microVUf(void) mVU_MAXy() { mVU_FMAC3 (MAX2, "MAXy"); }
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microVUf(void) mVU_MAXz() { mVU_FMAC3 (MAX2, "MAXz"); }
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microVUf(void) mVU_MAXw() { mVU_FMAC3 (MAX2, "MAXw"); }
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microVUf(void) mVU_MINI() { mVU_FMAC1 (MIN2, "MINI"); }
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microVUf(void) mVU_MINIi() { mVU_FMAC6 (MIN2, "MINIi"); }
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microVUf(void) mVU_MINIx() { mVU_FMAC3 (MIN2, "MINIx"); }
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microVUf(void) mVU_MINIy() { mVU_FMAC3 (MIN2, "MINIy"); }
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microVUf(void) mVU_MINIz() { mVU_FMAC3 (MIN2, "MINIz"); }
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microVUf(void) mVU_MINIw() { mVU_FMAC3 (MIN2, "MINIw"); }
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microVUf(void) mVU_MAX() { mVU_FMAC27(MAX2, "MAX"); }
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microVUf(void) mVU_MAXi() { mVU_FMAC28(MAX2, "MAXi"); }
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microVUf(void) mVU_MAXx() { mVU_FMAC29(MAX2, "MAXx"); }
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microVUf(void) mVU_MAXy() { mVU_FMAC29(MAX2, "MAXy"); }
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microVUf(void) mVU_MAXz() { mVU_FMAC29(MAX2, "MAXz"); }
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microVUf(void) mVU_MAXw() { mVU_FMAC29(MAX2, "MAXw"); }
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microVUf(void) mVU_MINI() { mVU_FMAC27(MIN2, "MINI"); }
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microVUf(void) mVU_MINIi() { mVU_FMAC28(MIN2, "MINIi"); }
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microVUf(void) mVU_MINIx() { mVU_FMAC29(MIN2, "MINIx"); }
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microVUf(void) mVU_MINIy() { mVU_FMAC29(MIN2, "MINIy"); }
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microVUf(void) mVU_MINIz() { mVU_FMAC29(MIN2, "MINIz"); }
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microVUf(void) mVU_MINIw() { mVU_FMAC29(MIN2, "MINIw"); }
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microVUf(void) mVU_OPMULA() { mVU_FMAC18(MUL, "OPMULA"); }
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microVUf(void) mVU_OPMSUB() { mVU_FMAC19(SUB, "OPMSUB"); }
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microVUf(void) mVU_NOP() { pass3 { mVUlog("NOP"); } }
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microVUf(void) mVU_NOP() { pass3 { mVUlog("NOP"); } }
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microVUq(void) mVU_FTOIx(uptr addr) {
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microVU* mVU = mVUx;
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pass1 { mVUanalyzeFMAC2<vuIndex>(_Fs_, _Ft_); }
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