mirror of https://github.com/PCSX2/pcsx2.git
microVU:
- More regalloc work/fixes - Implemented some untested SSE4.1 optimizations (can't test since don't have sse4.1 cpu) pcsx2: - Added an SSE4 instruction to the legacy emitter (just a wrapper to the new emitter function). Note: Currently tri-ace fix and logical min-max code (thing that mad DaZ safe to use) is broken with mVU. Will fix later. git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1547 96395faa-99c1-11dd-bbfe-3dabce05a288
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@ -1349,6 +1349,7 @@ extern void SSE4_DPPS_XMM_to_XMM(x86SSERegType to, x86SSERegType from, u8 imm8);
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extern void SSE4_DPPS_M128_to_XMM(x86SSERegType to, uptr from, u8 imm8);
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extern void SSE4_INSERTPS_XMM_to_XMM(x86SSERegType to, x86SSERegType from, u8 imm8);
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extern void SSE4_EXTRACTPS_XMM_to_R32(x86IntRegType to, x86SSERegType from, u8 imm8);
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extern void SSE4_EXTRACTPS_XMM_to_M32(uptr to, x86SSERegType from, u8 imm8);
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extern void SSE4_BLENDPS_XMM_to_XMM(x86SSERegType to, x86SSERegType from, u8 imm8);
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extern void SSE4_BLENDVPS_XMM_to_XMM(x86SSERegType to, x86SSERegType from);
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extern void SSE4_BLENDVPS_M128_to_XMM(x86SSERegType to, uptr from);
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@ -364,6 +364,7 @@ emitterT void SSE4_PINSRD_R32_to_XMM(x86SSERegType to, x86IntRegType from, u8 im
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emitterT void SSE4_INSERTPS_XMM_to_XMM(x86SSERegType to, x86SSERegType from, u8 imm8) { xINSERTPS( xRegisterSSE(to), xRegisterSSE(from), imm8 ); }
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emitterT void SSE4_EXTRACTPS_XMM_to_R32(x86IntRegType to, x86SSERegType from, u8 imm8) { xEXTRACTPS( xRegister32(to), xRegisterSSE(from), imm8 ); }
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emitterT void SSE4_EXTRACTPS_XMM_to_M32(uptr to, x86SSERegType from, u8 imm8) { xEXTRACTPS( (u32*)to, xRegisterSSE(from), imm8 ); }
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emitterT void SSE4_DPPS_XMM_to_XMM(x86SSERegType to, x86SSERegType from, u8 imm8) { xDP.PS( xRegisterSSE(to), xRegisterSSE(from), imm8 ); }
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emitterT void SSE4_DPPS_M128_to_XMM(x86SSERegType to, uptr from, u8 imm8) { xDP.PS( xRegisterSSE(to), (void*)from, imm8 ); }
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@ -161,6 +161,7 @@ struct microIR {
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// Reg Alloc
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//------------------------------------------------------------------
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void mVUmergeRegs(int dest, int src, int xyzw, bool modXYZW);
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void mVUsaveReg(int reg, uptr offset, int xyzw, bool modXYZW);
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void mVUloadReg(int reg, uptr offset, int xyzw);
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@ -223,7 +224,7 @@ public:
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}
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void writeBackReg(int reg) {
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if ((xmmReg[reg].reg > 0) && xmmReg[reg].xyzw) { // Reg was modified and not Temp or vf0
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if (xmmReg[reg].reg == 32) SSE_MOVAPS_XMM_to_M128((uptr)&vuRegs->ACC.UL[0], reg);
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if (xmmReg[reg].reg == 32) mVUsaveReg(reg, (uptr)&vuRegs->ACC.UL[0], xmmReg[reg].xyzw, 1);
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else mVUsaveReg(reg, (uptr)&vuRegs->VF[xmmReg[reg].reg].UL[0], xmmReg[reg].xyzw, 1);
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for (int i = 0; i < xmmTotal; i++) {
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if (i == reg) continue;
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@ -241,20 +242,26 @@ public:
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clearReg(reg); // Clear Reg
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}
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void clearNeeded(int reg) {
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// ToDo: Merge Regs Support
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xmmReg[reg].isNeeded = 0;
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if (xmmReg[reg].xyzw) { // Reg was modified
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if (xmmReg[reg].reg > 0) {
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if (xmmReg[reg].xyzw < 0xf) writeBackReg(reg); // Always Write Back Partial Writes
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if (xmmReg[reg].reg > 0) {
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int mergeRegs = 0;
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if (xmmReg[reg].xyzw < 0xf) { mergeRegs = 1; } // Try to merge partial writes
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for (int i = 0; i < xmmTotal; i++) { // Invalidate any other read-only regs of same vfReg
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if (i == reg) continue;
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if (xmmReg[i].reg == xmmReg[reg].reg) {
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if (xmmReg[i].xyzw && xmmReg[i].xyzw < 0xf) DevCon::Error("microVU Error: clearNeeded()");
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clearReg(i);
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}
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if (xmmReg[i].xyzw && xmmReg[i].xyzw < 0xf) DevCon::Error("microVU Error: clearNeeded() [%d]", params xmmReg[i].reg);
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if (mergeRegs == 1) {
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mVUmergeRegs(i, reg, xmmReg[reg].xyzw, 1);
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xmmReg[i].xyzw = 0xf;
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xmmReg[i].count = counter;
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mergeRegs = 2;
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}
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else clearReg(i);
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}
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}
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if (mergeRegs == 2) clearReg(reg); // Clear Current Reg if Merged
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else if (mergeRegs) writeBackReg(reg); // Write Back Partial Writes if couldn't merge
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}
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else clearReg(reg); // If Reg was temp or vf0, then invalidate itself
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}
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@ -296,7 +303,8 @@ public:
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writeBackReg(x);
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if (vfWriteReg >= 0) { // Reg Will Be Modified (allow partial reg loading)
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if (vfLoadReg == 32) mVUloadReg(x, (uptr)&vuRegs->ACC.UL[0], xyzw);
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if ((vfLoadReg == 0) && !(xyzw & 1)) { SSE2_PXOR_XMM_to_XMM(x, x); }
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else if (vfLoadReg == 32) mVUloadReg(x, (uptr)&vuRegs->ACC.UL[0], xyzw);
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else if (vfLoadReg >= 0) mVUloadReg(x, (uptr)&vuRegs->VF[vfLoadReg].UL[0], xyzw);
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xmmReg[x].reg = vfWriteReg;
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xmmReg[x].xyzw = xyzw;
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@ -104,10 +104,16 @@ void mVUsaveReg(int reg, uptr offset, int xyzw, bool modXYZW) {
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return;*/
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switch ( xyzw ) {
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case 5: SSE2_PSHUFD_XMM_to_XMM(reg, reg, 0xe1); //WZXY
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case 5: if (cpucaps.hasStreamingSIMD4Extensions) {
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SSE4_EXTRACTPS_XMM_to_M32(offset+4, reg, 1);
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SSE4_EXTRACTPS_XMM_to_M32(offset+12, reg, 3);
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}
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else {
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SSE2_PSHUFD_XMM_to_XMM(reg, reg, 0xe1); //WZXY
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SSE_MOVSS_XMM_to_M32(offset+4, reg);
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SSE2_PSHUFD_XMM_to_XMM(reg, reg, 0xff); //WWWW
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SSE_MOVSS_XMM_to_M32(offset+12, reg);
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}
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break; // YW
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case 6: SSE2_PSHUFD_XMM_to_XMM(reg, reg, 0xc9);
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SSE_MOVLPS_XMM_to_M64(offset+4, reg);
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@ -203,25 +209,33 @@ void mVUsaveReg2(int reg, int gprReg, u32 offset, int xyzw) {
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}
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}
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// Modifies the Source Reg!
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void mVUmergeRegs(int dest, int src, int xyzw) {
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// Modifies the Source Reg! (ToDo: Optimize modXYZW = 1 cases)
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void mVUmergeRegs(int dest, int src, int xyzw, bool modXYZW = 0) {
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xyzw &= 0xf;
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if ( (dest != src) && (xyzw != 0) ) {
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if (cpucaps.hasStreamingSIMD4Extensions && (xyzw != 0x8) && (xyzw != 0xf)) {
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if (modXYZW) {
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if (xyzw == 1) { SSE4_INSERTPS_XMM_to_XMM(dest, src, _MM_MK_INSERTPS_NDX(0, 3, 0)); return; }
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else if (xyzw == 2) { SSE4_INSERTPS_XMM_to_XMM(dest, src, _MM_MK_INSERTPS_NDX(0, 2, 0)); return; }
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else if (xyzw == 4) { SSE4_INSERTPS_XMM_to_XMM(dest, src, _MM_MK_INSERTPS_NDX(0, 1, 0)); return; }
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}
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xyzw = ((xyzw & 1) << 3) | ((xyzw & 2) << 1) | ((xyzw & 4) >> 1) | ((xyzw & 8) >> 3);
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SSE4_BLENDPS_XMM_to_XMM(dest, src, xyzw);
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}
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else {
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switch (xyzw) {
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case 1: SSE_MOVHLPS_XMM_to_XMM(src, dest);
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SSE_SHUFPS_XMM_to_XMM(dest, src, 0xc4);
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case 1: if (modXYZW) mVUunpack_xyzw(src, src, 0);
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SSE_MOVHLPS_XMM_to_XMM(src, dest); // src = Sw Sz Dw Dz
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SSE_SHUFPS_XMM_to_XMM(dest, src, 0xc4); // 11 00 01 00
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break;
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case 2: SSE_MOVHLPS_XMM_to_XMM(src, dest);
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case 2: if (modXYZW) mVUunpack_xyzw(src, src, 0);
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SSE_MOVHLPS_XMM_to_XMM(src, dest);
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SSE_SHUFPS_XMM_to_XMM(dest, src, 0x64);
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break;
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case 3: SSE_SHUFPS_XMM_to_XMM(dest, src, 0xe4);
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break;
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case 4: SSE_MOVSS_XMM_to_XMM(src, dest);
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case 4: if (modXYZW) mVUunpack_xyzw(src, src, 0);
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SSE_MOVSS_XMM_to_XMM(src, dest);
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SSE2_MOVSD_XMM_to_XMM(dest, src);
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break;
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case 5: SSE_SHUFPS_XMM_to_XMM(dest, src, 0xd8);
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@ -106,12 +106,21 @@ void mVU_printOP(microVU* mVU, int opCase, char* opName, bool isACC) {
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opCase4 { if (isACC) { mVUlogACC(); } else { mVUlogFd(); } mVUlogQ(); }
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}
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// Sets Up Pass1 Info for Normal, BC, I, and Q Cases
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void setupPass1(microVU* mVU, int opCase, bool isACC, bool noFlagUpdate) {
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opCase1 { mVUanalyzeFMAC1(mVU, ((isACC) ? 0 : _Fd_), _Fs_, _Ft_); }
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opCase2 { mVUanalyzeFMAC3(mVU, ((isACC) ? 0 : _Fd_), _Fs_, _Ft_); }
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opCase3 { mVUanalyzeFMAC1(mVU, ((isACC) ? 0 : _Fd_), _Fs_, 0); }
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opCase4 { mVUanalyzeFMAC1(mVU, ((isACC) ? 0 : _Fd_), _Fs_, 0); }
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if (noFlagUpdate) { sFLAG.doFlag = 0; }
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}
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// Sets Up Ft Reg for Normal, BC, I, and Q Cases
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void setupFtReg(microVU* mVU, int& Ft, int opCase) {
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opCase1 { Ft = mVU->regAlloc->allocReg(_Ft_); }
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opCase2 {
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if (!_XYZW_SS) {
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Ft = mVU->regAlloc->allocReg(_Ft_, 0, _X_Y_Z_W);
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Ft = mVU->regAlloc->allocReg(_Ft_, 0, 0xf);
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mVUunpack_xyzw(Ft, Ft, _bc_);
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}
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else Ft = mVU->regAlloc->allocReg(_Ft_);
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@ -122,13 +131,7 @@ void setupFtReg(microVU* mVU, int& Ft, int opCase) {
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// Normal FMAC Opcodes
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void mVU_FMACa(microVU* mVU, int recPass, int opCase, int opType, bool isACC, char* opName) {
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pass1 {
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opCase1 { mVUanalyzeFMAC1(mVU, ((isACC) ? 0 : _Fd_), _Fs_, _Ft_); }
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opCase2 { mVUanalyzeFMAC3(mVU, ((isACC) ? 0 : _Fd_), _Fs_, _Ft_); }
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opCase3 { mVUanalyzeFMAC1(mVU, ((isACC) ? 0 : _Fd_), _Fs_, 0); }
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opCase4 { mVUanalyzeFMAC1(mVU, ((isACC) ? 0 : _Fd_), _Fs_, 0); }
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if ((opType == 3) || (opType == 4)) { sFLAG.doFlag = 0; }
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}
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pass1 { setupPass1(mVU, opCase, isACC, ((opType == 3) || (opType == 4))); }
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pass2 {
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int Fs, Ft, ACC;
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mVU->regAlloc->reset(); // Reset for Testing
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// MADDA/MSUBA Opcodes
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void mVU_FMACb(microVU* mVU, int recPass, int opCase, int opType, char* opName) {
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pass1 {
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opCase1 { mVUanalyzeFMAC1(mVU, 0, _Fs_, _Ft_); }
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opCase2 { mVUanalyzeFMAC3(mVU, 0, _Fs_, _Ft_); }
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opCase3 { mVUanalyzeFMAC1(mVU, 0, _Fs_, 0); }
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opCase4 { mVUanalyzeFMAC1(mVU, 0, _Fs_, 0); }
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}
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pass1 { setupPass1(mVU, opCase, 1, 0); }
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pass2 {
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int Fs, Ft, ACC;
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mVU->regAlloc->reset(); // Reset for Testing
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@ -218,12 +216,7 @@ void mVU_FMACb(microVU* mVU, int recPass, int opCase, int opType, char* opName)
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// MADD Opcodes
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void mVU_FMACc(microVU* mVU, int recPass, int opCase, char* opName) {
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pass1 {
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opCase1 { mVUanalyzeFMAC1(mVU, _Fd_, _Fs_, _Ft_); }
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opCase2 { mVUanalyzeFMAC3(mVU, _Fd_, _Fs_, _Ft_); }
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opCase3 { mVUanalyzeFMAC1(mVU, _Fd_, _Fs_, 0); }
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opCase4 { mVUanalyzeFMAC1(mVU, _Fd_, _Fs_, 0); }
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}
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pass1 { setupPass1(mVU, opCase, 0, 0); }
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pass2 {
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int Fs, Ft, ACC;
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mVU->regAlloc->reset(); // Reset for Testing
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// MSUB Opcodes
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void mVU_FMACd(microVU* mVU, int recPass, int opCase, char* opName) {
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pass1 {
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opCase1 { mVUanalyzeFMAC1(mVU, _Fd_, _Fs_, _Ft_); }
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opCase2 { mVUanalyzeFMAC3(mVU, _Fd_, _Fs_, _Ft_); }
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opCase3 { mVUanalyzeFMAC1(mVU, _Fd_, _Fs_, 0); }
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opCase4 { mVUanalyzeFMAC1(mVU, _Fd_, _Fs_, 0); }
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}
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pass1 { setupPass1(mVU, opCase, 0, 0); }
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pass2 {
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int Fs, Ft, Fd;
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mVU->regAlloc->reset(); // Reset for Testing
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