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SPU2: Don't make end IRQ positions inclusive

This commit is contained in:
refractionpcsx2 2023-04-13 23:47:32 +01:00
parent 79705a2514
commit 988b1ad03b
1 changed files with 6 additions and 7 deletions
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13
pcsx2/SPU2/Dma.cpp
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@ -258,7 +258,6 @@ void V_Core::FinishDMAwrite()
#endif #endif
u32 buff1end = ActiveTSA + std::min(ReadSize, (u32)0x100 + std::abs(DMAICounter / 4)); u32 buff1end = ActiveTSA + std::min(ReadSize, (u32)0x100 + std::abs(DMAICounter / 4));
u32 start = ActiveTSA;
u32 buff2end = 0; u32 buff2end = 0;
if (buff1end > 0x100000) if (buff1end > 0x100000)
{ {
@ -298,6 +297,7 @@ void V_Core::FinishDMAwrite()
// memory below 0x2800 (registers and such) // memory below 0x2800 (registers and such)
//const u32 endpt2 = (buff2end + roundUp) / indexer_scalar; //const u32 endpt2 = (buff2end + roundUp) / indexer_scalar;
//memset( pcm_cache_flags, 0, endpt2 ); //memset( pcm_cache_flags, 0, endpt2 );
const u32 start = ActiveTSA;
TDA = buff1end; TDA = buff1end;
DMAPtr += TDA - ActiveTSA; DMAPtr += TDA - ActiveTSA;
@ -323,7 +323,7 @@ void V_Core::FinishDMAwrite()
// understanding would trigger the interrupt early causing it to switch buffers again immediately // understanding would trigger the interrupt early causing it to switch buffers again immediately
// and an interrupt never fires again, leaving the voices looping the same samples forever. // and an interrupt never fires again, leaving the voices looping the same samples forever.
if (Cores[i].IRQEnable && (Cores[i].IRQA > start || Cores[i].IRQA <= TDA)) if (Cores[i].IRQEnable && (Cores[i].IRQA > start || Cores[i].IRQA < TDA))
{ {
//ConLog("DMAwrite Core %d: IRQ Called (IRQ passed). IRQA = %x Cycles = %d\n", i, Cores[i].IRQA, Cycles ); //ConLog("DMAwrite Core %d: IRQ Called (IRQ passed). IRQA = %x Cycles = %d\n", i, Cores[i].IRQA, Cycles );
SetIrqCallDMA(i); SetIrqCallDMA(i);
@ -341,7 +341,7 @@ void V_Core::FinishDMAwrite()
// Important: Test both core IRQ settings for either DMA! // Important: Test both core IRQ settings for either DMA!
for (int i = 0; i < 2; i++) for (int i = 0; i < 2; i++)
{ {
if (Cores[i].IRQEnable && (Cores[i].IRQA > ActiveTSA && Cores[i].IRQA <= TDA)) if (Cores[i].IRQEnable && (Cores[i].IRQA > ActiveTSA && Cores[i].IRQA < TDA))
{ {
//ConLog("DMAwrite Core %d: IRQ Called (IRQ passed). IRQA = %x Cycles = %d\n", i, Cores[i].IRQA, Cycles ); //ConLog("DMAwrite Core %d: IRQ Called (IRQ passed). IRQA = %x Cycles = %d\n", i, Cores[i].IRQA, Cycles );
SetIrqCallDMA(i); SetIrqCallDMA(i);
@ -373,7 +373,6 @@ void V_Core::FinishDMAwrite()
void V_Core::FinishDMAread() void V_Core::FinishDMAread()
{ {
u32 buff1end = ActiveTSA + std::min(ReadSize, (u32)0x100 + std::abs(DMAICounter / 4)); u32 buff1end = ActiveTSA + std::min(ReadSize, (u32)0x100 + std::abs(DMAICounter / 4));
u32 start = ActiveTSA;
u32 buff2end = 0; u32 buff2end = 0;
if (buff1end > 0x100000) if (buff1end > 0x100000)
@ -396,7 +395,7 @@ void V_Core::FinishDMAread()
if (buff2end > 0) if (buff2end > 0)
{ {
const u32 start = ActiveTSA;
TDA = buff1end; TDA = buff1end;
DMARPtr += TDA - ActiveTSA; DMARPtr += TDA - ActiveTSA;
@ -415,7 +414,7 @@ void V_Core::FinishDMAread()
for (int i = 0; i < 2; i++) for (int i = 0; i < 2; i++)
{ {
if (Cores[i].IRQEnable && (Cores[i].IRQA > start || Cores[i].IRQA <= TDA)) if (Cores[i].IRQEnable && (Cores[i].IRQA > start || Cores[i].IRQA < TDA))
{ {
SetIrqCallDMA(i); SetIrqCallDMA(i);
} }
@ -433,7 +432,7 @@ void V_Core::FinishDMAread()
for (int i = 0; i < 2; i++) for (int i = 0; i < 2; i++)
{ {
if (Cores[i].IRQEnable && (Cores[i].IRQA > ActiveTSA && Cores[i].IRQA <= TDA)) if (Cores[i].IRQEnable && (Cores[i].IRQA > ActiveTSA && Cores[i].IRQA < TDA))
{ {
SetIrqCallDMA(i); SetIrqCallDMA(i);
} }