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Extremely insignificant optimization applied to recADD/ADDI instructions (omg it might save a cpu cycle per minutes or something!) 

Also: Reverted the addition of the ImplementationHelper<> class, since it failed miserably under GCC. -_-

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@998 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
Jake.Stine 2009-04-17 01:54:35 +00:00
parent 8865ee398b
commit 986683323e
10 changed files with 135 additions and 94 deletions
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15
pcsx2/x86/ix86-32/iR5900Arit.cpp
View File

@ -116,9 +116,18 @@ void recADD_constv(int info, int creg, int vreg)
}
else {
if( _Rd_ == vreg ) {
ADD32ItoM((int)&cpuRegs.GPR.r[_Rd_].UL[ 0 ], g_cpuConstRegs[creg].UL[0]);
if( EEINST_ISLIVE1(_Rd_) ) _signExtendSFtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ]);
else EEINST_RESETHASLIVE1(_Rd_);
if( EEINST_ISLIVE1(_Rd_) )
{
// must perform the ADD unconditionally, to maintain flags status:
ADD32ItoM((int)&cpuRegs.GPR.r[_Rd_].UL[ 0 ], g_cpuConstRegs[creg].UL[0]);
_signExtendSFtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ]);
}
else
{
if( g_cpuConstRegs[creg].UL[0] )
ADD32ItoM((int)&cpuRegs.GPR.r[_Rd_].UL[ 0 ], g_cpuConstRegs[creg].UL[0]);
EEINST_RESETHASLIVE1(_Rd_);
}
}
else {
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ vreg ].UL[ 0 ] );

14
pcsx2/x86/ix86-32/iR5900AritImm.cpp
View File

@ -111,9 +111,17 @@ void recADDI_(int info)
}
else {
if ( _Rt_ == _Rs_ ) {
ADD32ItoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], _Imm_);
if ( EEINST_ISLIVE1(_Rt_) ) _signExtendSFtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ]);
else EEINST_RESETHASLIVE1(_Rt_);
if ( EEINST_ISLIVE1(_Rt_) )
{
// must perform the ADD unconditionally, to maintain flags status:
ADD32ItoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], _Imm_);
_signExtendSFtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ]);
}
else
{
if( _Imm_ ) ADD32ItoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], _Imm_);
EEINST_RESETHASLIVE1(_Rt_);
}
}
else {
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );

13
pcsx2/x86/ix86/implement/dwshift.h
View File

@ -27,12 +27,17 @@
// because shifts by 0 do *not* affect flags status.
template< typename ImmType, bool isShiftRight >
class DwordShiftImpl : public ImplementationHelper< ImmType >
class DwordShiftImpl
{
protected:
static const uint OperandSize = sizeof(ImmType);
static bool Is8BitOperand() { return OperandSize == 1; }
static void prefix16() { if( OperandSize == 2 ) iWrite<u8>( 0x66 ); }
static void basesibform( bool isCL )
{
ImplementationHelper<ImmType>::prefix16();
prefix16();
write8( 0x0f );
write8( (isCL ? 0xa5 : 0xa4) | (isShiftRight ? 0x8 : 0) );
}
@ -42,7 +47,7 @@ public:
static __emitinline void Emit( const iRegister<ImmType>& to, const iRegister<ImmType>& from )
{
ImplementationHelper<ImmType>::prefix16();
prefix16();
write16( 0xa50f | (isShiftRight ? 0x800 : 0) );
ModRM_Direct( from.Id, to.Id );
}
@ -50,7 +55,7 @@ public:
static __emitinline void Emit( const iRegister<ImmType>& to, const iRegister<ImmType>& from, u8 imm )
{
if( imm == 0 ) return;
ImplementationHelper<ImmType>::prefix16();
prefix16();
write16( 0xa40f | (isShiftRight ? 0x800 : 0) );
ModRM_Direct( from.Id, to.Id );
write8( imm );

40
pcsx2/x86/ix86/implement/group1.h
View File

@ -35,50 +35,56 @@ enum G1Type
// -------------------------------------------------------------------
template< G1Type InstType, typename ImmType >
class Group1Impl : public ImplementationHelper< ImmType >
class Group1Impl
{
protected:
static const uint OperandSize = sizeof(ImmType);
static bool Is8BitOperand() { return OperandSize == 1; }
static void prefix16() { if( OperandSize == 2 ) iWrite<u8>( 0x66 ); }
public:
Group1Impl() {} // because GCC doesn't like static classes
static __emitinline void Emit( const iRegister<ImmType>& to, const iRegister<ImmType>& from )
{
ImplementationHelper<ImmType>::prefix16();
iWrite<u8>( (ImplementationHelper<ImmType>::Is8BitOperand() ? 0 : 1) | (InstType<<3) );
prefix16();
iWrite<u8>( (Is8BitOperand() ? 0 : 1) | (InstType<<3) );
ModRM_Direct( from.Id, to.Id );
}
static __emitinline void Emit( const ModSibBase& sibdest, const iRegister<ImmType>& from )
{
ImplementationHelper<ImmType>::prefix16();
iWrite<u8>( (ImplementationHelper<ImmType>::Is8BitOperand() ? 0 : 1) | (InstType<<3) );
prefix16();
iWrite<u8>( (Is8BitOperand() ? 0 : 1) | (InstType<<3) );
EmitSibMagic( from.Id, sibdest );
}
static __emitinline void Emit( const iRegister<ImmType>& to, const ModSibBase& sibsrc )
{
ImplementationHelper<ImmType>::prefix16();
iWrite<u8>( (ImplementationHelper<ImmType>::Is8BitOperand() ? 2 : 3) | (InstType<<3) );
prefix16();
iWrite<u8>( (Is8BitOperand() ? 2 : 3) | (InstType<<3) );
EmitSibMagic( to.Id, sibsrc );
}
static __emitinline void Emit( void* dest, const iRegister<ImmType>& from )
{
ImplementationHelper<ImmType>::prefix16();
iWrite<u8>( (ImplementationHelper<ImmType>::Is8BitOperand() ? 0 : 1) | (InstType<<3) );
prefix16();
iWrite<u8>( (Is8BitOperand() ? 0 : 1) | (InstType<<3) );
iWriteDisp( from.Id, dest );
}
static __emitinline void Emit( const iRegister<ImmType>& to, const void* src )
{
ImplementationHelper<ImmType>::prefix16();
iWrite<u8>( (ImplementationHelper<ImmType>::Is8BitOperand() ? 2 : 3) | (InstType<<3) );
prefix16();
iWrite<u8>( (Is8BitOperand() ? 2 : 3) | (InstType<<3) );
iWriteDisp( to.Id, src );
}
static __emitinline void Emit( const iRegister<ImmType>& to, int imm )
{
ImplementationHelper<ImmType>::prefix16();
if( !ImplementationHelper<ImmType>::Is8BitOperand() && is_s8( imm ) )
prefix16();
if( !Is8BitOperand() && is_s8( imm ) )
{
iWrite<u8>( 0x83 );
ModRM_Direct( InstType, to.Id );
@ -87,10 +93,10 @@ public:
else
{
if( to.IsAccumulator() )
iWrite<u8>( (ImplementationHelper<ImmType>::Is8BitOperand() ? 4 : 5) | (InstType<<3) );
iWrite<u8>( (Is8BitOperand() ? 4 : 5) | (InstType<<3) );
else
{
iWrite<u8>( ImplementationHelper<ImmType>::Is8BitOperand() ? 0x80 : 0x81 );
iWrite<u8>( Is8BitOperand() ? 0x80 : 0x81 );
ModRM_Direct( InstType, to.Id );
}
iWrite<ImmType>( imm );
@ -99,7 +105,7 @@ public:
static __emitinline void Emit( const ModSibStrict<ImmType>& sibdest, int imm )
{
if( ImplementationHelper<ImmType>::Is8BitOperand() )
if( Is8BitOperand() )
{
iWrite<u8>( 0x80 );
EmitSibMagic( InstType, sibdest );
@ -107,7 +113,7 @@ public:
}
else
{
ImplementationHelper<ImmType>::prefix16();
prefix16();
iWrite<u8>( is_s8( imm ) ? 0x83 : 0x81 );
EmitSibMagic( InstType, sibdest );
if( is_s8( imm ) )

28
pcsx2/x86/ix86/implement/group2.h
View File

@ -39,15 +39,21 @@ enum G2Type
// This is a safe optimization since any zero-value shift does not affect any flags.
//
template< G2Type InstType, typename ImmType >
class Group2Impl : public ImplementationHelper< ImmType >
class Group2Impl
{
protected:
static const uint OperandSize = sizeof(ImmType);
static bool Is8BitOperand() { return OperandSize == 1; }
static void prefix16() { if( OperandSize == 2 ) iWrite<u8>( 0x66 ); }
public:
Group2Impl() {} // For the love of GCC.
static __emitinline void Emit( const iRegister<ImmType>& to )
{
ImplementationHelper<ImmType>::prefix16();
iWrite<u8>( ImplementationHelper<ImmType>::Is8BitOperand() ? 0xd2 : 0xd3 );
prefix16();
iWrite<u8>( Is8BitOperand() ? 0xd2 : 0xd3 );
ModRM_Direct( InstType, to.Id );
}
@ -55,16 +61,16 @@ public:
{
if( imm == 0 ) return;
ImplementationHelper<ImmType>::prefix16();
prefix16();
if( imm == 1 )
{
// special encoding of 1's
iWrite<u8>( ImplementationHelper<ImmType>::Is8BitOperand() ? 0xd0 : 0xd1 );
iWrite<u8>( Is8BitOperand() ? 0xd0 : 0xd1 );
ModRM_Direct( InstType, to.Id );
}
else
{
iWrite<u8>( ImplementationHelper<ImmType>::Is8BitOperand() ? 0xc0 : 0xc1 );
iWrite<u8>( Is8BitOperand() ? 0xc0 : 0xc1 );
ModRM_Direct( InstType, to.Id );
iWrite<u8>( imm );
}
@ -72,8 +78,8 @@ public:
static __emitinline void Emit( const ModSibStrict<ImmType>& sibdest )
{
ImplementationHelper<ImmType>::prefix16();
iWrite<u8>( ImplementationHelper<ImmType>::Is8BitOperand() ? 0xd2 : 0xd3 );
prefix16();
iWrite<u8>( Is8BitOperand() ? 0xd2 : 0xd3 );
EmitSibMagic( InstType, sibdest );
}
@ -81,16 +87,16 @@ public:
{
if( imm == 0 ) return;
ImplementationHelper<ImmType>::prefix16();
prefix16();
if( imm == 1 )
{
// special encoding of 1's
iWrite<u8>( ImplementationHelper<ImmType>::Is8BitOperand() ? 0xd0 : 0xd1 );
iWrite<u8>( Is8BitOperand() ? 0xd0 : 0xd1 );
EmitSibMagic( InstType, sibdest );
}
else
{
iWrite<u8>( ImplementationHelper<ImmType>::Is8BitOperand() ? 0xc0 : 0xc1 );
iWrite<u8>( Is8BitOperand() ? 0xc0 : 0xc1 );
EmitSibMagic( InstType, sibdest );
iWrite<u8>( imm );
}

16
pcsx2/x86/ix86/implement/group3.h
View File

@ -32,22 +32,28 @@ enum G3Type
};
template< typename ImmType >
class Group3Impl : public ImplementationHelper<ImmType>
class Group3Impl
{
protected:
static const uint OperandSize = sizeof(ImmType);
static bool Is8BitOperand() { return OperandSize == 1; }
static void prefix16() { if( OperandSize == 2 ) iWrite<u8>( 0x66 ); }
public:
Group3Impl() {} // For the love of GCC.
static __emitinline void Emit( G3Type InstType, const iRegister<ImmType>& from )
{
ImplementationHelper<ImmType>::prefix16();
iWrite<u8>(ImplementationHelper<ImmType>::Is8BitOperand() ? 0xf6 : 0xf7 );
prefix16();
iWrite<u8>(Is8BitOperand() ? 0xf6 : 0xf7 );
ModRM_Direct( InstType, from.Id );
}
static __emitinline void Emit( G3Type InstType, const ModSibStrict<ImmType>& sibsrc )
{
ImplementationHelper<ImmType>::prefix16();
iWrite<u8>( ImplementationHelper<ImmType>::Is8BitOperand() ? 0xf6 : 0xf7 );
prefix16();
iWrite<u8>( Is8BitOperand() ? 0xf6 : 0xf7 );
EmitSibMagic( InstType, sibsrc );
}
};

14
pcsx2/x86/ix86/implement/incdec.h
View File

@ -22,8 +22,14 @@
// Note: This header is meant to be included from within the x86Emitter::Internal namespace.
template< typename ImmType >
class IncDecImpl : public ImplementationHelper<ImmType>
class IncDecImpl
{
protected:
static const uint OperandSize = sizeof(ImmType);
static bool Is8BitOperand() { return OperandSize == 1; }
static void prefix16() { if( OperandSize == 2 ) iWrite<u8>( 0x66 ); }
public:
IncDecImpl() {} // For the love of GCC.
@ -31,21 +37,21 @@ public:
{
// There is no valid 8-bit form of direct register inc/dec, so fall
// back on Mod/RM format instead:
if (ImplementationHelper<ImmType>::Is8BitOperand() )
if (Is8BitOperand() )
{
write8( 0xfe );
ModRM_Direct( isDec ? 1 : 0, to.Id );
}
else
{
ImplementationHelper<ImmType>::prefix16();
prefix16();
write8( (isDec ? 0x48 : 0x40) | to.Id );
}
}
static __emitinline void Emit( bool isDec, const ModSibStrict<ImmType>& dest )
{
write8( ImplementationHelper<ImmType>::Is8BitOperand() ? 0xfe : 0xff );
write8( Is8BitOperand() ? 0xfe : 0xff );
EmitSibMagic( isDec ? 1: 0, dest );
}
};

71
pcsx2/x86/ix86/implement/movs.h
View File

@ -25,112 +25,121 @@
// MOV instruction Implementation
template< typename ImmType >
class MovImpl : ImplementationHelper< ImmType >
class MovImpl
{
public:
static const uint OperandSize = sizeof(ImmType);
protected:
static bool Is8BitOperand() { return OperandSize == 1; }
static void prefix16() { if( OperandSize == 2 ) iWrite<u8>( 0x66 ); }
public:
MovImpl() {}
// ------------------------------------------------------------------------
static __forceinline void Emit( const iRegister<ImmType>& to, const iRegister<ImmType>& from )
static __emitinline void Emit( const iRegister<ImmType>& to, const iRegister<ImmType>& from )
{
if( to == from ) return; // ignore redundant MOVs.
ImplementationHelper<ImmType>::prefix16();
iWrite<u8>( ImplementationHelper<ImmType>::Is8BitOperand() ? 0x88 : 0x89 );
prefix16();
iWrite<u8>( Is8BitOperand() ? 0x88 : 0x89 );
ModRM( 3, from.Id, to.Id );
}
// ------------------------------------------------------------------------
static __forceinline void Emit( const ModSibBase& dest, const iRegister<ImmType>& from )
static __emitinline void Emit( const ModSibBase& dest, const iRegister<ImmType>& from )
{
ImplementationHelper<ImmType>::prefix16();
prefix16();
// mov eax has a special from when writing directly to a DISP32 address
// (sans any register index/base registers).
if( from.IsAccumulator() && dest.Index.IsEmpty() && dest.Base.IsEmpty() )
{
iWrite<u8>( ImplementationHelper<ImmType>::Is8BitOperand() ? 0xa2 : 0xa3 );
iWrite<u8>( Is8BitOperand() ? 0xa2 : 0xa3 );
iWrite<u32>( dest.Displacement );
}
else
{
iWrite<u8>( ImplementationHelper<ImmType>::Is8BitOperand() ? 0x88 : 0x89 );
iWrite<u8>( Is8BitOperand() ? 0x88 : 0x89 );
EmitSibMagic( from.Id, dest );
}
}
// ------------------------------------------------------------------------
static __forceinline void Emit( const iRegister<ImmType>& to, const ModSibBase& src )
static __emitinline void Emit( const iRegister<ImmType>& to, const ModSibBase& src )
{
ImplementationHelper<ImmType>::prefix16();
prefix16();
// mov eax has a special from when reading directly from a DISP32 address
// (sans any register index/base registers).
if( to.IsAccumulator() && src.Index.IsEmpty() && src.Base.IsEmpty() )
{
iWrite<u8>( ImplementationHelper<ImmType>::Is8BitOperand() ? 0xa0 : 0xa1 );
iWrite<u8>( Is8BitOperand() ? 0xa0 : 0xa1 );
iWrite<u32>( src.Displacement );
}
else
{
iWrite<u8>( ImplementationHelper<ImmType>::Is8BitOperand() ? 0x8a : 0x8b );
iWrite<u8>( Is8BitOperand() ? 0x8a : 0x8b );
EmitSibMagic( to.Id, src );
}
}
// ------------------------------------------------------------------------
static __forceinline void Emit( void* dest, const iRegister<ImmType>& from )
static __emitinline void Emit( void* dest, const iRegister<ImmType>& from )
{
ImplementationHelper<ImmType>::prefix16();
prefix16();
// mov eax has a special from when writing directly to a DISP32 address
if( from.IsAccumulator() )
{
iWrite<u8>( ImplementationHelper<ImmType>::Is8BitOperand() ? 0xa2 : 0xa3 );
iWrite<u8>( Is8BitOperand() ? 0xa2 : 0xa3 );
iWrite<s32>( (s32)dest );
}
else
{
iWrite<u8>( ImplementationHelper<ImmType>::Is8BitOperand() ? 0x88 : 0x89 );
iWrite<u8>( Is8BitOperand() ? 0x88 : 0x89 );
iWriteDisp( from.Id, dest );
}
}
// ------------------------------------------------------------------------
static __forceinline void Emit( const iRegister<ImmType>& to, const void* src )
static __emitinline void Emit( const iRegister<ImmType>& to, const void* src )
{
ImplementationHelper<ImmType>::prefix16();
prefix16();
// mov eax has a special from when reading directly from a DISP32 address
if( to.IsAccumulator() )
{
iWrite<u8>( ImplementationHelper<ImmType>::Is8BitOperand() ? 0xa0 : 0xa1 );
iWrite<u8>( Is8BitOperand() ? 0xa0 : 0xa1 );
iWrite<s32>( (s32)src );
}
else
{
iWrite<u8>( ImplementationHelper<ImmType>::Is8BitOperand() ? 0x8a : 0x8b );
iWrite<u8>( Is8BitOperand() ? 0x8a : 0x8b );
iWriteDisp( to.Id, src );
}
}
// ------------------------------------------------------------------------
static __forceinline void Emit( const iRegister<ImmType>& to, ImmType imm )
static __emitinline void Emit( const iRegister<ImmType>& to, ImmType imm )
{
// Note: MOV does not have (reg16/32,imm8) forms.
ImplementationHelper<ImmType>::prefix16();
iWrite<u8>( (ImplementationHelper<ImmType>::Is8BitOperand() ? 0xb0 : 0xb8) | to.Id );
prefix16();
iWrite<u8>( (Is8BitOperand() ? 0xb0 : 0xb8) | to.Id );
iWrite<ImmType>( imm );
}
// ------------------------------------------------------------------------
static __forceinline void Emit( ModSibStrict<ImmType> dest, ImmType imm )
static __emitinline void Emit( ModSibStrict<ImmType> dest, ImmType imm )
{
ImplementationHelper<ImmType>::prefix16();
iWrite<u8>( ImplementationHelper<ImmType>::Is8BitOperand() ? 0xc6 : 0xc7 );
prefix16();
iWrite<u8>( Is8BitOperand() ? 0xc6 : 0xc7 );
EmitSibMagic( 0, dest );
iWrite<ImmType>( imm );
}
@ -180,9 +189,11 @@ public:
// CMOV !! [in all of it's disappointing lack-of glory]
//
template< typename ImmType >
class CMovImpl : public ImplementationHelper< ImmType >
class CMovImpl
{
protected:
static const uint OperandSize = sizeof(ImmType);
static bool Is8BitOperand() {return OperandSize == 1; }
static void prefix16() { if( OperandSize == 2 ) iWrite<u8>( 0x66 ); }
@ -195,8 +206,8 @@ protected:
}
public:
static const uint OperandSize = sizeof(ImmType);
CMovImpl() {}
static __emitinline void Emit( JccComparisonType cc, const iRegister<ImmType>& to, const iRegister<ImmType>& from )
{
if( to == from ) return;
@ -215,8 +226,6 @@ public:
emit_base( cc );
EmitSibMagic( to.Id, sibsrc );
}
CMovImpl() {}
};
// ------------------------------------------------------------------------

6
pcsx2/x86/ix86/ix86.cpp
View File

@ -427,7 +427,7 @@ static void EmitLeaMagic( iRegister<OperandType> to, const ModSibBase& src, bool
{
// ESP is not encodable as an index (ix86 ignores it), thus:
iMOV( to, ToReg( src.Base.Id ) ); // will do the trick!
iADD( to, src.Displacement );
if( src.Displacement ) iADD( to, src.Displacement );
return;
}
else if( src.Displacement == 0 )
@ -483,10 +483,8 @@ __emitinline void iLEA( iRegister16 to, const ModSibBase& src, bool preserve_fla
template< typename ImmType >
class iMulImpl
{
public:
static const uint OperandSize = sizeof(ImmType);
protected:
static const uint OperandSize = sizeof(ImmType);
static void prefix16() { if( OperandSize == 2 ) iWrite<u8>( 0x66 ); }
public:

12
pcsx2/x86/ix86/ix86_types.h
View File

@ -618,18 +618,6 @@ namespace x86Emitter
extern void EmitSibMagic( uint regfield, const ModSibBase& info );
// ------------------------------------------------------------------------
template< typename ImmType >
class ImplementationHelper
{
public:
static const uint OperandSize = sizeof(ImmType);
protected:
static bool Is8BitOperand() { return OperandSize == 1; }
static void prefix16() { if( OperandSize == 2 ) iWrite<u8>( 0x66 ); }
};
// ------------------------------------------------------------------------
#include "implement/group1.h"
#include "implement/group2.h"