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pcsx2
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Removed old versions of instructions with no constprop support . Nothing seems to boot if I disable constprop now but that may indicate a recompiler bug so I'm committing it anyway as a reminder to find it. Doesn't affect normal compiles. 

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2691 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
sudonim1 2010-03-10 20:59:43 +00:00
parent d846c8709f
commit 956d041212
8 changed files with 8 additions and 1262 deletions
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2
pcsx2/Config.h
View File

@ -605,7 +605,7 @@ TraceLogFilters& SetTraceConfig();
#undef ARITHMETICIMM_RECOMPILE
#endif
#define EE_CONST_PROP // rec2 - enables constant propagation (faster)
#define EE_CONST_PROP 1 // rec2 - enables constant propagation (faster)
// Change to 1 if working on getting PS1 emulation working.
// This disables the exception normally caused by trying to load PS1

4
pcsx2/x86/iR5900.h
View File

@ -100,8 +100,8 @@ extern void recDoBranchImm_Likely( u32* jmpSkip );
////////////////////////////////////////////////////////////////////
// Constant Propagation - From here to the end of the header!
#define GPR_IS_CONST1(reg) ((reg)<32 && (g_cpuHasConstReg&(1<<(reg))))
#define GPR_IS_CONST2(reg1, reg2) ((g_cpuHasConstReg&(1<<(reg1)))&&(g_cpuHasConstReg&(1<<(reg2))))
#define GPR_IS_CONST1(reg) (EE_CONST_PROP && (reg)<32 && (g_cpuHasConstReg&(1<<(reg))))
#define GPR_IS_CONST2(reg1, reg2) (EE_CONST_PROP && (g_cpuHasConstReg&(1<<(reg1)))&&(g_cpuHasConstReg&(1<<(reg2))))
#define GPR_SET_CONST(reg) { \
if( (reg) < 32 ) { \
g_cpuHasConstReg |= (1<<(reg)); \

321
pcsx2/x86/ix86-32/iR5900Arit.cpp
View File

@ -53,7 +53,7 @@ REC_FUNC_DEL(NOR, _Rd_);
REC_FUNC_DEL(SLT, _Rd_);
REC_FUNC_DEL(SLTU, _Rd_);
#elif defined(EE_CONST_PROP)
#else
//// ADD
void recADD_const()
@ -824,325 +824,6 @@ void recSLTU_(int info)
EERECOMPILE_CODE0(SLTU, XMMINFO_READS|XMMINFO_READT|XMMINFO_WRITED);
#else
////////////////////////////////////////////////////
void recADD( void )
{
if ( ! _Rd_ )
{
return;
}
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
ADD32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
CDQ( );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
}
////////////////////////////////////////////////////
void recADDU( void )
{
recADD( );
}
////////////////////////////////////////////////////
void recDADD( void )
{
if ( ! _Rd_ )
{
return;
}
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
ADD32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
ADC32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
}
////////////////////////////////////////////////////
void recDADDU( void )
{
recDADD( );
}
////////////////////////////////////////////////////
void recSUB( void )
{
if ( ! _Rd_ ) return;
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
SUB32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
CDQ( );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
}
////////////////////////////////////////////////////
void recSUBU( void )
{
recSUB( );
}
////////////////////////////////////////////////////
void recDSUB( void )
{
if ( ! _Rd_ ) return;
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
SUB32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
SBB32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
}
////////////////////////////////////////////////////
void recDSUBU( void )
{
recDSUB( );
}
////////////////////////////////////////////////////
void recAND( void )
{
if ( ! _Rd_ )
{
return;
}
if ( ( _Rt_ == 0 ) || ( _Rs_ == 0 ) )
{
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], 0 );
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], 0 );
}
else
{
MOVQMtoR( MM0, (int)&cpuRegs.GPR.r[ _Rs_ ] );
MOVQMtoR( MM1, (int)&cpuRegs.GPR.r[ _Rt_ ] );
PANDRtoR( MM0, MM1);
MOVQRtoM( (int)&cpuRegs.GPR.r[ _Rd_ ], MM0 );
SetMMXstate();
}
}
////////////////////////////////////////////////////
void recOR( void )
{
if ( ! _Rd_ )
{
return;
}
if ( ( _Rs_ == 0 ) && ( _Rt_ == 0 ) )
{
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], 0x0 );
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], 0x0 );
}
else if ( _Rs_ == 0 )
{
MOVQMtoR( MM0, (int)&cpuRegs.GPR.r[ _Rt_ ] );
MOVQRtoM( (int)&cpuRegs.GPR.r[ _Rd_ ], MM0 );
SetMMXstate();
}
else if ( _Rt_ == 0 )
{
MOVQMtoR( MM0, (int)&cpuRegs.GPR.r[ _Rs_ ] );
MOVQRtoM( (int)&cpuRegs.GPR.r[ _Rd_ ], MM0 );
SetMMXstate();
}
else
{
MOVQMtoR( MM0, (int)&cpuRegs.GPR.r[ _Rs_ ] );
MOVQMtoR( MM1, (int)&cpuRegs.GPR.r[ _Rt_ ] );
PORRtoR( MM0, MM1 );
MOVQRtoM( (int)&cpuRegs.GPR.r[ _Rd_ ], MM0 );
SetMMXstate();
}
}
////////////////////////////////////////////////////
void recXOR( void )
{
if ( ! _Rd_ )
{
return;
}
if ( ( _Rs_ == 0 ) && ( _Rt_ == 0 ) )
{
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ],0x0);
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ],0x0);
return;
}
if ( _Rs_ == 0 )
{
MOVQMtoR( MM0, (int)&cpuRegs.GPR.r[ _Rt_ ] );
MOVQRtoM( (int)&cpuRegs.GPR.r[ _Rd_ ], MM0 );
SetMMXstate();
return;
}
if ( _Rt_ == 0 )
{
MOVQMtoR( MM0, (int)&cpuRegs.GPR.r[ _Rs_ ] );
MOVQRtoM( (int)&cpuRegs.GPR.r[ _Rd_ ], MM0 );
SetMMXstate();
return;
}
MOVQMtoR( MM0, (int)&cpuRegs.GPR.r[ _Rs_ ] );
MOVQMtoR( MM1, (int)&cpuRegs.GPR.r[ _Rt_ ] );
PXORRtoR( MM0, MM1);
MOVQRtoM( (int)&cpuRegs.GPR.r[ _Rd_ ], MM0 );
SetMMXstate();
}
////////////////////////////////////////////////////
void recNOR( void )
{
if ( ! _Rd_ )
{
return;
}
if ( ( _Rs_ == 0 ) && ( _Rt_ == 0 ) )
{
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ],0xffffffff);
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ],0xffffffff);
return;
}
if ( _Rs_ == 0 )
{
MOVQMtoR( MM0, (int)&cpuRegs.GPR.r[ _Rt_ ] );
PCMPEQDRtoR( MM1,MM1);
PXORRtoR( MM0,MM1);
MOVQRtoM( (int)&cpuRegs.GPR.r[ _Rd_ ],MM0);
SetMMXstate();
return;
}
if ( _Rt_ == 0 )
{
MOVQMtoR( MM0, (int)&cpuRegs.GPR.r[ _Rs_ ] );
PCMPEQDRtoR( MM1,MM1);
PXORRtoR( MM0,MM1);
MOVQRtoM( (int)&cpuRegs.GPR.r[ _Rd_ ],MM0);
SetMMXstate();
return;
}
MOVQMtoR( MM0, (int)&cpuRegs.GPR.r[ _Rs_ ] );
PCMPEQDRtoR( MM1,MM1);
PORMtoR( MM0,(int)&cpuRegs.GPR.r[ _Rt_ ] );
PXORRtoR( MM0,MM1);
MOVQRtoM( (int)&cpuRegs.GPR.r[ _Rd_ ],MM0);
SetMMXstate();
}
////////////////////////////////////////////////////
// test with silent hill, lemans
void recSLT( void )
{
if ( ! _Rd_ )
return;
MOV32ItoR(EAX, 1);
if( _Rs_ == 0 ) {
CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0);
j8Ptr[0] = JG8( 0 );
j8Ptr[2] = JL8( 0 );
CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], 0 );
j8Ptr[1] = JA8(0);
x86SetJ8(j8Ptr[2]);
XOR32RtoR(EAX, EAX);
}
else if( _Rt_ == 0 ) {
CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ], 0);
j8Ptr[0] = JL8( 0 );
j8Ptr[2] = JG8( 0 );
CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ], 0);
j8Ptr[1] = JB8(0);
x86SetJ8(j8Ptr[2]);
XOR32RtoR(EAX, EAX);
}
else {
MOV32MtoR(ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ]);
CMP32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ]);
j8Ptr[0] = JL8( 0 );
j8Ptr[2] = JG8( 0 );
MOV32MtoR(ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
CMP32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ]);
j8Ptr[1] = JB8(0);
x86SetJ8(j8Ptr[2]);
XOR32RtoR(EAX, EAX);
}
x86SetJ8(j8Ptr[0]);
x86SetJ8(j8Ptr[1]);
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], 0 );
}
////////////////////////////////////////////////////
void recSLTU( void )
{
MOV32ItoR(EAX, 1);
if( _Rs_ == 0 ) {
CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0);
j8Ptr[0] = JA8( 0 );
j8Ptr[2] = JB8( 0 );
CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], 0 );
j8Ptr[1] = JA8(0);
x86SetJ8(j8Ptr[2]);
XOR32RtoR(EAX, EAX);
}
else if( _Rt_ == 0 ) {
CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ], 0);
j8Ptr[0] = JB8( 0 );
j8Ptr[2] = JA8( 0 );
CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ], 0);
j8Ptr[1] = JB8(0);
x86SetJ8(j8Ptr[2]);
XOR32RtoR(EAX, EAX);
}
else {
MOV32MtoR(ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ]);
CMP32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ]);
j8Ptr[0] = JB8( 0 );
j8Ptr[2] = JA8( 0 );
MOV32MtoR(ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
CMP32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ]);
j8Ptr[1] = JB8(0);
x86SetJ8(j8Ptr[2]);
XOR32RtoR(EAX, EAX);
}
x86SetJ8(j8Ptr[0]);
x86SetJ8(j8Ptr[1]);
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], 0 );
}
#endif
} } }

168
pcsx2/x86/ix86-32/iR5900AritImm.cpp
View File

@ -45,7 +45,7 @@ REC_FUNC_DEL(XORI, _Rt_);
REC_FUNC_DEL(SLTI, _Rt_);
REC_FUNC_DEL(SLTIU, _Rt_);
#elif defined(EE_CONST_PROP)
#else
//// ADDI
void recADDI_const( void )
@ -259,172 +259,6 @@ void recXORI_(int info)
EERECOMPILE_CODEX(eeRecompileCode1, XORI);
#else
////////////////////////////////////////////////////
void recADDI( void )
{
if ( ! _Rt_ )
{
return;
}
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
if ( _Imm_ != 0 )
{
ADD32ItoR( EAX, _Imm_ );
}
CDQ( );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], EDX );
}
////////////////////////////////////////////////////
void recADDIU( void )
{
recADDI( );
}
////////////////////////////////////////////////////
void recDADDI( void )
{
if ( ! _Rt_ )
{
return;
}
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
if ( _Imm_ != 0 )
{
ADD32ItoR( EAX, _Imm_ );
if ( _Imm_ < 0 )
{
ADC32ItoR( EDX, 0xffffffff );
}
else
{
ADC32ItoR( EDX, 0 );
}
}
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], EDX );
}
////////////////////////////////////////////////////
void recDADDIU( void )
{
recDADDI( );
}
////////////////////////////////////////////////////
void recSLTIU( void )
{
if ( ! _Rt_ )
return;
MOV32ItoR(EAX, 1);
CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ], _Imm_ >= 0 ? 0 : 0xffffffff);
j8Ptr[0] = JB8( 0 );
j8Ptr[2] = JA8( 0 );
CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ], (s32)_Imm_ );
j8Ptr[1] = JB8(0);
x86SetJ8(j8Ptr[2]);
XOR32RtoR(EAX, EAX);
x86SetJ8(j8Ptr[0]);
x86SetJ8(j8Ptr[1]);
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0 );
}
////////////////////////////////////////////////////
void recSLTI( void )
{
if ( ! _Rt_ )
return;
// test silent hill if modding
MOV32ItoR(EAX, 1);
CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ], _Imm_ >= 0 ? 0 : 0xffffffff);
j8Ptr[0] = JL8( 0 );
j8Ptr[2] = JG8( 0 );
CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ], (s32)_Imm_ );
j8Ptr[1] = JB8(0);
x86SetJ8(j8Ptr[2]);
XOR32RtoR(EAX, EAX);
x86SetJ8(j8Ptr[0]);
x86SetJ8(j8Ptr[1]);
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0 );
}
////////////////////////////////////////////////////
void recANDI( void )
{
if ( ! _Rt_ )
{
return;
}
if ( _ImmU_ != 0 )
{
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
AND32ItoR( EAX, _ImmU_ );
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0 );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
}
else
{
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0 );
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], 0 );
}
}
////////////////////////////////////////////////////
static u64 _imm = 0; // temp immediate
void recORI( void )
{
if ( ! _Rt_ )
return;
MOVQMtoR( MM0, (int)&cpuRegs.GPR.r[ _Rs_ ].UD[ 0 ] );
if ( _ImmU_ != 0 )
{
MOV32ItoM( (int)&_imm, _ImmU_ );
MOVQMtoR( MM1, (int)&_imm );
PORRtoR( MM0, MM1 );
}
MOVQRtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UD[ 0 ], MM0 );
SetMMXstate();
}
////////////////////////////////////////////////////
void recXORI( void )
{
if ( ! _Rt_ )
return;
MOVQMtoR( MM0, (int)&cpuRegs.GPR.r[ _Rs_ ] );
if ( _ImmU_ != 0 )
{
MOV32ItoM( (int)&_imm, _ImmU_ );
MOVQMtoR( MM1, (int)&_imm );
PXORRtoR( MM0, MM1 );
}
MOVQRtoM( (int)&cpuRegs.GPR.r[ _Rt_ ], MM0 );
SetMMXstate();
}
#endif
} } }

233
pcsx2/x86/ix86-32/iR5900Branch.cpp
View File

@ -54,8 +54,6 @@ REC_SYS_DEL(BGEZALL, 31);
#else
#if defined(EE_CONST_PROP)
void recSetBranchEQ(int info, int bne, int process)
{
if( info & PROCESS_EE_XMM ) {
@ -577,198 +575,6 @@ void recBGEZALL( void )
SetBranchImm(pc);
}
#else
////////////////////////////////////////////////////
void recBEQ( void )
{
u32 branchTo = ((s32)_Imm_ * 4) + pc;
if ( _Rs_ == _Rt_ )
{
_clearNeededMMXregs();
_clearNeededXMMregs();
recompileNextInstruction(1);
SetBranchImm( branchTo );
}
else
{
MOV32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
CMP32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
j32Ptr[ 0 ] = JNE32( 0 );
MOV32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
CMP32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
j32Ptr[ 1 ] = JNE32( 0 );
_clearNeededMMXregs();
_clearNeededXMMregs();
SaveBranchState();
recompileNextInstruction(1);
SetBranchImm(branchTo);
x86SetJ32( j32Ptr[ 0 ] );
x86SetJ32( j32Ptr[ 1 ] );
// recopy the next inst
pc -= 4;
LoadBranchState();
recompileNextInstruction(1);
SetBranchImm(pc);
}
}
////////////////////////////////////////////////////
void recBNE( void )
{
u32 branchTo = ((s32)_Imm_ * 4) + pc;
if ( _Rs_ == _Rt_ )
{
_clearNeededMMXregs();
_clearNeededXMMregs();
recompileNextInstruction(1);
SetBranchImm(pc);
return;
}
MOV32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
CMP32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
j32Ptr[ 0 ] = JNE32( 0 );
MOV32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
CMP32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
j32Ptr[ 1 ] = JE32( 0 );
x86SetJ32( j32Ptr[ 0 ] );
_clearNeededMMXregs();
_clearNeededXMMregs();
SaveBranchState();
recompileNextInstruction(1);
SetBranchImm(branchTo);
x86SetJ32( j32Ptr[ 1 ] );
// recopy the next inst
pc -= 4;
LoadBranchState();
recompileNextInstruction(1);
SetBranchImm(pc);
}
////////////////////////////////////////////////////
void recBEQL( void )
{
u32 branchTo = ((s32)_Imm_ * 4) + pc;
MOV32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
CMP32RtoR( ECX, EDX );
j32Ptr[ 0 ] = JNE32( 0 );
MOV32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
CMP32RtoR( ECX, EDX );
j32Ptr[ 1 ] = JNE32( 0 );
_clearNeededMMXregs();
_clearNeededXMMregs();
SaveBranchState();
recompileNextInstruction(1);
SetBranchImm(branchTo);
x86SetJ32( j32Ptr[ 0 ] );
x86SetJ32( j32Ptr[ 1 ] );
LoadBranchState();
SetBranchImm(pc);
}
////////////////////////////////////////////////////
void recBNEL( void )
{
u32 branchTo = ((s32)_Imm_ * 4) + pc;
MOV32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
CMP32RtoR( ECX, EDX );
j32Ptr[ 0 ] = JNE32( 0 );
MOV32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
CMP32RtoR( ECX, EDX );
j32Ptr[ 1 ] = JNE32( 0 );
_clearNeededMMXregs();
_clearNeededXMMregs();
SaveBranchState();
SetBranchImm(pc+4);
x86SetJ32( j32Ptr[ 0 ] );
x86SetJ32( j32Ptr[ 1 ] );
// recopy the next inst
LoadBranchState();
recompileNextInstruction(1);
SetBranchImm(branchTo);
}
/*********************************************************
* Register branch logic *
* Format: OP rs, offset *
*********************************************************/
////////////////////////////////////////////////////
void recBLTZAL( void )
{
MOV32ItoM( (int)&cpuRegs.code, cpuRegs.code );
MOV32ItoM( (int)&cpuRegs.pc, pc );
iFlushCall(FLUSH_EVERYTHING);
CALLFunc( (uptr)R5900::Interpreter::OpcodeImpl::BLTZAL );
branch = 2;
}
////////////////////////////////////////////////////
void recBGEZAL( void )
{
MOV32ItoM( (int)&cpuRegs.code, cpuRegs.code );
MOV32ItoM( (int)&cpuRegs.pc, pc );
iFlushCall(FLUSH_EVERYTHING);
CALLFunc( (uptr)R5900::Interpreter::OpcodeImpl::BGEZAL );
branch = 2;
}
////////////////////////////////////////////////////
void recBLTZALL( void )
{
MOV32ItoM( (int)&cpuRegs.code, cpuRegs.code );
MOV32ItoM( (int)&cpuRegs.pc, pc );
iFlushCall(FLUSH_EVERYTHING);
CALLFunc( (uptr)R5900::Interpreter::OpcodeImpl::BLTZALL );
branch = 2;
}
////////////////////////////////////////////////////
void recBGEZALL( void )
{
MOV32ItoM( (int)&cpuRegs.code, cpuRegs.code );
MOV32ItoM( (int)&cpuRegs.pc, pc );
iFlushCall(FLUSH_EVERYTHING);
CALLFunc( (uptr)R5900::Interpreter::OpcodeImpl::BGEZALL );
branch = 2;
}
#endif
//// BLEZ
void recBLEZ( void )
@ -863,7 +669,6 @@ void recBGTZ( void )
}
////////////////////////////////////////////////////
#ifdef EE_CONST_PROP
void recBLTZ()
{
u32 branchTo = ((s32)_Imm_ * 4) + pc;
@ -988,44 +793,6 @@ void recBGEZL( void )
SetBranchImm(pc);
}
#else
void recBLTZ( void )
{
MOV32ItoM( (int)&cpuRegs.code, cpuRegs.code );
MOV32ItoM( (int)&cpuRegs.pc, pc );
iFlushCall(FLUSH_EVERYTHING);
CALLFunc( (uptr)R5900::Interpreter::OpcodeImpl::BLTZ );
branch = 2;
}
void recBGEZ( void )
{
MOV32ItoM( (int)&cpuRegs.code, cpuRegs.code );
MOV32ItoM( (int)&cpuRegs.pc, pc );
iFlushCall(FLUSH_EVERYTHING);
CALLFunc( (uptr)R5900::Interpreter::OpcodeImpl::BGEZ );
branch = 2;
}
void recBLTZL( void )
{
MOV32ItoM( (int)&cpuRegs.code, cpuRegs.code );
MOV32ItoM( (int)&cpuRegs.pc, pc );
iFlushCall(FLUSH_EVERYTHING);
CALLFunc( (uptr)R5900::Interpreter::OpcodeImpl::BLTZL );
branch = 2;
}
void recBGEZL( void )
{
MOV32ItoM( (int)&cpuRegs.code, cpuRegs.code );
MOV32ItoM( (int)&cpuRegs.pc, pc );
iFlushCall(FLUSH_EVERYTHING);
CALLFunc( (uptr)R5900::Interpreter::OpcodeImpl::BGEZL );
branch = 2;
}
#endif

116
pcsx2/x86/ix86-32/iR5900Move.cpp
View File

@ -53,7 +53,7 @@ REC_FUNC( MTLO1 );
REC_FUNC_DEL(MOVZ, _Rd_);
REC_FUNC_DEL(MOVN, _Rd_);
#elif defined(EE_CONST_PROP)
#else
/*********************************************************
* Load higher 16 bits of the first word in GPR with imm *
@ -577,120 +577,6 @@ void recMOVN()
recMOVNtemp();
}
#else
////////////////////////////////////////////////////
void recLUI( void )
{
if(!_Rt_) return;
if ( _Imm_ < 0 )
{
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], (u32)_Imm_ << 16 ); //U
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0xffffffff ); //V
}
else
{
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], (u32)_Imm_ << 16 ); //U
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0 ); //V
}
}
////////////////////////////////////////////////////
void recMFHI( void )
{
if ( ! _Rd_ )
{
return;
}
MOVQMtoR( MM0, (int)&cpuRegs.HI.UD[ 0 ] );
MOVQRtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UD[ 0 ], MM0 );
SetMMXstate();
}
////////////////////////////////////////////////////
void recMFLO( void )
{
if ( ! _Rd_ )
{
return;
}
MOVQMtoR( MM0, (int)&cpuRegs.LO.UD[ 0 ] );
MOVQRtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UD[ 0 ], MM0 );
SetMMXstate();
}
////////////////////////////////////////////////////
void recMTHI( void )
{
MOVQMtoR( MM0, (int)&cpuRegs.GPR.r[ _Rs_ ].UD[ 0 ] );
MOVQRtoM( (int)&cpuRegs.HI.UD[ 0 ], MM0 );
SetMMXstate();
}
////////////////////////////////////////////////////
void recMTLO( void )
{
MOVQMtoR( MM0, (int)&cpuRegs.GPR.r[ _Rs_ ].UD[ 0 ] );
MOVQRtoM( (int)&cpuRegs.LO.UD[ 0 ], MM0 );
SetMMXstate();
}
////////////////////////////////////////////////////
void recMOVZ( void )
{
if ( ! _Rd_ )
{
return;
}
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
OR32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
j8Ptr[ 0 ] = JNZ8( 0 );
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
x86SetJ8( j8Ptr[ 0 ] );
}
////////////////////////////////////////////////////
void recMOVN( void )
{
if ( ! _Rd_ )
{
return;
}
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
OR32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
j8Ptr[ 0 ] = JZ8( 0 );
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
MOV32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], ECX );
x86SetJ8( j8Ptr[ 0 ] );
}
REC_FUNC( MFHI1 );
REC_FUNC( MFLO1 );
REC_FUNC( MTHI1 );
REC_FUNC( MTLO1 );
#endif
} } }

111
pcsx2/x86/ix86-32/iR5900MultDiv.cpp
View File

@ -48,7 +48,7 @@ REC_FUNC_DEL( MADDU , _Rd_);
REC_FUNC_DEL( MADD1 , _Rd_);
REC_FUNC_DEL( MADDU1 , _Rd_ );
#elif defined(EE_CONST_PROP)
#else
// if upper is 1, write in upper 64 bits of LO/HI
void recWritebackHILO(int info, int writed, int upper)
@ -950,115 +950,6 @@ void recMADDU1()
}
#else
////////////////////////////////////////////////////
void recMULT( void )
{
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
IMUL32M( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
MOV32RtoR( ECX, EDX );
CDQ( );
MOV32RtoM( (int)&cpuRegs.LO.UL[ 0 ], EAX );
MOV32RtoM( (int)&cpuRegs.LO.UL[ 1 ], EDX );
if ( _Rd_ )
{
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
}
MOV32RtoR( EAX, ECX );
CDQ( );
MOV32RtoM( (int)&cpuRegs.HI.UL[ 0 ], EAX );
MOV32RtoM( (int)&cpuRegs.HI.UL[ 1 ], EDX );
}
////////////////////////////////////////////////////
void recMULTU( void )
{
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
MUL32M( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
MOV32RtoR( ECX, EDX );
CDQ( );
MOV32RtoM( (int)&cpuRegs.LO.UL[ 0 ], EAX );
MOV32RtoM( (int)&cpuRegs.LO.UL[ 1 ], EDX );
if ( _Rd_ != 0 )
{
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
}
MOV32RtoR( EAX, ECX );
CDQ( );
MOV32RtoM( (int)&cpuRegs.HI.UL[ 0 ], ECX );
MOV32RtoM( (int)&cpuRegs.HI.UL[ 1 ], EDX );
}
////////////////////////////////////////////////////
void recDIV( void )
{
MOV32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
OR32RtoR( ECX, ECX );
j8Ptr[ 0 ] = JE8( 0 );
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
// XOR32RtoR( EDX,EDX );
CDQ();
IDIV32R( ECX );
MOV32RtoR( ECX, EDX );
CDQ( );
MOV32RtoM( (int)&cpuRegs.LO.UL[ 0 ], EAX );
MOV32RtoM( (int)&cpuRegs.LO.UL[ 1 ], EDX );
MOV32RtoR( EAX, ECX );
CDQ( );
MOV32RtoM( (int)&cpuRegs.HI.UL[ 0 ], ECX );
MOV32RtoM( (int)&cpuRegs.HI.UL[ 1 ], EDX );
x86SetJ8( j8Ptr[ 0 ] );
}
////////////////////////////////////////////////////
void recDIVU( void )
{
MOV32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
OR32RtoR( ECX, ECX );
j8Ptr[ 0 ] = JE8( 0 );
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
XOR32RtoR( EDX, EDX );
// CDQ();
DIV32R( ECX );
MOV32RtoR( ECX, EDX );
CDQ( );
MOV32RtoM( (int)&cpuRegs.LO.UL[ 0 ], EAX );
MOV32RtoM( (int)&cpuRegs.LO.UL[ 1 ], EDX );
MOV32RtoR( EAX,ECX );
CDQ( );
MOV32RtoM( (int)&cpuRegs.HI.UL[ 0 ], ECX );
MOV32RtoM( (int)&cpuRegs.HI.UL[ 1 ], EDX );
x86SetJ8( j8Ptr[ 0 ] );
}
REC_FUNC_DEL( MULT1, _Rd_ );
REC_FUNC_DEL( MULTU1, _Rd_ );
REC_FUNC_DEL( DIV1, _Rd_ );
REC_FUNC_DEL( DIVU1, _Rd_ );
REC_FUNC_DEL( MADD, _Rd_ );
REC_FUNC_DEL( MADDU, _Rd_ );
REC_FUNC_DEL( MADD1, _Rd_ );
REC_FUNC_DEL( MADDU1, _Rd_ );
#endif
} } }

315
pcsx2/x86/ix86-32/iR5900Shift.cpp
View File

@ -51,7 +51,7 @@ REC_FUNC_DEL(DSLLV, _Rd_);
REC_FUNC_DEL(DSRLV, _Rd_);
REC_FUNC_DEL(DSRAV, _Rd_);
#elif defined(EE_CONST_PROP)
#else
//// SLL
void recSLL_const()
@ -614,319 +614,6 @@ void recDSRAV_(int info)
EERECOMPILE_CODE0(DSRAV, XMMINFO_READS|XMMINFO_READT|XMMINFO_WRITED);
#else
////////////////////////////////////////////////////
void recDSRA( void )
{
if( !_Rd_ ) return; //?
if ( _Sa_ != 0 ) {
// it is a signed shift
MOVQMtoR(MM0, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
MOVQRtoR(MM1, MM0);
PSRADItoR(MM0, _Sa_);
PSRLQItoR(MM1, _Sa_);
PUNPCKHDQRtoR(MM0, MM0); // shift to lower
// take lower dword of MM1 and lower dword of MM0
PUNPCKLDQRtoR(MM1, MM0);
MOVQRtoM((int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], MM1);
}
else {
MOVQMtoR(MM0, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
MOVQRtoM((int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], MM0);
}
SetMMXstate();
}
////////////////////////////////////////////////////
void recDSRA32(void)
{
if( !_Rd_ ) return; //?
MOV32MtoR(EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
CDQ();
if ( _Sa_ != 0 )
{
SAR32ItoR( EAX, _Sa_ );
}
MOV32RtoM((int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX);
MOV32RtoM((int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX);
}
////////////////////////////////////////////////////
void recSLL( void )
{
if ( ! _Rd_ )
return;
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
if ( _Sa_ != 0 )
{
SHL32ItoR( EAX, _Sa_ );
}
CDQ( );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
}
////////////////////////////////////////////////////
void recSRL( void )
{
if ( ! _Rd_ )
{
return;
}
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
if ( _Sa_ != 0 )
{
SHR32ItoR( EAX, _Sa_);
}
CDQ( );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
}
////////////////////////////////////////////////////
void recSRA( void )
{
if ( ! _Rd_ )
{
return;
}
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
if ( _Sa_ != 0 )
{
SAR32ItoR( EAX, _Sa_);
}
CDQ();
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
}
////////////////////////////////////////////////////
void recDSLL( void )
{
if ( ! _Rd_ )
{
return;
}
MOVQMtoR( MM0, (int)&cpuRegs.GPR.r[ _Rt_ ] );
if ( _Sa_ != 0 )
{
PSLLQItoR( MM0, _Sa_ );
}
MOVQRtoM( (int)&cpuRegs.GPR.r[ _Rd_ ], MM0 );
SetMMXstate();
}
////////////////////////////////////////////////////
void recDSRL( void )
{
if ( ! _Rd_ )
{
return;
}
MOVQMtoR( MM0, (int)&cpuRegs.GPR.r[ _Rt_ ] );
if ( _Sa_ != 0 )
{
PSRLQItoR( MM0, _Sa_ );
}
MOVQRtoM( (int)&cpuRegs.GPR.r[ _Rd_ ], MM0 );
SetMMXstate();
}
////////////////////////////////////////////////////
void recDSLL32( void )
{
if ( ! _Rd_ )
{
return;
}
if ( _Sa_ == 0 )
{
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], 0 );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EAX );
return;
}
MOVQMtoR( MM0, (int)&cpuRegs.GPR.r[ _Rt_ ] );
PSLLQItoR( MM0, _Sa_ + 32 );
MOVQRtoM( (int)&cpuRegs.GPR.r[ _Rd_ ], MM0 );
SetMMXstate();
}
////////////////////////////////////////////////////
void recDSRL32( void )
{
if ( ! _Rd_ )
{
return;
}
if ( _Sa_ == 0 )
{
MOV32MtoR( EAX,(int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], 0 );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
return;
}
MOVQMtoR( MM0, (int)&cpuRegs.GPR.r[ _Rt_ ] );
PSRLQItoR( MM0, _Sa_ + 32 );
MOVQRtoM( (int)&cpuRegs.GPR.r[ _Rd_ ], MM0 );
SetMMXstate();
}
/*********************************************************
* Shift arithmetic with variant register shift *
* Format: OP rd, rt, rs *
*********************************************************/
////////////////////////////////////////////////////
////////////////////////////////////////////////////
void recSLLV( void )
{
if ( ! _Rd_ ) return;
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
if ( _Rs_ != 0 )
{
MOV32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
AND32ItoR( ECX, 0x1f );
SHL32CLtoR( EAX );
}
CDQ();
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
}
////////////////////////////////////////////////////
void recSRLV( void )
{
if ( ! _Rd_ ) return;
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
if ( _Rs_ != 0 )
{
MOV32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
AND32ItoR( ECX, 0x1f );
SHR32CLtoR( EAX );
}
CDQ( );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
}
////////////////////////////////////////////////////
void recSRAV( void )
{
if ( ! _Rd_ ) return;
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
if ( _Rs_ != 0 )
{
MOV32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
AND32ItoR( ECX, 0x1f );
SAR32CLtoR( EAX );
}
CDQ( );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
}
////////////////////////////////////////////////////
static u64 _sa = 0;
void recDSLLV( void )
{
if ( ! _Rd_ ) return;
MOVQMtoR( MM0, (int)&cpuRegs.GPR.r[ _Rt_ ] );
if ( _Rs_ != 0 )
{
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ] );
AND32ItoR( EAX, 0x3f);
MOV32RtoM( (int)&_sa, EAX );
PSLLQMtoR( MM0, (int)&_sa );
}
MOVQRtoM( (int)&cpuRegs.GPR.r[ _Rd_ ], MM0 );
SetMMXstate();
}
////////////////////////////////////////////////////
void recDSRLV( void )
{
if ( ! _Rd_ ) return;
MOVQMtoR( MM0, (int)&cpuRegs.GPR.r[ _Rt_ ] );
if ( _Rs_ != 0 )
{
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ] );
AND32ItoR( EAX, 0x3f);
MOV32RtoM( (int)&_sa, EAX );
PSRLQMtoR( MM0, (int)&_sa );
}
MOVQRtoM( (int)&cpuRegs.GPR.r[ _Rd_ ], MM0 );
SetMMXstate();
}
////////////////////////////////////////////////////////////////
void recDSRAV( void )
{
MOVQMtoR(MM0, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
if ( _Rs_ != 0 ) {
PXORRtoR(MM1, MM1);
// calc high bit
MOVQRtoR(MM2, MM0);
PUNPCKHDQRtoR(MM2, MM2); // shift to lower
PCMPGTDRtoR(MM1, MM2);
// it is a signed shift
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ] );
AND32ItoR( EAX, 0x3f);
MOVD32RtoMMX(MM2, EAX); // amount to shift
NOT32R(EAX);
ADD32ItoR(EAX, 65);
// right logical shift
PSRLQRtoR(MM0, MM2);
// shift highest bit, 64 - eax
MOVD32RtoMMX(MM2, EAX);
PSLLQRtoR(MM1, MM2); // highest bits
PORRtoR(MM0, MM1);
MOVQRtoM((int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], MM0);
}
else {
MOVQRtoM((int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], MM0);
}
SetMMXstate();
}
#endif
} } }