mirror of https://github.com/PCSX2/pcsx2.git
IPU: Remove some DMA hacks
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3922091a58
commit
9441d2a33a
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@ -58,7 +58,7 @@ void tIPU_cmd::clear()
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__fi void IPUProcessInterrupt()
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__fi void IPUProcessInterrupt()
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{
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{
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if (ipuRegs.ctrl.BUSY && !CommandExecuteQueued) // && (g_BP.FP || g_BP.IFC || (ipu1ch.chcr.STR && ipu1ch.qwc > 0)))
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if (ipuRegs.ctrl.BUSY && !CommandExecuteQueued)
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IPUWorker();
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IPUWorker();
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}
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}
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@ -277,16 +277,6 @@ __fi RETURNS_R64 ipuRead64(u32 mem)
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void ipuSoftReset()
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void ipuSoftReset()
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{
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{
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if (ipu1ch.chcr.STR && g_BP.IFC < 8 && IPU1Status.DataRequested)
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{
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DevCon.Warning("Refill input fifo on reset");
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ipu1Interrupt();
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}
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if (!ipu1ch.chcr.STR)
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psHu32(DMAC_STAT) &= ~(1 << DMAC_TO_IPU);
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ipu_fifo.clear();
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ipu_fifo.clear();
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memzero(g_BP);
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memzero(g_BP);
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@ -317,8 +307,8 @@ __fi bool ipuWrite32(u32 mem, u32 value)
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return false;
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return false;
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ipucase(IPU_CTRL): // IPU_CTRL
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ipucase(IPU_CTRL): // IPU_CTRL
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// CTRL = the first 16 bits of ctrl [0x8000ffff], + value for the next 16 bits,
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// CTRL = the first 16 bits of ctrl [0x8000ffff], + value for the next 16 bits,
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// minus the reserved bits. (18-19; 27-29) [0x47f30000]
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// minus the reserved bits. (18-19; 27-29) [0x47f30000]
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ipuRegs.ctrl.write(value);
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ipuRegs.ctrl.write(value);
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if (ipuRegs.ctrl.IDP == 3)
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if (ipuRegs.ctrl.IDP == 3)
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{
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{
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@ -361,12 +351,6 @@ __fi bool ipuWrite64(u32 mem, u64 value)
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static void ipuBCLR(u32 val)
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static void ipuBCLR(u32 val)
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{
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{
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if (ipu1ch.chcr.STR && g_BP.IFC < 8 && IPU1Status.DataRequested)
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ipu1Interrupt();
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if(!ipu1ch.chcr.STR)
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psHu32(DMAC_STAT) &= ~(1 << DMAC_TO_IPU);
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ipu_fifo.in.clear();
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ipu_fifo.in.clear();
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memzero(g_BP);
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memzero(g_BP);
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g_BP.BP = val & 0x7F;
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g_BP.BP = val & 0x7F;
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@ -950,11 +934,6 @@ __noinline void IPUWorker()
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//ipuRegs.ctrl.OFC = 0;
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//ipuRegs.ctrl.OFC = 0;
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ipuRegs.topbusy = 0;
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ipuRegs.topbusy = 0;
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ipuRegs.cmd.BUSY = 0;
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ipuRegs.cmd.BUSY = 0;
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// CHECK!: IPU0dma remains when IDEC is done, so we need to clear it
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// Check Mana Khemia 1 "off campus" to trigger a GUST IDEC messup.
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// This hackfixes it :/
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//if (ipu0ch.qwc > 0 && ipu0ch.chcr.STR) ipu0Interrupt();
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break;
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break;
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case SCE_IPU_BDEC:
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case SCE_IPU_BDEC:
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@ -41,9 +41,10 @@ void IPU_Fifo_Input::clear()
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// Because the FIFO is drained it will request more data immediately
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// Because the FIFO is drained it will request more data immediately
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IPU1Status.DataRequested = true;
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IPU1Status.DataRequested = true;
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if (ipu1ch.chcr.STR && cpuRegs.eCycle[4] == 0x9999)
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if (ipu1ch.chcr.STR && cpuRegs.eCycle[4] == 0x9999)
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{
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{
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CPU_INT(DMAC_TO_IPU, 32);
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CPU_INT(DMAC_TO_IPU, 4);
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}
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}
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}
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}
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