mirror of https://github.com/PCSX2/pcsx2.git
ReorderingMTGS: Added a new optimized memcpy_amd_qwc, for use by GIFpath copies. After much studying, we determined this is about as efficient as memcpy will ever get, for what we're doing with it.
DevNot: Win32-only at the moment -- needs a GAS port (but that shouldn't be hard). I made some notes in the code about it. git-svn-id: http://pcsx2.googlecode.com/svn/branches/ReorderingMTGS@3472 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
Jake.Stine
parent
a6b3acb5d0
commit
934578c8fe
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@ -28,6 +28,7 @@
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# include "win_memzero.h"
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extern void __fastcall memcpy_amd_(void *dest, const void *src, size_t bytes);
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extern void memcpy_amd_qwc(void *dest, const void *src, size_t bytes);
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extern u8 memcmp_mmx(const void* src1, const void* src2, int cmpsize);
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extern void memxor_mmx(void* dst, const void* src1, int cmpsize);
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@ -37,6 +38,8 @@
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void _memset16_unaligned( void* dest, u16 data, size_t size );
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#define memcpy_fast memcpy_amd_ // Fast memcpy
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#define memcpy_aligned(d,s,c) memcpy_amd_(d,s,c*16) // Memcpy with 16-byte Aligned addresses
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#define memcpy_aligned(d,s,c) memcpy_amd_(d,s,c) // Memcpy with 16-byte Aligned addresses
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#define memcpy_const memcpy_amd_ // Memcpy with constant size
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#define memcpy_constA memcpy_amd_ // Memcpy with constant size and 16-byte aligned
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#define memcpy_qwc(d,s,c) memcpy_amd_qwc(d,s,c)
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//#define memcpy_qwc(d,s,c) memcpy_amd_(d,s,c*16)
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@ -129,6 +129,10 @@ namespace Threading
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// For use in spin/wait loops.
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extern void SpinWait();
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// Use prior to committing data to another thread (internal memcpy_qwc does not use fencing,
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// so that many memcpys can be issued in a row more efficiently)
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extern void StoreFence();
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// Optional implementation to enable hires thread/process scheduler for the operating system.
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// Needed by Windows, but might not be relevant to other platforms.
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@ -36,6 +36,11 @@ __forceinline void Threading::SpinWait()
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__asm pause;
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}
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__forceinline void Threading::StoreFence()
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{
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__asm sfence;
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}
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__forceinline void Threading::EnableHiresScheduler()
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{
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// This improves accuracy of Sleep() by some amount, and only adds a negligible amount of
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@ -146,7 +146,7 @@ $memcpy_ic_1: ; 64-byte block copies, in-cache copy
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add esi, 64 ; update source pointer
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add edi, 64 ; update destination pointer
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dec eax ; count down
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sub eax, 1
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jnz $memcpy_ic_1 ; last 64-byte block?
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$memcpy_ic_2:
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@ -189,64 +189,15 @@ $memcpy_uc_1: ; 64-byte blocks, uncached copy
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movq mm1,[esi-8]
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movntq [edi-24], mm2
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movntq [edi-16], mm0
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dec eax
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movntq [edi-8], mm1
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sub eax, 1
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jnz $memcpy_uc_1 ; last 64-byte block?
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jmp $memcpy_ic_2 ; almost done (not needed because large copy below was removed)
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// For the largest size blocks, a special technique called Block Prefetch
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// can be used to accelerate the read operations. Block Prefetch reads
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// one address per cache line, for a series of cache lines, in a short loop.
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// This is faster than using software prefetch. The technique is great for
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// getting maximum read bandwidth, especially in DDR memory systems.
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// Note: Pcsx2 rarely invokes large copies, so this mode has been disabled to
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// help keep the code cache footprint of memcpy_fast to a minimum.
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/*
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$memcpy_bp_1: ; large blocks, block prefetch copy
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cmp ecx, CACHEBLOCK ; big enough to run another prefetch loop?
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jl $memcpy_64_test ; no, back to regular uncached copy
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mov eax, CACHEBLOCK / 2 ; block prefetch loop, unrolled 2X
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add esi, CACHEBLOCK * 64 ; move to the top of the block
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align 16
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$memcpy_bp_2:
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mov edx, [esi-64] ; grab one address per cache line
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mov edx, [esi-128] ; grab one address per cache line
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sub esi, 128 ; go reverse order to suppress HW prefetcher
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dec eax ; count down the cache lines
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jnz $memcpy_bp_2 ; keep grabbing more lines into cache
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mov eax, CACHEBLOCK ; now that it's in cache, do the copy
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align 16
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$memcpy_bp_3:
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movq mm0, [esi ] ; read 64 bits
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movq mm1, [esi+ 8]
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movq mm2, [esi+16]
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movq mm3, [esi+24]
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movq mm4, [esi+32]
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movq mm5, [esi+40]
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movq mm6, [esi+48]
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movq mm7, [esi+56]
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add esi, 64 ; update source pointer
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movntq [edi ], mm0 ; write 64 bits, bypassing cache
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movntq [edi+ 8], mm1 ; note: movntq also prevents the CPU
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movntq [edi+16], mm2 ; from READING the destination address
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movntq [edi+24], mm3 ; into the cache, only to be over-written,
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movntq [edi+32], mm4 ; so that also helps performance
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movntq [edi+40], mm5
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movntq [edi+48], mm6
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movntq [edi+56], mm7
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add edi, 64 ; update dest pointer
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dec eax ; count down
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jnz $memcpy_bp_3 ; keep copying
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sub ecx, CACHEBLOCK ; update the 64-byte block count
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jmp $memcpy_bp_1 ; keep processing chunks
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*/
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// Note: Pcsx2 rarely invokes large copies, so the large copy "block prefetch" mode has been
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// disabled to help keep the code cache footprint of memcpy_fast to a minimum.
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// The smallest copy uses the X86 "movsd" instruction, in an optimized
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// form which is an "unrolled loop". Then it handles the last few bytes.
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@ -274,17 +225,99 @@ $memcpy_last_few: ; dword aligned from before movsd's
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rep movsb ; the last 1, 2, or 3 bytes
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$memcpy_final:
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pop esi
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pop edi
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emms ; clean up the MMX state
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sfence ; flush the write buffer
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//mov eax, [dest] ; ret value = destination pointer
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pop esi
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pop edi
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ret 4
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}
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}
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// Quadword Copy! Count is in QWCs (128 bits). Neither source nor dest need to be aligned.
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__forceinline void memcpy_amd_qwc(void *dest, const void *src, size_t qwc)
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{
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// Optimization Analysis: This code is *nearly* optimal. Do not think that using XMM
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// registers will improve copy performance, because they won't. Use of XMMs is only
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// warranted in situations where both source and dest are guaranteed aligned to 16 bytes,
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// and even then the benefits are typically minimal (sometimes slower depending on the
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// amount of data being copied).
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//
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// Thus: MMX are alignment safe, fast, and widely available. Lets just stick with them.
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// --air
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// Linux Conversion note:
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// This code would benefit nicely from having inline-able GAS syntax, since it should
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// allow GCC to optimize the first 3 instructions out of existence in many scenarios.
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// And its called enough times to probably merit the extra effort to ensure proper
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// optimization. --air
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__asm
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{
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mov ecx, [dest]
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mov edx, [src]
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mov eax, [qwc] ; keep a copy of count
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shr eax, 1
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jz $memcpy_qwc_1 ; only one 16 byte block to copy?
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cmp eax, IN_CACHE_COPY/32
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jb $memcpy_qwc_loop1 ; small copies should be cached (definite speedup --air)
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$memcpy_qwc_loop2: ; 32-byte blocks, uncached copy
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prefetchnta [edx + 568] ; start reading ahead (tested: it helps! --air)
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movq mm0,[edx+0] ; read 64 bits
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movq mm1,[edx+8]
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movq mm2,[edx+16]
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movntq [ecx+0], mm0 ; write 64 bits, bypassing the cache
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movntq [ecx+8], mm1
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movq mm3,[edx+24]
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movntq [ecx+16], mm2
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movntq [ecx+24], mm3
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add edx,32 ; update source pointer
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add ecx,32 ; update destination pointer
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sub eax,1
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jnz $memcpy_qwc_loop2 ; last 64-byte block?
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sfence ; flush the write buffer
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jmp $memcpy_qwc_1
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; 32-byte blocks, cached!
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; This *is* important. Removing this and using exclusively non-temporal stores
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; results in noticable speed loss!
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$memcpy_qwc_loop1:
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prefetchnta [edx + 568] ; start reading ahead (tested: it helps! --air)
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movq mm0,[edx+0] ; read 64 bits
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movq mm1,[edx+8]
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movq mm2,[edx+16]
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movq [ecx+0], mm0 ; write 64 bits, bypassing the cache
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movq [ecx+8], mm1
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movq mm3,[edx+24]
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movq [ecx+16], mm2
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movq [ecx+24], mm3
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add edx,32 ; update source pointer
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add ecx,32 ; update destination pointer
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sub eax,1
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jnz $memcpy_qwc_loop1 ; last 64-byte block?
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$memcpy_qwc_1:
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test [qwc],1
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jz $memcpy_qwc_final
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movq mm0,[edx]
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movq mm1,[edx+8]
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movq [ecx], mm0
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movq [ecx+8], mm1
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$memcpy_qwc_final:
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emms ; clean up the MMX state
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}
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}
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// mmx mem-compare implementation, size has to be a multiple of 8
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// returns 0 is equal, nonzero value if not equal
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// ~10 times faster than standard memcmp
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@ -395,6 +395,7 @@ struct Pcsx2Config
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// style. Useful for debugging potential bugs in the MTGS pipeline.
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bool SynchronousMTGS;
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bool DisableOutput;
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int VsyncQueueSize;
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bool FrameLimitEnable;
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bool FrameSkipEnable;
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@ -420,6 +421,8 @@ struct Pcsx2Config
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return
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OpEqu( SynchronousMTGS ) &&
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OpEqu( DisableOutput ) &&
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OpEqu( VsyncQueueSize ) &&
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OpEqu( FrameSkipEnable ) &&
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OpEqu( FrameLimitEnable ) &&
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OpEqu( VsyncEnable ) &&
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@ -142,14 +142,11 @@ void SysMtgsThread::PostVsyncEnd()
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SendDataPacket();
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// Alter-frame flushing! Restarts the ringbuffer (wraps) on every other frame. This is a
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// mandatory feature that prevents the MTGS from queuing more than 2 frames at any time.
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// (queued frames cause input lag and desynced audio -- bad!). Ring restarts work for this
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// because they act as sync points where the EE must stall to wait for the GS to catch-up,
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// and they also allow us to reuse the front of the ringbuffer more often, which should improve
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// L2 cache performance.
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// If the MTGS is allowed to queue a lot of frames in advance, it creates input lag.
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// Use the Queued FrameCount to stall the EE if another vsync is already queued in
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// the ringbuffer.
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if( AtomicIncrement(m_QueuedFrameCount) < 2 ) return;
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if( AtomicIncrement(m_QueuedFrameCount) < EmuConfig.GS.VsyncQueueSize ) return;
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uint readpos = volatize(m_RingPos);
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uint freeroom;
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@ -190,7 +187,7 @@ void SysMtgsThread::OpenPlugin()
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{
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if( m_PluginOpened ) return;
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memcpy_aligned( RingBuffer.Regs, PS2MEM_GS, sizeof(PS2MEM_GS)/16 );
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memcpy_aligned( RingBuffer.Regs, PS2MEM_GS, sizeof(PS2MEM_GS) );
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GSsetBaseMem( RingBuffer.Regs );
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GSirqCallback( dummyIrqCallback );
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@ -624,6 +621,7 @@ void SysMtgsThread::SendDataPacket()
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PacketTagType& tag = (PacketTagType&)RingBuffer[m_packet_startpos];
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tag.data[0] = actualSize;
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//Threading::StoreFence();
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m_WritePos = m_packet_ringpos;
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if( EmuConfig.GS.SynchronousMTGS )
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@ -217,6 +217,7 @@ Pcsx2Config::GSOptions::GSOptions()
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SynchronousMTGS = false;
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DisableOutput = false;
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VsyncQueueSize = 2;
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DefaultRegionMode = Region_NTSC;
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FramesToDraw = 2;
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@ -234,6 +235,7 @@ void Pcsx2Config::GSOptions::LoadSave( IniInterface& ini )
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IniEntry( SynchronousMTGS );
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IniEntry( DisableOutput );
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IniEntry( VsyncQueueSize );
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IniEntry( FrameLimitEnable );
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IniEntry( FrameSkipEnable );
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@ -526,36 +526,36 @@ __forceinline int GIFPath::ParseTagQuick(GIF_PATH pathidx, const u8* pMem, u32 s
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void MemCopy_WrappedDest( const u128* src, u128* destBase, uint& destStart, uint destSize, uint len )
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{
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uint endpos = destStart + len;
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if( endpos >= destSize )
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if( endpos < destSize )
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{
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uint firstcopylen = destSize - destStart;
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memcpy_aligned(&destBase[destStart], src, firstcopylen );
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destStart = endpos % destSize;
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memcpy_aligned(destBase, src+firstcopylen, destStart );
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memcpy_qwc(&destBase[destStart], src, len );
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destStart += len;
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}
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else
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{
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memcpy_aligned(&destBase[destStart], src, len );
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destStart += len;
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uint firstcopylen = destSize - destStart;
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memcpy_qwc(&destBase[destStart], src, firstcopylen );
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destStart = endpos % destSize;
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memcpy_qwc(destBase, src+firstcopylen, destStart );
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}
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}
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void MemCopy_WrappedSrc( const u128* srcBase, uint& srcStart, uint srcSize, u128* dest, uint len )
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{
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uint endpos = srcStart + len;
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if( endpos >= srcSize )
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if( endpos < srcSize )
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{
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uint firstcopylen = srcSize - srcStart;
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memcpy_aligned(dest, &srcBase[srcStart], firstcopylen );
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srcStart = endpos & srcSize;
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memcpy_aligned(dest+firstcopylen, srcBase, srcStart );
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memcpy_qwc(dest, &srcBase[srcStart], len );
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srcStart += len;
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}
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else
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{
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memcpy_aligned(dest, &srcBase[srcStart], len );
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srcStart += len;
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uint firstcopylen = srcSize - srcStart;
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memcpy_qwc(dest, &srcBase[srcStart], firstcopylen );
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srcStart = endpos & srcSize;
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memcpy_qwc(dest+firstcopylen, srcBase, srcStart );
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}
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}
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@ -1129,14 +1129,14 @@ void __fastcall mVU_XGKICK_(u32 addr) {
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// fixme: one of these days the following *16's will get cleaned up when we introduce
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// a special qwc/simd16 optimized version of memcpy_aligned. :)
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//DevCon.Status("XGkick Wrap!");
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memcpy_aligned(pDest, microVU1.regs->Mem + (addr*16), diff);
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memcpy_qwc(pDest, microVU1.regs->Mem + (addr*16), diff);
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Path1WritePos += size;
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size -= diff;
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pDest += diff*16;
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memcpy_aligned(pDest, microVU1.regs->Mem, size);
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memcpy_qwc(pDest, microVU1.regs->Mem, size);
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}
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else {
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memcpy_aligned(pDest, microVU1.regs->Mem + (addr*16), size);
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memcpy_qwc(pDest, microVU1.regs->Mem + (addr*16), size);
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Path1WritePos += size;
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}
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//if(!gifRegs->stat.P1Q) CPU_INT(28, 128);
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