diff --git a/pcsx2/HwWrite.cpp b/pcsx2/HwWrite.cpp
index b1e842930e..c845205aa6 100644
--- a/pcsx2/HwWrite.cpp
+++ b/pcsx2/HwWrite.cpp
@@ -109,7 +109,7 @@ static __forceinline void DmaExec8( void (*func)(), u32 mem, u8 value )
 		func();
 		Registers::Thaw();
 	}
-	else
+	else if(reg->chcr.STR)
 	{
 		//DevCon.Warning(L"8bit %s DMA Start while DMAC Disabled\n",ChcrName(mem));
 		QueuedDMA._u16 |= (1 << ChannelNumber(mem & ~0xf)); //Queue the DMA up to be started then the DMA's are Enabled and or the Suspend is lifted
@@ -165,7 +165,7 @@ static __forceinline void DmaExec16( void (*func)(), u32 mem, u16 value )
 		func();
 		Registers::Thaw();
 	}
-	else
+	else if(reg->chcr.STR)
 	{
 		//DevCon.Warning(L"16bit %s DMA Start while DMAC Disabled\n",ChcrName(mem));
 		QueuedDMA._u16 |= (1 << ChannelNumber(mem)); //Queue the DMA up to be started then the DMA's are Enabled and or the Suspend is lifted
diff --git a/pcsx2/IPU/IPU.cpp b/pcsx2/IPU/IPU.cpp
index db7a6eb282..14657fd635 100644
--- a/pcsx2/IPU/IPU.cpp
+++ b/pcsx2/IPU/IPU.cpp
@@ -248,7 +248,7 @@ __forceinline u32 ipuRead32(u32 mem)
 			ipuRegs->ipubp |= g_BP.IFC << 8;
 			ipuRegs->ipubp |= (g_BP.FP /*+ g_BP.bufferhasnew*/) << 16;
 
-			IPU_LOG("Ipu read32: IPU_BP=0x%08X", *(u32*)&g_BP);
+			IPU_LOG("Ipu read32: IPU_BP=0x%08X", ipuRegs->ipubp);
 			return ipuRegs->ipubp;
 		default:
 			IPU_LOG("Ipu read32: Addr=0x%x Value = 0x%08X", mem, *(u32*)(((u8*)ipuRegs) + mem));
@@ -1409,6 +1409,8 @@ int IPU1dma()
 					ipu1cycles += 1; // Add 1 cycles from the QW read for the tag
 					IPU1Status.ChainMode = ptag->ID;
 
+					if(ipu1dma->chcr.TTE) DevCon.Warning("TTE?");
+
 					switch (IPU1Status.ChainMode)
 					{
 						case TAG_REFE: // refe