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1.0 branch: Merged the latest GIF / VU Interpreter changes as well. 

git-svn-id: http://pcsx2.googlecode.com/svn/branches/1.0.0@5251 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
ramapcsx2 2012-05-31 18:45:34 +00:00
parent fd6511fc6e
commit 9253a64a20
7 changed files with 62 additions and 8 deletions
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28
pcsx2/Gif.cpp
View File

@ -57,8 +57,12 @@ __fi void gifInterrupt()
if(vif1Regs.stat.VGW)
{
CPU_INT(DMAC_GIF, 16);
return;
CPU_INT(DMAC_VIF1, 1);
if(!gifUnit.Path3Masked())
CPU_INT(DMAC_GIF, 16);
if(!gspath3done || gifch.qwc > 0) return;
}
}
@ -168,7 +172,10 @@ static __fi tDMA_TAG* ReadTag2()
bool CheckPaths(EE_EventType Channel) {
// Can't do Path 3, so try dma again later...
if(!gifUnit.CanDoPath3()) {
CPU_INT(Channel, 128);
if(!gifUnit.Path3Masked())
{
CPU_INT(Channel, 128);
}
return false;
}
return true;
@ -448,6 +455,21 @@ void gifMFIFOInterrupt()
GIF_LOG("gifMFIFOInterrupt");
mfifocycles = 0;
if(gifUnit.gifPath[GIF_PATH_3].state == GIF_PATH_WAIT)
{
gifUnit.gifPath[GIF_PATH_3].state = GIF_PATH_IDLE;
if(vif1Regs.stat.VGW)
{
CPU_INT(DMAC_VIF1, 1);
if(!gifUnit.Path3Masked())
CPU_INT(DMAC_MFIFO_GIF, 16);
if(!gspath3done || gifch.qwc > 0) return;
}
}
if (dmacRegs.ctrl.MFD != MFD_GIF) {
DevCon.Warning("Not in GIF MFIFO mode! Stopping GIF MFIFO");
return;

2
pcsx2/VU.h
View File

@ -139,6 +139,8 @@ struct __aligned16 VURegs {
// classes requires considerable code refactoring. Maybe later. >_<
u32 branch;
u32 branchpc;
u32 delaybranchpc;
bool takedelaybranch;
// MAC/Status flags -- these are used by interpreters and superVU, but are kind of hacky
// and shouldn't be relied on for any useful/valid info. Would like to move them out of

8
pcsx2/VU0microInterp.cpp
View File

@ -148,6 +148,14 @@ static void _vu0Exec(VURegs* VU)
VU->branch--;
if (VU->branch == 0) {
VU->VI[REG_TPC].UL = VU->branchpc;
if(VU->takedelaybranch == true)
{
//DevCon.Warning("Setting VU0 Delay branch to next branch, treating first as delay slot");
VU->branchpc = VU->delaybranchpc;
VU->delaybranchpc = 0;
VU->branch = 2;
VU->takedelaybranch = false;
}
}
}

8
pcsx2/VU1microInterp.cpp
View File

@ -144,6 +144,14 @@ static void _vu1Exec(VURegs* VU)
if (VU->branch > 0) {
if (VU->branch-- == 1) {
VU->VI[REG_TPC].UL = VU->branchpc;
if(VU->takedelaybranch == true)
{
//DevCon.Warning("Setting VU1 Delay branch to next branch, treating first as delay slot");
VU->branchpc = VU->delaybranchpc;
VU->delaybranchpc = 0;
VU->branch = 2;
VU->takedelaybranch = false;
}
}
}

13
pcsx2/VUops.cpp
View File

@ -1873,8 +1873,17 @@ s32 _branchAddr(VURegs * VU) {
}
static __fi void _setBranch(VURegs * VU, u32 bpc) {
VU->branch = 2;
VU->branchpc = bpc;
if(VU->branch == 1)
{
//DevCon.Warning("Branch in Branch Delay slot!");
VU->delaybranchpc = bpc;
VU->takedelaybranch = true;
}
else
{
VU->branch = 2;
VU->branchpc = bpc;
}
}
static __ri void _vuIBEQ(VURegs * VU) {

4
pcsx2/Vif1_Dma.cpp
View File

@ -342,7 +342,9 @@ __fi void vif1Interrupt()
if(g_vif1Cycles > 0 || vif1ch.qwc)
{
CPU_INT(DMAC_VIF1, max((int)g_vif1Cycles, 8));
if(!(vif1Regs.stat.VGW && gifUnit.gifPath[GIF_PATH_3].state != GIF_PATH_IDLE)) //If we're waiting on GIF, stop looping, (can be over 1000 loops!)
CPU_INT(DMAC_VIF1, max((int)g_vif1Cycles, 8));
return;
}
else if(vif1Regs.stat.VPS == VPS_TRANSFERRING) DevCon.Warning("Cycles %x, cmd %x, qwc %x, waitonvu %x", g_vif1Cycles, vif1.cmd, vif1ch.qwc, vif1.waitforvu);

7
pcsx2/Vif1_MFIFO.cpp
View File

@ -318,9 +318,12 @@ void vifMFIFOInterrupt()
vif1Regs.stat.FQC = min((u16)0x10, vif1ch.qwc);
case 1: //Transfer data
mfifo_VIF1chain();
if(vif1.inprogress & 0x1) //Just in case the tag breaks early (or something wierd happens)!
mfifo_VIF1chain();
//Sanity check! making sure we always have non-zero values
CPU_INT(DMAC_MFIFO_VIF, (g_vif1Cycles == 0 ? 4 : g_vif1Cycles) );
if(!(vif1Regs.stat.VGW && gifUnit.gifPath[GIF_PATH_3].state != GIF_PATH_IDLE)) //If we're waiting on GIF, stop looping, (can be over 1000 loops!)
CPU_INT(DMAC_MFIFO_VIF, (g_vif1Cycles == 0 ? 4 : g_vif1Cycles) );
vif1Regs.stat.FQC = min((u16)0x10, vif1ch.qwc);
return;
}