mirror of https://github.com/PCSX2/pcsx2.git
microVU: more recompiler first-pass implementation stuff...
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@915 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
cottonvibes
parent
014b5c6671
commit
923802f936
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@ -23,11 +23,12 @@
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#include "VUmicro.h"
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#include "iVUzerorec.h"
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#ifndef PCSX2_MICROVU_
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namespace VU0micro
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{
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void recAlloc()
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{
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SuperVUAlloc(0);
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void recAlloc()
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{
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SuperVUAlloc(0);
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}
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void __fastcall recClear(u32 Addr, u32 Size)
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@ -62,6 +63,32 @@ namespace VU0micro
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FreezeXMMRegs(0);
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}
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}
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#else
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extern void initVUrec(VURegs* vuRegs, const int vuIndex);
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extern void closeVUrec(const int vuIndex);
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extern void resetVUrec(const int vuIndex);
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extern void clearVUrec(u32 addr, u32 size, const int vuIndex);
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extern void runVUrec(u32 startPC, u32 cycles, const int vuIndex);
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namespace VU0micro
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{
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void recAlloc() { initVUrec(&VU0, 0); }
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void __fastcall recClear(u32 Addr, u32 Size) { clearVUrec(Addr, Size, 0); }
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void recShutdown() { closeVUrec(0); }
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static void recReset() { resetVUrec(0); x86FpuState = FPU_STATE; }
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static void recStep() {}
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static void recExecuteBlock()
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{
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if((VU0.VI[REG_VPU_STAT].UL & 1) == 0) return;
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FreezeXMMRegs(1);
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runVUrec(VU0.VI[REG_TPC].UL & 0xfff, 0xffffffff, 0);
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FreezeXMMRegs(0);
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}
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}
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#endif
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using namespace VU0micro;
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@ -29,7 +29,7 @@
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#ifdef _DEBUG
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extern u32 vudump;
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#endif
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#ifndef PCSX2_MICROVU_
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namespace VU1micro
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{
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void recAlloc()
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@ -121,6 +121,32 @@ namespace VU1micro
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FreezeXMMRegs(0);
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}
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}
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#else
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extern void initVUrec(VURegs* vuRegs, const int vuIndex);
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extern void closeVUrec(const int vuIndex);
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extern void resetVUrec(const int vuIndex);
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extern void clearVUrec(u32 addr, u32 size, const int vuIndex);
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extern void runVUrec(u32 startPC, u32 cycles, const int vuIndex);
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namespace VU1micro
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{
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void recAlloc() { initVUrec(&VU1, 1); }
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void __fastcall recClear(u32 Addr, u32 Size) { clearVUrec(Addr, Size, 1); }
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void recShutdown() { closeVUrec(1); }
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static void recReset() { resetVUrec(1); x86FpuState = FPU_STATE; }
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static void recStep() {}
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static void recExecuteBlock() {
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if((VU0.VI[REG_VPU_STAT].UL & 0x100) == 0) return;
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assert( (VU1.VI[REG_TPC].UL&7) == 0 );
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FreezeXMMRegs(1);
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runVUrec(VU1.VI[REG_TPC].UL & 0x3fff, 0xffffffff, 1);
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FreezeXMMRegs(0);
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}
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}
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#endif
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using namespace VU1micro;
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@ -42,7 +42,7 @@ microVUt(void) mVUinit(VURegs* vuRegsPtr) {
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mVU->index = vuIndex;
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mVU->microSize = (vuIndex ? 0x4000 : 0x1000);
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mVU->progSize = (vuIndex ? 0x4000 : 0x1000) / 8;
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mVU->cacheAddr = 0xC0000000 + (vuIndex ? mVU->cacheSize : 0);
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mVU->cacheAddr = (vuIndex ? 0x1e840000 : 0x0e840000);
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mVU->cache = NULL;
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mVUreset<vuIndex>();
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@ -55,16 +55,16 @@ microVUt(void) mVUreset() {
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mVUclose<vuIndex>(); // Close
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// Create Block Managers
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for (int i; i <= mVU->prog.max; i++) {
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for (u32 j; j < (mVU->progSize / 2); j++) {
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for (int i = 0; i <= mVU->prog.max; i++) {
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for (u32 j = 0; j < (mVU->progSize / 2); j++) {
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mVU->prog.prog[i].block[j] = new microBlockManager();
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}
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}
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// Dynarec Cache
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mVU->cache = SysMmapEx(mVU->cacheAddr, mVU->cacheSize, 0x10000000, (vuIndex ? "Micro VU1" : "Micro VU0"));
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if ( mVU->cache == NULL ) throw Exception::OutOfMemory(fmt_string( "microVU Error: failed to allocate recompiler memory! (addr: 0x%x)", params (u32)mVU->cache));
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mVU->cache = SysMmapEx(mVU->cacheAddr, mVU->cacheSize, 0, (vuIndex ? "Micro VU1" : "Micro VU0"));
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if ( mVU->cache == NULL ) throw Exception::OutOfMemory(fmt_string( "microVU Error: Failed to allocate recompiler memory! (addr: 0x%x)", params (u32)mVU->cache));
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// Other Variables
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memset(&mVU->prog, 0, sizeof(mVU->prog));
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mVU->prog.finished = 1;
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@ -81,8 +81,8 @@ microVUt(void) mVUclose() {
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if ( mVU->cache ) { HostSys::Munmap( mVU->cache, mVU->cacheSize ); mVU->cache = NULL; }
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// Delete Block Managers
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for (int i; i <= mVU->prog.max; i++) {
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for (u32 j; j < (mVU->progSize / 2); j++) {
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for (int i = 0; i <= mVU->prog.max; i++) {
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for (u32 j = 0; j < (mVU->progSize / 2); j++) {
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if (mVU->prog.prog[i].block[j]) delete mVU->prog.prog[i].block[j];
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}
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}
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@ -277,27 +277,27 @@ extern "C" {
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// Wrapper Functions - Called by other parts of the Emu
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//------------------------------------------------------------------
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__forceinline void initVUrec(VURegs* vuRegs, const int vuIndex) {
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void initVUrec(VURegs* vuRegs, const int vuIndex) {
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if (!vuIndex) mVUinit<0>(vuRegs);
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else mVUinit<1>(vuRegs);
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}
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__forceinline void closeVUrec(const int vuIndex) {
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void closeVUrec(const int vuIndex) {
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if (!vuIndex) mVUclose<0>();
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else mVUclose<1>();
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}
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__forceinline void resetVUrec(const int vuIndex) {
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void resetVUrec(const int vuIndex) {
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if (!vuIndex) mVUreset<0>();
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else mVUreset<1>();
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}
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__forceinline void clearVUrec(u32 addr, u32 size, const int vuIndex) {
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void clearVUrec(u32 addr, u32 size, const int vuIndex) {
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if (!vuIndex) mVUclear<0>(addr, size);
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else mVUclear<1>(addr, size);
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}
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__forceinline void runVUrec(u32 startPC, u32 cycles, const int vuIndex) {
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void runVUrec(u32 startPC, u32 cycles, const int vuIndex) {
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if (!vuIndex) startVU0(startPC, cycles);
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else startVU1(startPC, cycles);
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}
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@ -54,6 +54,7 @@ struct microAllocInfo {
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u8 maxStall; // Helps in computing stalls (stores the max amount of cycles to stall for the current opcodes)
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u32 cycles; // Cycles for current block
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u32 curPC; // Current PC
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u32 startPC; // Start PC for Cur Block
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u32 info[pSize]; // bit 00 = Lower Instruction is NOP
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// bit 01
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// bit 02
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@ -143,4 +143,18 @@ microVUt(void) mVUanalyzeEFU2(int Fs, u8 xCycles) {
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analyzePreg(xCycles);
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}
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//------------------------------------------------------------------
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// Sflag - Status Flag Opcodes
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//------------------------------------------------------------------
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#define analyzeVIreg1(reg) { if (reg) { mVUstall = aMax(mVUstall, mVUregs.VI[reg]); } }
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#define analyzeVIreg2(reg, aCycles) { if (reg) { mVUregsTemp.VIreg = reg; mVUregsTemp.VI = aCycles; } }
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microVUt(void) mVUanalyzeSflag(int It) {
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microVU* mVU = mVUx;
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if (!It) { mVUinfo |= _isNOP; return; }
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mVUinfo |= _isSflag;
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analyzeVIreg2(It, 1);
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}
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#endif //PCSX2_MICROVU
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@ -19,18 +19,6 @@
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#pragma once
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#ifdef PCSX2_MICROVU
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#ifdef mVUdebug
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#define mVUdebugStuff1() { \
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if (curI & _Ibit_) { SysPrintf("microVU: I-bit set!\n"); } \
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if (curI & _Ebit_) { SysPrintf("microVU: E-bit set!\n"); } \
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if (curI & _Mbit_) { SysPrintf("microVU: M-bit set!\n"); } \
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if (curI & _Dbit_) { SysPrintf("microVU: D-bit set!\n"); } \
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if (curI & _Tbit_) { SysPrintf("microVU: T-bit set!\n"); } \
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}
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#else
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#define mVUdebugStuff1() {}
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#endif
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#define createBlock(blockEndPtr) { \
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block.pipelineState = pipelineState; \
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block.x86ptrStart = x86ptrStart; \
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@ -59,19 +47,18 @@ microVUt(void) mVUsetCycles() {
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microVUx(void) mVUcompile(u32 startPC, u32 pipelineState, microRegInfo* pState, u8* x86ptrStart) {
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microVU* mVU = mVUx;
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microBlock block;
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int branch;
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iPC = startPC / 4;
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// Searches for Existing Compiled Block (if found, then returns; else, compile)
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microBlock* pblock = mVUblock[iPC]->search(pipelineState, pState);
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if (block) { x86SetPtr(pblock->x86ptrEnd); return; }
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// First Pass
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setCode();
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branch = 0;
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mVUbranch = 0;
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mVUcycles = 1; // Skips "M" phase, and starts counting cycles at "T" stage
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for (;;) {
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mVUbranch = 0;
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mVUstartPC = iPC;
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mVUcycles = 1; // Skips "M" phase, and starts counting cycles at "T" stage
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for (int branch = 0;; ) {
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startLoop();
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mVUopU<vuIndex, 0>();
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if (curI & _Ebit_) { branch = 1; }
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@ -89,6 +76,9 @@ microVUx(void) mVUcompile(u32 startPC, u32 pipelineState, microRegInfo* pState,
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iPC = startPC;
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setCode();
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for (bool x = 1; x; ) {
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//
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// ToDo: status/mac flag stuff
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//
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if (isEOB) { x = 0; }
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else if (isBranch) { mVUopU<vuIndex, 1>(); incPC(2); }
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@ -23,6 +23,10 @@
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// Micro VU Micromode Lower instructions
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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// DIV/SQRT/RSQRT
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//------------------------------------------------------------------
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#define testZero(xmmReg, xmmTemp, gprTemp) { \
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SSE_XORPS_XMM_to_XMM(xmmTemp, xmmTemp); /* Clear xmmTemp (make it 0) */ \
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SSE_CMPEQPS_XMM_to_XMM(xmmTemp, xmmReg); /* Set all F's if zero */ \
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@ -128,6 +132,10 @@ microVUf(void) mVU_RSQRT() {
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}
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}
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//------------------------------------------------------------------
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// EATAN/EEXP/ELENG/ERCPR/ERLENG/ERSADD/ERSQRT/ESADD/ESIN/ESQRT/ESUM
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//------------------------------------------------------------------
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#define EATANhelper(addr) { \
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SSE_MULSS_XMM_to_XMM(xmmT1, xmmFs); \
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SSE_MULSS_XMM_to_XMM(xmmT1, xmmFs); \
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@ -401,6 +409,10 @@ microVUf(void) mVU_ESUM() {
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}
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}
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//------------------------------------------------------------------
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// FCAND/FCEQ/FCGET/FCOR/FCSET
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//------------------------------------------------------------------
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microVUf(void) mVU_FCAND() {
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microVU* mVU = mVUx;
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if (!recPass) {}
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@ -456,6 +468,10 @@ microVUf(void) mVU_FCSET() {
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}
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}
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//------------------------------------------------------------------
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// FMAND/FMEQ/FMOR
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//------------------------------------------------------------------
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microVUf(void) mVU_FMAND() {
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microVU* mVU = mVUx;
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if (!recPass) {}
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@ -491,9 +507,13 @@ microVUf(void) mVU_FMOR() {
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}
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}
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//------------------------------------------------------------------
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// FSAND/FSEQ/FSOR/FSSET
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//------------------------------------------------------------------
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microVUf(void) mVU_FSAND() {
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microVU* mVU = mVUx;
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if (!recPass) {}
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if (!recPass) { mVUanalyzeSflag<vuIndex>(_Ft_); }
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else {
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mVUallocSFLAGa<vuIndex>(gprT1, fvsInstance);
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AND16ItoR(gprT1, _Imm12_);
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@ -503,7 +523,7 @@ microVUf(void) mVU_FSAND() {
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microVUf(void) mVU_FSEQ() {
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microVU* mVU = mVUx;
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if (!recPass) {}
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if (!recPass) { mVUanalyzeSflag<vuIndex>(_Ft_); }
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else {
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mVUallocSFLAGa<vuIndex>(gprT1, fvsInstance);
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XOR16ItoR(gprT1, _Imm12_);
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@ -515,7 +535,7 @@ microVUf(void) mVU_FSEQ() {
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microVUf(void) mVU_FSOR() {
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microVU* mVU = mVUx;
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if (!recPass) {}
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if (!recPass) { mVUanalyzeSflag<vuIndex>(_Ft_); }
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else {
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mVUallocSFLAGa<vuIndex>(gprT1, fvsInstance);
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OR16ItoR(gprT1, _Imm12_);
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@ -536,6 +556,10 @@ microVUf(void) mVU_FSSET() {
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}
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}
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//------------------------------------------------------------------
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// IADD/IADDI/IADDIU/IAND/IOR/ISUB/ISUBIU
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//------------------------------------------------------------------
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microVUf(void) mVU_IADD() {
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microVU* mVU = mVUx;
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if (!recPass) {}
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@ -623,6 +647,10 @@ microVUf(void) mVU_ISUBIU() {
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}
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}
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//------------------------------------------------------------------
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// MOVE/MFIR/MFP/MTIR/MR32
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//------------------------------------------------------------------
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microVUf(void) mVU_MOVE() {
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microVU* mVU = mVUx;
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if (!recPass) { /*If (!_Ft_ || (_Ft_ == _Fs_)) nop();*/ }
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@ -672,6 +700,10 @@ microVUf(void) mVU_MR32() {
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}
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}
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//------------------------------------------------------------------
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// ILW/ILWR
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//------------------------------------------------------------------
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microVUf(void) mVU_ILW() {
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microVU* mVU = mVUx;
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if (!recPass) { /*If (!_Ft_) nop();*/ }
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@ -709,6 +741,10 @@ microVUf(void) mVU_ILWR() {
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}
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}
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//------------------------------------------------------------------
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// ISW/ISWR
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//------------------------------------------------------------------
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microVUf(void) mVU_ISW() {
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microVU* mVU = mVUx;
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if (!recPass) {}
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@ -757,6 +793,10 @@ microVUf(void) mVU_ISWR() {
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}
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}
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//------------------------------------------------------------------
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// LQ/LQD/LQI
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//------------------------------------------------------------------
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microVUf(void) mVU_LQ() {
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microVU* mVU = mVUx;
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if (!recPass) { /*If (!_Ft_) nop();*/ }
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@ -818,6 +858,10 @@ microVUf(void) mVU_LQI() {
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}
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}
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//------------------------------------------------------------------
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// SQ/SQD/SQI
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//------------------------------------------------------------------
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microVUf(void) mVU_SQ() {
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microVU* mVU = mVUx;
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if (!recPass) {}
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@ -875,6 +919,10 @@ microVUf(void) mVU_SQI() {
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}
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}
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//------------------------------------------------------------------
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// RINIT/RGET/RNEXT/RXOR
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//------------------------------------------------------------------
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microVUf(void) mVU_RINIT() {
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microVU* mVU = mVUx;
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if (!recPass) {}
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@ -938,21 +986,27 @@ microVUf(void) mVU_RXOR() {
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}
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}
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//------------------------------------------------------------------
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// WaitP/WaitQ
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//------------------------------------------------------------------
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microVUf(void) mVU_WAITP() {
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microVU* mVU = mVUx;
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if (!recPass) {}
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else {}
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if (!recPass) { mVUstall = aMax(mVUstall, ((mVUregs.p) ? (mVUregs.p - 1) : 0)); }
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}
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microVUf(void) mVU_WAITQ() {
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microVU* mVU = mVUx;
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if (!recPass) {}
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else {}
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if (!recPass) { mVUstall = aMax(mVUstall, mVUregs.q); }
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}
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//------------------------------------------------------------------
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// XTOP/XITOP
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||||
//------------------------------------------------------------------
|
||||
|
||||
microVUf(void) mVU_XTOP() {
|
||||
microVU* mVU = mVUx;
|
||||
if (!recPass) {}
|
||||
if (!recPass) { if (!_Ft_) { mVUinfo |= _isNOP; return; } analyzeVIreg2(_Ft_, 1); }
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||||
else {
|
||||
MOVZX32M16toR( gprT1, (uptr)&mVU->regs->vifRegs->top);
|
||||
mVUallocVIb<vuIndex>(gprT1, _Ft_);
|
||||
|
|
@ -961,13 +1015,17 @@ microVUf(void) mVU_XTOP() {
|
|||
|
||||
microVUf(void) mVU_XITOP() {
|
||||
microVU* mVU = mVUx;
|
||||
if (!recPass) {}
|
||||
if (!recPass) { if (!_Ft_) { mVUinfo |= _isNOP; return; } analyzeVIreg2(_Ft_, 1); }
|
||||
else {
|
||||
MOVZX32M16toR( gprT1, (uptr)&mVU->regs->vifRegs->itop );
|
||||
mVUallocVIb<vuIndex>(gprT1, _Ft_);
|
||||
}
|
||||
}
|
||||
|
||||
//------------------------------------------------------------------
|
||||
// XGkick
|
||||
//------------------------------------------------------------------
|
||||
|
||||
microVUt(void) __fastcall mVU_XGKICK_(u32 addr) {
|
||||
microVU* mVU = mVUx;
|
||||
u32 *data = (u32*)(mVU->regs->Mem + (addr&0x3fff));
|
||||
|
|
@ -990,7 +1048,7 @@ microVUf(void) mVU_XGKICK() {
|
|||
}
|
||||
|
||||
//------------------------------------------------------------------
|
||||
// Branches
|
||||
// Branches/Jumps
|
||||
//------------------------------------------------------------------
|
||||
|
||||
microVUf(void) mVU_B() {
|
||||
|
|
|
|||
|
|
@ -66,9 +66,9 @@ declareAllVariables
|
|||
//------------------------------------------------------------------
|
||||
// Helper Macros
|
||||
//------------------------------------------------------------------
|
||||
#define _Ft_ ((mVU->code >> 16) & 0x1F) // The rt part of the instruction register
|
||||
#define _Fs_ ((mVU->code >> 11) & 0x1F) // The rd part of the instruction register
|
||||
#define _Fd_ ((mVU->code >> 6) & 0x1F) // The sa part of the instruction register
|
||||
#define _Ft_ ((mVU->code >> 16) & 0x1F) // The ft/it part of the instruction register
|
||||
#define _Fs_ ((mVU->code >> 11) & 0x1F) // The fs/is part of the instruction register
|
||||
#define _Fd_ ((mVU->code >> 6) & 0x1F) // The fd/id part of the instruction register
|
||||
|
||||
#define _X ((mVU->code>>24) & 0x1)
|
||||
#define _Y ((mVU->code>>23) & 0x1)
|
||||
|
|
@ -144,11 +144,12 @@ declareAllVariables
|
|||
#define mVUbranch mVUallocInfo.branch
|
||||
#define mVUcycles mVUallocInfo.cycles
|
||||
#define mVUstall mVUallocInfo.maxStall
|
||||
#define mVUdivFlag mVUallocInfo.divFlag
|
||||
#define mVUdivFlagT mVUallocInfo.divFlagTimer
|
||||
//#define mVUdivFlag mVUallocInfo.divFlag
|
||||
//#define mVUdivFlagT mVUallocInfo.divFlagTimer
|
||||
#define mVUregs mVUallocInfo.regs
|
||||
#define mVUregsTemp mVUallocInfo.regsTemp
|
||||
#define mVUinfo mVUallocInfo.info[mVUallocInfo.curPC / 2]
|
||||
#define mVUstartPC mVUallocInfo.startPC
|
||||
#define iPC mVUallocInfo.curPC
|
||||
#define xPC ((iPC / 2) * 8)
|
||||
#define incCycles(x) { mVUcycles += x; }
|
||||
|
|
@ -157,6 +158,7 @@ declareAllVariables
|
|||
#define _isBranch (1<<1) // Cur Instruction is a Branch
|
||||
#define _isEOB (1<<2) // End of Block
|
||||
#define _isBdelay (1<<3) // Cur Instruction in Branch Delay slot
|
||||
#define _isSflag (1<<4) // Cur Instruction uses status flag
|
||||
#define _writeQ (1<<5)
|
||||
#define _readQ (1<<6)
|
||||
#define _writeP (1<<7)
|
||||
|
|
@ -177,6 +179,7 @@ declareAllVariables
|
|||
#define isBranch (mVUinfo & (1<<1))
|
||||
#define isEOB (mVUinfo & (1<<2))
|
||||
#define isBdelay (mVUinfo & (1<<3))
|
||||
#define isSflag (mVUinfo & (1<<4))
|
||||
#define writeQ ((mVUinfo >> 5) & 1)
|
||||
#define readQ ((mVUinfo >> 6) & 1)
|
||||
#define writeP ((mVUinfo >> 7) & 1)
|
||||
|
|
@ -200,3 +203,14 @@ declareAllVariables
|
|||
#define isMMX(_VIreg_) (_VIreg_ >= 1 && _VIreg_ <=9)
|
||||
#define mmVI(_VIreg_) (_VIreg_ - 1)
|
||||
|
||||
#ifdef mVUdebug
|
||||
#define mVUdebugStuff1() { \
|
||||
if (curI & _Ibit_) { SysPrintf("microVU: I-bit set!\n"); } \
|
||||
if (curI & _Ebit_) { SysPrintf("microVU: E-bit set!\n"); } \
|
||||
if (curI & _Mbit_) { SysPrintf("microVU: M-bit set!\n"); } \
|
||||
if (curI & _Dbit_) { SysPrintf("microVU: D-bit set!\n"); } \
|
||||
if (curI & _Tbit_) { SysPrintf("microVU: T-bit set!\n"); } \
|
||||
}
|
||||
#else
|
||||
#define mVUdebugStuff1() {}
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue