mirror of https://github.com/PCSX2/pcsx2.git
microVU:
- Fixed up some code so blocks are recompiled less often. - Tweaked flag code. - Minor changes... git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1151 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
cottonvibes
parent
0005b749b5
commit
912185348e
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@ -117,10 +117,6 @@ microVUt(void) mVUclear(u32 addr, u32 size) {
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microVU* mVU = mVUx;
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memset(&mVU->prog.lpState, 0, sizeof(mVU->prog.lpState));
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mVU->prog.cleared = 1; // Next execution searches/creates a new microprogram
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// Note: It might be better to copy old recompiled blocks to the new microprogram rec data
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// however, if games primarily do big writes, its probably not worth it.
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// The cost of invalidating bad blocks is also kind of expensive, which is another reason
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// that its probably not worth it...
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}
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//------------------------------------------------------------------
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@ -49,16 +49,17 @@ public:
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}
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microBlock* search(microRegInfo* pState) {
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if (listSize < 0) return NULL;
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//if (blockList[0].pState.needExactMatch) { // Needs Detailed Search (Exact Match of Pipeline State)
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if (blockList[0].pState.needExactMatch) { // Needs Detailed Search (Exact Match of Pipeline State)
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for (int i = 0; i <= listSize; i++) {
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if (!memcmp(pState, &blockList[i].pState, sizeof(microRegInfo) - 1)) return &blockList[i];
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}
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/*}
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}
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else { // Can do Simple Search (Only Matches the Important Pipeline Stuff)
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for (int i = 0; i <= listSize; i++) {
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if ((blockList[i].pState.q == pState->q) && (blockList[i].pState.p == pState->p)) { return &blockList[i]; }
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if ((blockList[i].pState.q == pState->q) && (blockList[i].pState.p == pState->p)
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&& (blockList[i].pState.clip == pState->clip)) { return &blockList[i]; }
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}
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}*/
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}
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return NULL;
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}
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};
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@ -90,7 +91,7 @@ struct microVU {
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u32 index; // VU Index (VU0 or VU1)
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u32 microSize; // VU Micro Memory Size
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u32 progSize; // VU Micro Program Size (microSize/4)
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static const u32 cacheSize = 0x800000; // VU Cache Size
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static const u32 cacheSize = 0xb00000; // VU Cache Size
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microProgManager<0x4000> prog; // Micro Program Data
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@ -29,6 +29,10 @@ union regInfo {
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};
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};
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#if defined(_MSC_VER)
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#pragma pack(push, 1)
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#pragma warning(disable:4996)
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#endif
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struct microRegInfo {
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regInfo VF[32];
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u8 VI[32];
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@ -38,7 +42,12 @@ struct microRegInfo {
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u8 xgkick;
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u8 clip;
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u8 needExactMatch; // If set, block needs an exact match of pipeline state (needs to be last byte in struct)
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#if defined(_MSC_VER)
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};
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#pragma pack(pop)
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#else
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} __attribute__((packed));
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#endif
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struct microTempRegInfo {
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regInfo VF[2]; // Holds cycle info for Fd, VF[0] = Upper Instruction, VF[1] = Lower Instruction
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@ -59,6 +68,7 @@ struct microBlock {
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template<u32 pSize>
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struct microAllocInfo {
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microBlock* pBlock; // Pointer to a block in mVUblocks
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microBlock block; // Block/Pipeline info
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microTempRegInfo regsTemp; // Temp Pipeline info (used so that new pipeline info isn't conflicting between upper and lower instructions in the same cycle)
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u8 branch; // 0 = No Branch, 1 = B. 2 = BAL, 3~8 = Conditional Branches, 9 = JALR, 10 = JR
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@ -665,13 +665,17 @@ microVUt(void) mVUallocFMAC26b(int& ACCw, int& ACCr) {
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// Flag Allocators
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//------------------------------------------------------------------
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#define getFlagReg(regX, fInst) { \
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switch (fInst) { \
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case 0: regX = gprF0; break; \
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case 1: regX = gprF1; break; \
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case 2: regX = gprF2; break; \
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case 3: regX = gprF3; break; \
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} \
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#define getFlagReg(regX, fInst) { \
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switch (fInst) { \
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case 0: regX = gprF0; break; \
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case 1: regX = gprF1; break; \
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case 2: regX = gprF2; break; \
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case 3: regX = gprF3; break; \
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default: \
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Console::Error("microVU: Flag Instance Error (fInst = %d)", params fInst); \
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regX = gprF0; \
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break; \
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} \
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}
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microVUt(void) mVUallocSFLAGa(int reg, int fInstance) {
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@ -257,7 +257,7 @@ microVUt(void) mVUanalyzeSflag(int It) {
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if (!It) { mVUinfo |= _isNOP; }
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else { // Sets _isSflag at instruction that FSxxx opcode reads it's status flag from
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mVUinfo |= _swapOps;
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if (mVUcount < 4) { mVUregs.needExactMatch = 1; }
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if (mVUcount < 4) { mVUpBlock->pState.needExactMatch = 1; }
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if (mVUcount >= 1) { incPC2(-2); mVUinfo |= _isSflag; incPC2(2); }
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// Note: _isSflag is used for status flag optimizations.
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// Do to stalls, it can only be set one instruction prior to the status flag read instruction
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@ -285,7 +285,7 @@ microVUt(void) mVUanalyzeMflag(int Is, int It) {
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if (!It) { mVUinfo |= _isNOP; }
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else { // Need set _doMac for 4 previous Ops (need to do all 4 because stalls could change the result needed)
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mVUinfo |= _swapOps;
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if (mVUcount < 4) { mVUregs.needExactMatch = 1; }
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if (mVUcount < 4) { mVUpBlock->pState.needExactMatch = 1; }
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int curPC = iPC;
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for (int i = mVUcount, j = 0; i > 1; i--, j++) {
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incPC2(-2);
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@ -297,6 +297,15 @@ microVUt(void) mVUanalyzeMflag(int Is, int It) {
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analyzeVIreg2(It, 1);
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}
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//------------------------------------------------------------------
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// Cflag - Clip Flag Opcodes
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//------------------------------------------------------------------
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microVUt(void) mVUanalyzeCflag() {
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microVU* mVU = mVUx;
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if (mVUcount < 4) { mVUpBlock->pState.needExactMatch = 1; }
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}
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//------------------------------------------------------------------
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// XGkick
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//------------------------------------------------------------------
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@ -127,6 +127,12 @@ microVUt(void) mVUsetFlags(int* bStatus, int* bMac) {
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mVUcount = xCount; // Restore count
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mVUregs.clip = xClip&3; // Note: Clip timing isn't cycle-accurate between block linking; but hopefully doesn't matter
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// Temp Hack-fix until flag-algorithm rewrite
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for (int i = 0; i < 4; i++) {
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bStatus[i] = 0;
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bMac[i] = 0;
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}
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// Setup Last 4 instances of Status/Mac flags (needed for accurate block linking)
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iPC = endPC;
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for (int i = 3, j = 3, ii = 1, jj = 1; aCount > 0; ii++, jj++, aCount--) {
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@ -238,20 +244,17 @@ microVUt(void) mVUdivSet() {
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if (doDivFlag) {
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getFlagReg(flagReg1, fsInstance);
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if (!doStatus) { getFlagReg(flagReg2, fpsInstance); MOV16RtoR(flagReg1, flagReg2); }
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//MOV32RtoR(gprT1, flagReg1);
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//AND32ItoR(gprT1, 0xffff0fcf);
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//OR32MtoR (gprT1, (uptr)&mVU->divFlag);
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//MOV32RtoR(flagReg1, gprT1);
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AND16ItoR(flagReg1, 0x0fcf);
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OR32MtoR (flagReg1, (uptr)&mVU->divFlag);
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}
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}
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microVUt(void) mVUendProgram() {
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microVUt(void) mVUendProgram(int fStatus, int fMac) {
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microVU* mVU = mVUx;
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incCycles(100); // Ensures Valid P/Q instances (And sets all cycle data to 0)
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mVUcycles -= 100;
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// Save P/Q Regs
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if (mVU->q) { SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, 0xe5); }
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SSE_MOVSS_XMM_to_M32((uptr)&mVU->regs->VI[REG_Q].UL, xmmPQ);
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if (vuIndex) {
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@ -259,6 +262,15 @@ microVUt(void) mVUendProgram() {
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SSE_MOVSS_XMM_to_M32((uptr)&mVU->regs->VI[REG_P].UL, xmmPQ);
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}
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// Save Flag Instances
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getFlagReg(fStatus, fStatus);
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getFlagReg(fMac, fMac);
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MOV32RtoR(gprT1, fStatus);
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AND32ItoR(gprT1, 0xffff);
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SHR32ItoR(fMac, 16);
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MOV32RtoM((uptr)&mVU->regs->VI[REG_STATUS_FLAG].UL, gprT1);
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MOV32RtoM((uptr)&mVU->regs->VI[REG_MAC_FLAG].UL, fMac);
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//memcpy_fast(&pBlock->pStateEnd, &mVUregs, sizeof(microRegInfo));
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//MOV32ItoM((uptr)&mVU->prog.lpState, (int)&mVUblock.pState); // Save pipeline state (clipflag instance)
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//AND32ItoM((uptr)&VU0.VI[REG_VPU_STAT].UL, (vuIndex ? ~0x100 : ~0x001)); // VBS0/VBS1 flag
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@ -273,7 +285,7 @@ microVUt(void) mVUtestCycles() {
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iPC = mVUstartPC;
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CMP32ItoM((uptr)&mVU->cycles, 0);
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u8* jmp8 = JG8(0);
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mVUendProgram<vuIndex>();
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mVUendProgram<vuIndex>(0, 0);
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x86SetJ8(jmp8);
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SUB32ItoM((uptr)&mVU->cycles, mVUcycles);
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}
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@ -304,6 +316,7 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) {
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memcpy_fast(&mVUregs, (microRegInfo*)pState, sizeof(microRegInfo)); // Loads up Pipeline State Info
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mVUblock.x86ptrStart = thisPtr;
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pBlock = mVUblocks[startPC/8]->add(&mVUblock); // Add this block to block manager
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mVUpBlock = pBlock;
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for (int branch = 0;; ) {
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incPC(1);
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@ -330,6 +343,9 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) {
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int bStatus[4]; int bMac[4];
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mVUsetFlags<vuIndex>(bStatus, bMac);
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mVUtestCycles<vuIndex>();
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//SysPrintf("bS[0] = %08x, bS[1] = %08x, bS[2] = %08x, bS[3] = %08x\n", bStatus[0], bStatus[1], bStatus[2], bStatus[3]);
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//SysPrintf("bM[0] = %08x, bM[1] = %08x, bM[2] = %08x, bM[3] = %08x\n", bMac[0], bMac[1], bMac[2], bMac[3]);
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//SysPrintf("mVUcount = %d\n", mVUcount);
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// Second Pass
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iPC = mVUstartPC;
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@ -414,7 +430,7 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) {
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if (x == (vuIndex?(0x3fff/8):(0xfff/8))) { mVUprint("microVU: Possible infinite compiling loop!"); }
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// Do E-bit end stuff here
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mVUendProgram<vuIndex>();
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mVUendProgram<vuIndex>(bStatus[3], bMac[3]);
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return thisPtr; //ToDo: Save pipeline state?
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}
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@ -86,20 +86,14 @@ microVUt(void) mVUdispatcherB() {
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eeMXCSR = g_sseMXCSR;
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SSE_LDMXCSR((uptr)&eeMXCSR);
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// Save Regs
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MOV32RtoR(gprT1, gprF0); // ToDo: Ensure Correct Flag instances
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AND32ItoR(gprT1, 0xffff);
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SHR32ItoR(gprF0, 16);
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MOV32RtoM((uptr)&mVU->regs->VI[REG_R].UL, gprR);
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MOV32RtoM((uptr)&mVU->regs->VI[REG_STATUS_FLAG].UL, gprT1);
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MOV32RtoM((uptr)&mVU->regs->VI[REG_MAC_FLAG].UL, gprF0);
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// Save Regs (Other Regs Saved in mVUcompile)
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MOV32RtoM((uptr)&mVU->regs->VI[REG_R].UL, gprR);
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SSE_MOVAPS_XMM_to_M128((uptr)&mVU->regs->ACC.UL[0], xmmACC);
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for (int i = 1; i < 16; i++) {
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if (isMMX(i)) { MOVDMMXtoM((uptr)&mVU->regs->VI[i].UL, mmVI(i)); }
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}
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SSE_MOVAPS_XMM_to_M128((uptr)&mVU->regs->ACC.UL[0], xmmACC);
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// __fastcall = The first two DWORD or smaller arguments are passed in ECX and EDX registers; all other arguments are passed right to left.
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if (!vuIndex) { CALLFunc((uptr)mVUcleanUpVU0); }
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else { CALLFunc((uptr)mVUcleanUpVU1); }
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@ -110,8 +104,6 @@ microVUt(void) mVUdispatcherB() {
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POP32R(EBP);
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POP32R(EBX);
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//write8(0xcc);
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if (isMMX(1)) EMMS();
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RET();
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@ -431,6 +431,7 @@ microVUf(void) mVU_ESUM() {
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microVUf(void) mVU_FCAND() {
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microVU* mVU = mVUx;
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pass1 { mVUanalyzeCflag<vuIndex>(); }
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pass2 {
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mVUallocCFLAGa<vuIndex>(gprT1, fvcInstance);
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AND32ItoR(gprT1, _Imm24_);
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@ -443,6 +444,7 @@ microVUf(void) mVU_FCAND() {
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microVUf(void) mVU_FCEQ() {
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microVU* mVU = mVUx;
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pass1 { mVUanalyzeCflag<vuIndex>(); }
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pass2 {
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mVUallocCFLAGa<vuIndex>(gprT1, fvcInstance);
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XOR32ItoR(gprT1, _Imm24_);
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@ -455,6 +457,7 @@ microVUf(void) mVU_FCEQ() {
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microVUf(void) mVU_FCGET() {
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microVU* mVU = mVUx;
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pass1 { mVUanalyzeCflag<vuIndex>(); }
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pass2 {
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mVUallocCFLAGa<vuIndex>(gprT1, fvcInstance);
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AND32ItoR(gprT1, 0xfff);
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@ -465,6 +468,7 @@ microVUf(void) mVU_FCGET() {
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microVUf(void) mVU_FCOR() {
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microVU* mVU = mVUx;
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pass1 { mVUanalyzeCflag<vuIndex>(); }
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pass2 {
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mVUallocCFLAGa<vuIndex>(gprT1, fvcInstance);
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OR32ItoR(gprT1, _Imm24_);
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@ -152,6 +152,7 @@ declareAllVariables
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#define mVUbranch mVUallocInfo.branch
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#define mVUcycles mVUallocInfo.cycles
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#define mVUcount mVUallocInfo.count
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#define mVUpBlock mVUallocInfo.pBlock
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#define mVUblock mVUallocInfo.block
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#define mVUregs mVUallocInfo.block.pState
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#define mVUregsTemp mVUallocInfo.regsTemp
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@ -263,5 +264,5 @@ declareAllVariables
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#define mVUcacheCheck(ptr, start, limit) { \
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uptr diff = ptr - start; \
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if (diff >= limit) { Console::Error("microVU Error: Program went over it's cache limit. Size = %x", params diff); } \
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if (diff >= limit) { Console::Error("microVU Error: Program went over its cache limit. Size = 0x%x", params diff); } \
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}
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