mirror of https://github.com/PCSX2/pcsx2.git
SPU2-X: Fixed some more major bugs and typos; most sound *should* be working again now. Added a hackfix for a crash in the BIOS cased by what *should* be correct handling of IRQAs.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1947 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
Jake.Stine
parent
d386ce0ac6
commit
910669f937
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@ -128,15 +128,15 @@ void V_Core::StartADMAWrite(u16 *pMem, u32 sz)
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if(MsgAutoDMA()) ConLog(" * SPU2: DMA%c AutoDMA Transfer of %d bytes to %x (%02x %x %04x).\n",
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GetDmaIndexChar(), size<<1, TSA, DMABits, AutoDMACtrl, (~Regs.ATTR)&0x7fff);
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InputDataProgress=0;
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InputDataProgress = 0;
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if((AutoDMACtrl&(Index+1))==0)
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{
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TSA=0x2000+(Index<<10);
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DMAICounter=size;
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TSA = 0x2000 + (Index<<10);
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DMAICounter = size;
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}
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else if(size>=512)
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{
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InputDataLeft=size;
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InputDataLeft = size;
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if(AdmaInProgress==0)
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{
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#ifdef PCM24_S1_INTERLEAVE
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@ -149,26 +149,43 @@ void V_Core::StartADMAWrite(u16 *pMem, u32 sz)
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AutoDMAReadBuffer(Index,0);
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}
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#else
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if(((PlayMode&4)==4)&&(Index==0))
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if( ((PlayMode&4)==4) && (Index==0) )
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Cores[0].InputPos=0;
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AutoDMAReadBuffer(0);
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#endif
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if(size==512)
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DMAICounter=size;
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DMAICounter = size;
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}
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AdmaInProgress=1;
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AdmaInProgress = 1;
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}
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else
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{
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InputDataLeft=0;
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DMAICounter=1;
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InputDataLeft = 0;
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DMAICounter = 1;
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}
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TADR=MADR+(size<<1);
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TADR = MADR + (size<<1);
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}
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// HACKFIX: The BIOS breaks if we check the IRQA for both cores when issuing DMA writes. The
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// breakage is a null psxRegs.pc being loaded form some memory address (haven't traced it deeper
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// yet). We get around it by only checking the current core's IRQA, instead of doing the
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// *correct* thing and checking both. This might break some games, but having a working BIOS
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// is more important for now, until a proper fix can be uncovered.
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//
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// This problem might be caused by bad DMA timings in the IOP or a lack of proper IRQ
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// handling by the Effects Processor. After those are implemented, let's hope it gets
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// magically fixed?
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//
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// Note: This appears to affect DMA Writes only, so DMA Read DMAs are left intact (both core
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// IRQAs are tested). Very few games use DMA reads tho, so it could just be a case of "works
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// by the grace of not being used."
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//
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#define NO_BIOS_HACKFIX 0 // set to 1 to disable the hackfix
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void V_Core::PlainDMAWrite(u16 *pMem, u32 size)
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{
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// Perform an alignment check.
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@ -239,10 +256,33 @@ void V_Core::PlainDMAWrite(u16 *pMem, u32 size)
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//memset( pcm_cache_flags, 0, endpt2 );
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// Emulation Grayarea: Should addresses wrap around to zero, or wrap around to
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// 0x2800? Hard to know for usre (almost no games depend on this)
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// 0x2800? Hard to know for sure (almost no games depend on this)
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memcpy( GetMemPtr( 0 ), &pMem[buff1size], buff2end*2 );
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TDA = (buff2end+1) & 0xfffff;
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// Flag interrupt? If IRQA occurs between start and dest, flag it.
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// Important: Test both core IRQ settings for either DMA!
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// Note: Because this buffer wraps, we use || instead of &&
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#if NO_BIOS_HACKFIX
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for( int i=0; i<2; i++ )
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{
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// Note: (start is inclusive, dest exclusive -- fixes DMC1 FMVs)
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if( Cores[i].IRQEnable && (Cores[i].IRQA >= TSA) || (Cores[i].IRQA < TDA) )
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{
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Spdif.Info = 4 << i;
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SetIrqCall();
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}
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}
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#else
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if( IRQEnable && (IRQA >= TSA) || (IRQA < TDA) )
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{
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Spdif.Info = 4 << Index;
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SetIrqCall();
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}
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#endif
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}
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else
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{
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@ -250,30 +290,28 @@ void V_Core::PlainDMAWrite(u16 *pMem, u32 size)
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// Just set the TDA and check for an IRQ...
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TDA = buff1end;
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}
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// Flag interrupt? If IRQA occurs between start and dest, flag it.
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// Important: Test both core IRQ settings for either DMA!
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// Flag interrupt? If IRQA occurs between start and dest, flag it.
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// Important: Test both core IRQ settings for either DMA!
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for( int i=0; i<2; i++ )
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{
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// Note: (start is inclusive, dest exclusive -- fixes DMC1 FMVs)
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if( Cores[i].IRQEnable && (Cores[i].IRQA >= Cores[i].TSA) && (Cores[i].IRQA < Cores[i].TDA) )
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#if NO_BIOS_HACKFIX
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for( int i=0; i<2; i++ )
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{
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Spdif.Info = 4 << i;
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SetIrqCall();
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// Note: (start is inclusive, dest exclusive -- fixes DMC1 FMVs)
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if( Cores[i].IRQEnable && (Cores[i].IRQA >= TSA) && (Cores[i].IRQA < TDA) )
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{
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Spdif.Info = 4 << i;
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SetIrqCall();
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}
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}
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}
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if(IRQEnable)
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{
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if( ( IRQA >= TSA ) && ( IRQA < TDA ) )
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#else
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if( IRQEnable && (IRQA >= TSA) && (IRQA < TDA) )
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{
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Spdif.Info = 4 << Index;
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SetIrqCall();
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}
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#endif
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}
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TSA = TDA & 0xFFFF0;
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@ -308,6 +346,19 @@ void V_Core::DoDMAread(u16* pMem, u32 size)
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memcpy( &pMem[buff1size], GetMemPtr( 0 ), buff2end*2 );
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TDA = (buff2end+0x20) & 0xfffff;
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// Flag interrupt? If IRQA occurs between start and dest, flag it.
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// Important: Test both core IRQ settings for either DMA!
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// Note: Because this buffer wraps, we use || instead of &&
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for( int i=0; i<2; i++ )
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{
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if( Cores[i].IRQEnable && (Cores[i].IRQA >= TSA) || (Cores[i].IRQA < TDA) )
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{
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Spdif.Info = 4 << i;
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SetIrqCall();
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}
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}
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}
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else
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{
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@ -315,17 +366,17 @@ void V_Core::DoDMAread(u16* pMem, u32 size)
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// Just set the TDA and check for an IRQ...
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TDA = (buff1end + 0x20) & 0xfffff;
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}
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// Flag interrupt? If IRQA occurs between start and dest, flag it.
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// Important: Test both core IRQ settings for either DMA!
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// Flag interrupt? If IRQA occurs between start and dest, flag it.
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// Important: Test both core IRQ settings for either DMA!
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for( int i=0; i<2; i++ )
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{
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if( Cores[i].IRQEnable && (Cores[i].IRQA >= Cores[i].TSA) && (Cores[i].IRQA < Cores[i].TDA) )
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for( int i=0; i<2; i++ )
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{
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Spdif.Info = 4 << i;
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SetIrqCall();
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if( Cores[i].IRQEnable && (Cores[i].IRQA >= TSA) && (Cores[i].IRQA < TDA) )
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{
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Spdif.Info = 4 << i;
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SetIrqCall();
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}
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}
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}
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@ -177,8 +177,6 @@ EXPORT_C_(void) CALLBACK SPU2writeDMA4Mem(u16* pMem, u32 size) // size now in 16
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EXPORT_C_(void) CALLBACK SPU2interruptDMA4()
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{
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if( cyclePtr != NULL ) TimeUpdate( *cyclePtr );
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FileLog("[%10d] SPU2 interruptDMA4\n",Cycles);
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Cores[0].Regs.STATX |= 0x80;
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//Cores[0].Regs.ATTR &= ~0x30;
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@ -206,8 +204,6 @@ EXPORT_C_(void) CALLBACK SPU2writeDMA7Mem(u16* pMem, u32 size)
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EXPORT_C_(void) CALLBACK SPU2interruptDMA7()
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{
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if( cyclePtr != NULL ) TimeUpdate( *cyclePtr );
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FileLog("[%10d] SPU2 interruptDMA7\n",Cycles);
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Cores[1].Regs.STATX |= 0x80;
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//Cores[1].Regs.ATTR &= ~0x30;
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@ -266,10 +262,8 @@ EXPORT_C_(s32) SPU2init()
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memset(spu2regs, 0, 0x010000);
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memset(_spu2mem, 0, 0x200000);
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Cores[0].Index = 0;
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Cores[1].Index = 1;
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Cores[0].Reset();
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Cores[1].Reset();
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Cores[0].Reset(0);
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Cores[1].Reset(1);
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DMALogOpen();
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@ -18,6 +18,177 @@
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#include "Global.h"
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#include "dma.h"
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#if 0
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static void __fastcall __ReadInput( uint core, StereoOut32& PData )
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{
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V_Core& thiscore( Cores[core] );
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if((thiscore.AutoDMACtrl&(core+1))==(core+1))
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{
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s32 tl,tr;
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if((core==1)&&((PlayMode&8)==8))
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{
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thiscore.InputPos&=~1;
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// CDDA mode
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// Source audio data is 32 bits.
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// We don't yet have the capability to handle this high res input data
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// so we just downgrade it to 16 bits for now.
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#ifdef PCM24_S1_INTERLEAVE
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*PData.Left=*(((s32*)(thiscore.ADMATempBuffer+(thiscore.InputPos<<1))));
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*PData.Right=*(((s32*)(thiscore.ADMATempBuffer+(thiscore.InputPos<<1)+2)));
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#else
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s32 *pl=(s32*)&(thiscore.ADMATempBuffer[thiscore.InputPos]);
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s32 *pr=(s32*)&(thiscore.ADMATempBuffer[thiscore.InputPos+0x200]);
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PData.Left = *pl;
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PData.Right = *pr;
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#endif
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PData.Left >>= 2; //give 30 bit data (SndOut downsamples the rest of the way)
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PData.Right >>= 2;
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thiscore.InputPos+=2;
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if((thiscore.InputPos==0x100)||(thiscore.InputPos>=0x200)) {
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thiscore.AdmaInProgress=0;
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if(thiscore.InputDataLeft>=0x200)
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{
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u8 k=thiscore.InputDataLeft>=thiscore.InputDataProgress;
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#ifdef PCM24_S1_INTERLEAVE
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thiscore.AutoDMAReadBuffer(1);
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#else
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thiscore.AutoDMAReadBuffer(0);
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#endif
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thiscore.AdmaInProgress=1;
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thiscore.TSA=(core<<10)+thiscore.InputPos;
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if (thiscore.InputDataLeft<0x200)
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{
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FileLog("[%10d] AutoDMA%c block end.\n",Cycles, (core==0)?'4':'7');
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if( IsDevBuild )
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{
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if(thiscore.InputDataLeft>0)
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{
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if(MsgAutoDMA()) ConLog("WARNING: adma buffer didn't finish with a whole block!!\n");
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}
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}
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thiscore.InputDataLeft=0;
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thiscore.DMAICounter=1;
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}
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}
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thiscore.InputPos&=0x1ff;
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}
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}
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else if((core==0)&&((PlayMode&4)==4))
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{
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thiscore.InputPos&=~1;
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s32 *pl=(s32*)&(thiscore.ADMATempBuffer[thiscore.InputPos]);
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s32 *pr=(s32*)&(thiscore.ADMATempBuffer[thiscore.InputPos+0x200]);
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PData.Left = *pl;
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PData.Right = *pr;
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thiscore.InputPos+=2;
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if(thiscore.InputPos>=0x200) {
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thiscore.AdmaInProgress=0;
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if(thiscore.InputDataLeft>=0x200)
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{
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u8 k=thiscore.InputDataLeft>=thiscore.InputDataProgress;
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thiscore.AutoDMAReadBuffer(0);
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thiscore.AdmaInProgress=1;
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thiscore.TSA=(core<<10)+thiscore.InputPos;
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if (thiscore.InputDataLeft<0x200)
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{
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FileLog("[%10d] Spdif AutoDMA%c block end.\n",Cycles, (core==0)?'4':'7');
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if( IsDevBuild )
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{
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if(thiscore.InputDataLeft>0)
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{
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if(MsgAutoDMA()) ConLog("WARNING: adma buffer didn't finish with a whole block!!\n");
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}
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}
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thiscore.InputDataLeft=0;
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thiscore.DMAICounter=1;
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}
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}
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thiscore.InputPos&=0x1ff;
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}
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}
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else
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{
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if((core==1)&&((PlayMode&2)!=0))
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{
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tl=0;
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tr=0;
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}
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else
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{
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// Using the temporary buffer because this area gets overwritten by some other code.
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//*PData.Left = (s32)*(s16*)(spu2mem+0x2000+(core<<10)+thiscore.InputPos);
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//*PData.Right = (s32)*(s16*)(spu2mem+0x2200+(core<<10)+thiscore.InputPos);
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tl = (s32)thiscore.ADMATempBuffer[thiscore.InputPos];
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tr = (s32)thiscore.ADMATempBuffer[thiscore.InputPos+0x200];
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}
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PData.Left = tl;
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PData.Right = tr;
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thiscore.InputPos++;
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if((thiscore.InputPos==0x100)||(thiscore.InputPos>=0x200)) {
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thiscore.AdmaInProgress=0;
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if(thiscore.InputDataLeft>=0x200)
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{
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u8 k=thiscore.InputDataLeft>=thiscore.InputDataProgress;
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thiscore.AutoDMAReadBuffer(0);
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thiscore.AdmaInProgress=1;
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thiscore.TSA=(core<<10)+thiscore.InputPos;
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if (thiscore.InputDataLeft<0x200)
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{
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thiscore.AutoDMACtrl |= ~3;
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if( IsDevBuild )
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{
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FileLog("[%10d] AutoDMA%c block end.\n",Cycles, (core==0)?'4':'7');
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if(thiscore.InputDataLeft>0)
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{
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if(MsgAutoDMA()) ConLog("WARNING: adma buffer didn't finish with a whole block!!\n");
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}
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}
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thiscore.InputDataLeft = 0;
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thiscore.DMAICounter = 1;
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}
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}
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thiscore.InputPos&=0x1ff;
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}
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}
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}
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else
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{
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PData.Left = 0;
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PData.Right = 0;
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}
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}
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#endif
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// CDDA mode - Source audio data is 32 bits.
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// PS2 note: Very! few PS2 games use this mode. Some PSX games used it, however no
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// *known* PS2 game does since it was likely only available if the game was recorded to CD
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@ -49,8 +220,8 @@ __forceinline StereoOut32 V_Core::ReadInput_HiFi( bool isCDDA )
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}
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InputPos += 2;
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//if( (InputPos==0x100) || (InputPos>=0x200) ) // CDDA mode?
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if( InputPos >= 0x200 )
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if( (InputPos==0x100) || (InputPos>=0x200) ) // CDDA mode?
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//if( InputPos >= 0x200 )
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{
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AdmaInProgress = 0;
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if(InputDataLeft >= 0x200)
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@ -88,6 +259,10 @@ __forceinline StereoOut32 V_Core::ReadInput_HiFi( bool isCDDA )
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StereoOut32 V_Core::ReadInput()
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{
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/*StereoOut32 retval2;
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__ReadInput( Index, retval2 );
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return retval2;*/
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if((AutoDMACtrl&(Index+1)) != (Index+1))
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return StereoOut32();
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@ -432,11 +432,12 @@ struct V_Core
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// V_Core Methods
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// ----------------------------------------------------------------------------------
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V_Core() : Index( -1 ) {} // uninitialized constructor
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// uninitialized constructor
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V_Core() : Index( -1 ), DMAPtr( NULL ) {}
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V_Core( int idx ); // our badass constructor
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virtual ~V_Core() throw();
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void Reset();
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void Reset( int index );
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void UpdateEffectsBufferSize();
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s32 EffectsBufferIndexer( s32 offset ) const;
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@ -107,11 +107,11 @@ V_Core::~V_Core() throw()
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}*/
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}
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void V_Core::Reset()
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void V_Core::Reset( int index )
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{
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memset( this, 0, sizeof(V_Core) );
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const int c = Index;
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const int c = Index = index;
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|
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Regs.STATX = 0;
|
||||
Regs.ATTR = 0;
|
||||
|
|
@ -276,7 +276,7 @@ u32 TicksThread = 0;
|
|||
|
||||
__forceinline void TimeUpdate(u32 cClocks)
|
||||
{
|
||||
u32 dClocks = cClocks-lClocks;
|
||||
s32 dClocks = cClocks-lClocks;
|
||||
|
||||
// [Air]: Sanity Check
|
||||
// If for some reason our clock value seems way off base, just mix
|
||||
|
|
@ -306,7 +306,7 @@ __forceinline void TimeUpdate(u32 cClocks)
|
|||
Cores[0].InitDelay--;
|
||||
if(Cores[0].InitDelay==0)
|
||||
{
|
||||
Cores[0].Reset();
|
||||
Cores[0].Reset(0);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -315,7 +315,7 @@ __forceinline void TimeUpdate(u32 cClocks)
|
|||
Cores[1].InitDelay--;
|
||||
if(Cores[1].InitDelay==0)
|
||||
{
|
||||
Cores[1].Reset();
|
||||
Cores[1].Reset(1);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -824,7 +824,7 @@ static void __fastcall RegWrite_Core( u16 value )
|
|||
|
||||
for( int i=0; i<2; i++ )
|
||||
{
|
||||
if(Cores[i].IRQEnable && (Cores[i].IRQA == Cores[i].TSA))
|
||||
if(Cores[i].IRQEnable && (Cores[i].IRQA == thiscore.TSA))
|
||||
{
|
||||
Spdif.Info = 4 << i;
|
||||
SetIrqCall();
|
||||
|
|
@ -851,7 +851,7 @@ static void __fastcall RegWrite_Core( u16 value )
|
|||
}
|
||||
else
|
||||
{
|
||||
thiscore.Reset();
|
||||
thiscore.Reset(thiscore.Index);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue