diff --git a/pcsx2/IopCommon.h b/pcsx2/IopCommon.h
index 4c10164b75..75d83f5774 100644
--- a/pcsx2/IopCommon.h
+++ b/pcsx2/IopCommon.h
@@ -32,3 +32,6 @@ static const s64 PSXCLK = 36864000;	/* 36.864 Mhz */
 //#define PSXCLK	 9216000	/* 36.864 Mhz */
 //#define PSXCLK	186864000	/* 36.864 Mhz */
 
+// Uncomment to make pcsx2 print each spu2 interrupt it receives
+//#define SPU2IRQTEST
+
diff --git a/pcsx2/IopDma.cpp b/pcsx2/IopDma.cpp
index 53c59619d4..8b1786fc60 100644
--- a/pcsx2/IopDma.cpp
+++ b/pcsx2/IopDma.cpp
@@ -84,6 +84,9 @@ void psxDma4(u32 madr, u32 bcr, u32 chcr)		// SPU2's Core 0
 
 int psxDma4Interrupt()
 {
+	#ifdef SPU2IRQTEST
+		Console.Warning("psxDma4Interrupt()");
+	#endif
 	HW_DMA4_CHCR &= ~0x01000000;
 	psxDmaInterrupt(4);
 	iopIntcIrq(9);
@@ -92,6 +95,9 @@ int psxDma4Interrupt()
 
 void spu2DMA4Irq()
 {
+	#ifdef SPU2IRQTEST
+		Console.Warning("spu2DMA4Irq()");
+	#endif
 	SPU2interruptDMA4();
 	HW_DMA4_CHCR &= ~0x01000000;
 	psxDmaInterrupt(4);
@@ -104,6 +110,9 @@ void psxDma7(u32 madr, u32 bcr, u32 chcr)		// SPU2's Core 1
 
 int psxDma7Interrupt()
 {
+	#ifdef SPU2IRQTEST
+		Console.Warning("psxDma7Interrupt()");
+	#endif
 	HW_DMA7_CHCR &= ~0x01000000;
 	psxDmaInterrupt2(0);
 	return 1;
@@ -112,6 +121,9 @@ int psxDma7Interrupt()
 
 void spu2DMA7Irq()
 {
+	#ifdef SPU2IRQTEST
+		Console.Warning("spu2DMA7Irq()");
+	#endif
 	SPU2interruptDMA7();
 	HW_DMA7_CHCR &= ~0x01000000;
 	psxDmaInterrupt2(0);
diff --git a/pcsx2/IopIrq.cpp b/pcsx2/IopIrq.cpp
index 762adf7322..e0ffe21683 100644
--- a/pcsx2/IopIrq.cpp
+++ b/pcsx2/IopIrq.cpp
@@ -52,6 +52,9 @@ void fwIrq()
 
 void spu2Irq()
 {
+	#ifdef SPU2IRQTEST
+		Console.Warning("spu2Irq");
+	#endif
 	iopIntcIrq(9);
 	hwIntcIrq(INTC_SBUS);
 }
diff --git a/pcsx2/x86/ix86-32/iR5900-32.cpp b/pcsx2/x86/ix86-32/iR5900-32.cpp
index a0d3e759f7..190e2ec593 100644
--- a/pcsx2/x86/ix86-32/iR5900-32.cpp
+++ b/pcsx2/x86/ix86-32/iR5900-32.cpp
@@ -1198,7 +1198,7 @@ void recompileNextInstruction(int delayslot)
 	const OPCODE& opcode = GetCurrentInstruction();
 
  	//pxAssert( !(g_pCurInstInfo->info & EEINSTINFO_NOREC) );
-
+	//Console.Warning("opcode name = %s, it's cycles = %d\n",opcode.Name,opcode.cycles);
 	// if this instruction is a jump or a branch, exit right away
 	if( delayslot ) {
 		switch(_Opcode_) {
diff --git a/plugins/spu2-x/src/spu2sys.cpp b/plugins/spu2-x/src/spu2sys.cpp
index 4ca6aedca5..4762d999f5 100644
--- a/plugins/spu2-x/src/spu2sys.cpp
+++ b/plugins/spu2-x/src/spu2sys.cpp
@@ -1429,6 +1429,15 @@ static RegWriteHandler * const tbl_reg_writes[0x401] =
 
 __forceinline void SPU2_FastWrite( u32 rmem, u16 value )
 {
+	// Check for these 2 adresses and schedule an interrupt when they get written with 0x3fff.
+	// This is what peops spu2 does, and it helps silent hill origins start a bit more stuff.
+	if (value == 0x3fff && (rmem == 0x1f900500 || rmem == 0x1f900400) ) {
+		// no idea which core ><
+		Spdif.Info |= 4 << 0; 
+		SetIrqCall();
+		ConLog( "SPU2-X: Schedule IRQ for odd register write. rmem = %x , value = %x \n", rmem, value);
+	}
+
 	tbl_reg_writes[(rmem&0x7ff)/2]( value );
 }