From 8d0f6701b7cca96e544e2042b0472d0d43f4d2a0 Mon Sep 17 00:00:00 2001
From: "refraction@gmail.com"
 <refraction@gmail.com@96395faa-99c1-11dd-bbfe-3dabce05a288>
Date: Sat, 9 Mar 2013 11:03:59 +0000
Subject: [PATCH] microVU/VU Int: Implemented T-Bit/D-Bit handling on microVU.

-Dreamworks Over The Hedge actually requires this to load.  Interpreter kind of had it right, but didn't stop the VU on these flags, causing the graphics to look bad and hang on the start button, works fine now.

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@5583 96395faa-99c1-11dd-bbfe-3dabce05a288
---
 pcsx2/Dmac.h                  |  2 +-
 pcsx2/Hw.cpp                  |  3 ++-
 pcsx2/VU0microInterp.cpp      |  2 ++
 pcsx2/VU1microInterp.cpp      |  2 ++
 pcsx2/x86/microVU_Compile.inl | 28 ++++++++++++++++++++++++++--
 pcsx2/x86/microVU_IR.h        |  2 ++
 6 files changed, 35 insertions(+), 4 deletions(-)

diff --git a/pcsx2/Dmac.h b/pcsx2/Dmac.h
index 9dededbe0d..1a3df37284 100644
--- a/pcsx2/Dmac.h
+++ b/pcsx2/Dmac.h
@@ -553,7 +553,7 @@ extern void setDmacStat(u32 num);
 extern tDMA_TAG *SPRdmaGetAddr(u32 addr, bool write);
 extern tDMA_TAG *dmaGetAddr(u32 addr, bool write);
 
-extern void hwIntcIrq(int n);
+extern void __fastcall hwIntcIrq(int n);
 extern void hwDmacIrq(int n);
 
 extern void FireMFIFOEmpty();
diff --git a/pcsx2/Hw.cpp b/pcsx2/Hw.cpp
index bcfca1fc7c..55a03a7ea1 100644
--- a/pcsx2/Hw.cpp
+++ b/pcsx2/Hw.cpp
@@ -129,7 +129,8 @@ __fi uint dmacInterrupt()
 	return 0x800;
 }
 
-void hwIntcIrq(int n)
+//Fastcall required for VU recompilers. Test Over the Hedge when changing.
+void __fastcall hwIntcIrq(int n)
 {
 	psHu32(INTC_STAT) |= 1<<n;
 	if(psHu32(INTC_MASK) & (1<<n))cpuTestINTCInts();
diff --git a/pcsx2/VU0microInterp.cpp b/pcsx2/VU0microInterp.cpp
index 6d02cbaa2b..4b15d5b7de 100644
--- a/pcsx2/VU0microInterp.cpp
+++ b/pcsx2/VU0microInterp.cpp
@@ -62,12 +62,14 @@ static void _vu0Exec(VURegs* VU)
 			VU0.VI[REG_VPU_STAT].UL|= 0x2;
 			hwIntcIrq(INTC_VU0);
 		}
+		VU->ebit = 1;
 	}
 	if (ptr[1] & 0x08000000) { /* T flag */
 		if (VU0.VI[REG_FBRST].UL & 0x8) {
 			VU0.VI[REG_VPU_STAT].UL|= 0x4;
 			hwIntcIrq(INTC_VU0);
 		}
+		VU->ebit = 1;
 	}
 
 	VU->code = ptr[1];
diff --git a/pcsx2/VU1microInterp.cpp b/pcsx2/VU1microInterp.cpp
index 3ddfec7518..2edb5fb73c 100644
--- a/pcsx2/VU1microInterp.cpp
+++ b/pcsx2/VU1microInterp.cpp
@@ -60,12 +60,14 @@ static void _vu1Exec(VURegs* VU)
 			VU0.VI[REG_VPU_STAT].UL|= 0x200;
 			hwIntcIrq(INTC_VU1);
 		}
+		VU->ebit = 1;
 	}
 	if (ptr[1] & 0x08000000) { /* T flag */
 		if (VU0.VI[REG_FBRST].UL & 0x800) {
 			VU0.VI[REG_VPU_STAT].UL|= 0x400;
 			hwIntcIrq(INTC_VU1);
 		}
+		VU->ebit = 1;
 	}
 
 	//VUM_LOG("VU->cycle = %d (flags st=%x;mac=%x;clip=%x,q=%f)", VU->cycle, VU->statusflag, VU->macflag, VU->clipflag, VU->q.F);
diff --git a/pcsx2/x86/microVU_Compile.inl b/pcsx2/x86/microVU_Compile.inl
index 383b991b68..7a5e2e1fc5 100644
--- a/pcsx2/x86/microVU_Compile.inl
+++ b/pcsx2/x86/microVU_Compile.inl
@@ -479,6 +479,26 @@ void* mVUcompileSingleInstruction(microVU& mVU, u32 startPC, uptr pState, microF
 	return thisPtr;
 }
 
+void mVUDoDBit(microVU& mVU)
+{
+	xTEST(ptr32[&VU0.VI[REG_FBRST].UL], (isVU1 ? 0x400 : 0x4));
+	xForwardJump32 eJMP(Jcc_Zero);
+	xOR(ptr32[&VU0.VI[REG_VPU_STAT].UL], (isVU1 ? 0x200 : 0x2));
+	xMOV( gprT2, (isVU1 ? 7 : 6));
+	xCALL( hwIntcIrq );
+	eJMP.SetTarget();
+}
+
+void mVUDoTBit(microVU& mVU)
+{
+	xTEST(ptr32[&VU0.VI[REG_FBRST].UL], (isVU1 ? 0x800 : 0x8));
+	xForwardJump32 eJMP(Jcc_Zero);
+	xOR(ptr32[&VU0.VI[REG_VPU_STAT].UL], (isVU1 ? 0x400 : 0x4));
+	xMOV( gprT2, (isVU1 ? 7 : 6));
+	xCALL( hwIntcIrq );
+	eJMP.SetTarget();
+}
+
 void* mVUcompile(microVU& mVU, u32 startPC, uptr pState) {
 	
 	microFlagCycles mFC;
@@ -498,8 +518,9 @@ void* mVUcompile(microVU& mVU, u32 startPC, uptr pState) {
 		mVUopU(mVU, 0);
 		mVUcheckBadOp(mVU);
 		if (curI & _Ebit_)  { eBitPass1(mVU, branch); }
-		if (curI & _DTbit_) { branch = 4; }
+		if (curI & _Dbit_)  { mVUup.dBit = 1; branch = 2; }
 		if (curI & _Mbit_)  { mVUup.mBit = 1; }
+		if (curI & _Tbit_)  { mVUup.tBit = 1; branch = 2; }
 		if (curI & _Ibit_)  { mVUlow.isNOP = 1; mVUup.iBit = 1; }
 		else			    { incPC(-1); mVUopL(mVU, 0); incPC(1); }
 		mVUsetCycles(mVU);
@@ -554,7 +575,10 @@ void* mVUcompile(microVU& mVU, u32 startPC, uptr pState) {
 		}
 	}
 	if ((x == endCount) && (x!=1)) { Console.Error("microVU%d: Possible infinite compiling loop!", mVU.index); }
-
+	incPC(-1);
+	if(mVUup.tBit) mVUDoTBit(mVU);
+	if(mVUup.dBit) mVUDoDBit(mVU);
+	incPC(1);
 	// E-bit End
 	mVUsetupRange(mVU, xPC-8, 0);
 	mVUendProgram(mVU, &mFC, 1);
diff --git a/pcsx2/x86/microVU_IR.h b/pcsx2/x86/microVU_IR.h
index ef7c24fef0..5f045d6b1f 100644
--- a/pcsx2/x86/microVU_IR.h
+++ b/pcsx2/x86/microVU_IR.h
@@ -112,6 +112,8 @@ struct microUpperOp {
 	bool eBit;				// Has E-bit set
 	bool iBit;				// Has I-bit set
 	bool mBit;				// Has M-bit set
+	bool tBit;				// Has T-bit set
+	bool dBit;				// Has D-bit set
 	microVFreg VF_write;	// VF Vectors written to by this instruction
 	microVFreg VF_read[2];	// VF Vectors read by this instruction
 };