mirror of https://github.com/PCSX2/pcsx2.git
Unified the three DmaExec functions into one. :)
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3550 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
Jake.Stine
parent
bc849cc042
commit
8d07e78b86
33
pcsx2/Dmac.h
33
pcsx2/Dmac.h
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@ -438,18 +438,24 @@ union tDMAC_CTRL {
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union tDMAC_STAT {
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struct {
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u32 CIS : 10;
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u32 _reserved1 : 3;
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u32 SIS : 1;
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u32 MEIS : 1;
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u32 BEIS : 1;
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u32 CIM : 10;
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u32 _reserved2 : 3;
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u32 SIM : 1;
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u32 MEIM : 1;
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u32 _reserved3 : 1;
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struct {
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u32 CIS : 10;
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u32 _reserved1 : 3;
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u32 SIS : 1;
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u32 MEIS : 1;
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u32 BEIS : 1;
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u32 CIM : 10;
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u32 _reserved2 : 3;
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u32 SIM : 1;
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u32 MEIM : 1;
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u32 _reserved3 : 1;
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};
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u32 _u32;
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};
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struct {
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u16 _u16lo;
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u16 _u16hi;
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};
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u32 _u32;
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tDMAC_STAT(u32 val) { _u32 = val; }
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@ -458,6 +464,11 @@ union tDMAC_STAT {
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void clear_flags(u32 flags) { _u32 &= ~flags; }
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void reset() { _u32 = 0; }
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wxString desc() const { return wxsFormat(L"Stat: 0x%x", _u32); }
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bool TestForInterrupt() const
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{
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return ((_u16lo & _u16hi) != 0) || BEIS;
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}
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};
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union tDMAC_PCR {
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@ -24,6 +24,8 @@ using namespace R5900;
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/////////////////////////////////////////////////////////////////////////
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// DMA Execution Interfaces
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// Returns true if the DMA is enabled and executed successfully. Returns false if execution
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// was blocked (DMAE or master DMA enabler).
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static bool QuickDmaExec( void (*func)(), u32 mem)
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{
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bool ret = false;
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@ -35,7 +37,6 @@ static bool QuickDmaExec( void (*func)(), u32 mem)
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ret = true;
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}
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return ret;
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}
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@ -43,205 +44,49 @@ static bool QuickDmaExec( void (*func)(), u32 mem)
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tDMAC_QUEUE QueuedDMA(0);
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u32 oldvalue = 0;
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void __fastcall StartQueuedDMA()
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static void StartQueuedDMA()
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{
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if (QueuedDMA.VIF0) { DMA_LOG("Resuming DMA for VIF0"); if(QuickDmaExec(dmaVIF0, D0_CHCR) == true) QueuedDMA.VIF0 = false; }
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if (QueuedDMA.VIF1) { DMA_LOG("Resuming DMA for VIF1"); if(QuickDmaExec(dmaVIF1, D1_CHCR) == true) QueuedDMA.VIF1 = false; }
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if (QueuedDMA.GIF ) { DMA_LOG("Resuming DMA for GIF" ); if(QuickDmaExec(dmaGIF , D2_CHCR) == true) QueuedDMA.GIF = false; }
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if (QueuedDMA.IPU0) { DMA_LOG("Resuming DMA for IPU0"); if(QuickDmaExec(dmaIPU0, D3_CHCR) == true) QueuedDMA.IPU0 = false; }
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if (QueuedDMA.IPU1) { DMA_LOG("Resuming DMA for IPU1"); if(QuickDmaExec(dmaIPU1, D4_CHCR) == true) QueuedDMA.IPU1 = false; }
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if (QueuedDMA.SIF0) { DMA_LOG("Resuming DMA for SIF0"); if(QuickDmaExec(dmaSIF0, D5_CHCR) == true) QueuedDMA.SIF0 = false; }
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if (QueuedDMA.SIF1) { DMA_LOG("Resuming DMA for SIF1"); if(QuickDmaExec(dmaSIF1, D6_CHCR) == true) QueuedDMA.SIF1 = false; }
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if (QueuedDMA.SIF2) { DMA_LOG("Resuming DMA for SIF2"); if(QuickDmaExec(dmaSIF2, D7_CHCR) == true) QueuedDMA.SIF2 = false; }
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if (QueuedDMA.SPR0) { DMA_LOG("Resuming DMA for SPR0"); if(QuickDmaExec(dmaSPR0, D8_CHCR) == true) QueuedDMA.SPR0 = false; }
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if (QueuedDMA.SPR1) { DMA_LOG("Resuming DMA for SPR1"); if(QuickDmaExec(dmaSPR1, D9_CHCR) == true) QueuedDMA.SPR1 = false; }
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if (QueuedDMA.VIF0) { DMA_LOG("Resuming DMA for VIF0"); QueuedDMA.VIF0 = !QuickDmaExec(dmaVIF0, D0_CHCR); }
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if (QueuedDMA.VIF1) { DMA_LOG("Resuming DMA for VIF1"); QueuedDMA.VIF1 = !QuickDmaExec(dmaVIF1, D1_CHCR); }
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if (QueuedDMA.GIF ) { DMA_LOG("Resuming DMA for GIF" ); QueuedDMA.GIF = !QuickDmaExec(dmaGIF , D2_CHCR); }
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if (QueuedDMA.IPU0) { DMA_LOG("Resuming DMA for IPU0"); QueuedDMA.IPU0 = !QuickDmaExec(dmaIPU0, D3_CHCR); }
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if (QueuedDMA.IPU1) { DMA_LOG("Resuming DMA for IPU1"); QueuedDMA.IPU1 = !QuickDmaExec(dmaIPU1, D4_CHCR); }
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if (QueuedDMA.SIF0) { DMA_LOG("Resuming DMA for SIF0"); QueuedDMA.SIF0 = !QuickDmaExec(dmaSIF0, D5_CHCR); }
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if (QueuedDMA.SIF1) { DMA_LOG("Resuming DMA for SIF1"); QueuedDMA.SIF1 = !QuickDmaExec(dmaSIF1, D6_CHCR); }
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if (QueuedDMA.SIF2) { DMA_LOG("Resuming DMA for SIF2"); QueuedDMA.SIF2 = !QuickDmaExec(dmaSIF2, D7_CHCR); }
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if (QueuedDMA.SPR0) { DMA_LOG("Resuming DMA for SPR0"); QueuedDMA.SPR0 = !QuickDmaExec(dmaSPR0, D8_CHCR); }
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if (QueuedDMA.SPR1) { DMA_LOG("Resuming DMA for SPR1"); QueuedDMA.SPR1 = !QuickDmaExec(dmaSPR1, D9_CHCR); }
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}
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// dark cloud2 uses 8 bit DMAs register writes
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static __forceinline void DmaExec8( void (*func)(), u32 mem, u8 value )
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static _f void DmaExec( void (*func)(), u32 mem, u32 value )
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{
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DMACh *reg = &psH_DMACh(mem & ~0xf);
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//The only thing we can do in an 8bit write is set the CHCR, so lets just do checks for that
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//It's invalid for the hardware to write a DMA while it is active, not without Suspending the DMAC
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if (reg->chcr.STR)
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{
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if(psHu8(DMAC_ENABLER+2) == 1) //DMA is suspended so we can allow writes to anything
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{
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//If it stops the DMA, we need to clear any pending interrupts so the DMA doesnt continue.
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if(value == 0)
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{
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//DevCon.Warning(L"8bit %s DMA Stopped on Suspend", ChcrName(mem & ~0xf));
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if(ChannelNumber(mem & ~0xf) == 1)
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{
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cpuClearInt( 10 );
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QueuedDMA._u16 &= ~(1 << 10); //Clear any queued DMA requests for this channel
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}
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else if(ChannelNumber(mem & ~0xf) == 2)
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{
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cpuClearInt( 11 );
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QueuedDMA._u16 &= ~(1 << 11); //Clear any queued DMA requests for this channel
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}
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cpuClearInt( ChannelNumber(mem & ~0xf) );
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QueuedDMA._u16 &= ~(1 << ChannelNumber(mem & ~0xf)); //Clear any queued DMA requests for this channel;
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}
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//Here we update the CHCR STR (Busy) bit, we don't touch anything else.
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reg->chcr.STR = value;
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return;
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}
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else //Else the DMA is running (Not Suspended), so we cant touch it!
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{
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//As the manual states "Fields other than STR can only be written to when the DMA is stopped"
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//Also "The DMA may not stop properly just by writing 0 to STR"
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//So the presumption is that STR can be written to (ala force stop the DMA) but nothing else
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if(value == 0)
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{
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//DevCon.Warning(L"8bit Force Stopping %s (Current CHCR %x) while DMA active", ChcrName(mem & ~0xf), reg->chcr._u32, value);
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reg->chcr.STR = value;
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//We need to clear any existing DMA loops that are in progress else they will continue!
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if(ChannelNumber(mem & ~0xf) == 1)
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{
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cpuClearInt( 10 );
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QueuedDMA._u16 &= ~(1 << 10); //Clear any queued DMA requests for this channel
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}
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else if(ChannelNumber(mem & ~0xf) == 2)
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{
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cpuClearInt( 11 );
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QueuedDMA._u16 &= ~(1 << 11); //Clear any queued DMA requests for this channel
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}
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cpuClearInt( ChannelNumber(mem & ~0xf) );
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QueuedDMA._u16 &= ~(1 << ChannelNumber(mem & ~0xf)); //Clear any queued DMA requests for this channel
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}
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//else DevCon.Warning(L"8bit Attempted to stop %s DMA without suspend, ignoring", ChcrName(mem & ~0xf));
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return;
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}
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}
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reg->chcr.STR = value;
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if (reg->chcr.STR && dmacRegs->ctrl.DMAE && !psHu8(DMAC_ENABLER+2))
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{
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func();
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}
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else if(reg->chcr.STR)
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{
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//DevCon.Warning(L"8bit %s DMA Start while DMAC Disabled\n",ChcrName(mem));
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QueuedDMA._u16 |= (1 << ChannelNumber(mem & ~0xf)); //Queue the DMA up to be started then the DMA's are Enabled and or the Suspend is lifted
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}
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}
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static __forceinline void DmaExec16( void (*func)(), u32 mem, u16 value )
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{
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DMACh *reg = &psH_DMACh(mem);
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tDMA_CHCR chcr(value);
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//It's invalid for the hardware to write a DMA while it is active, not without Suspending the DMAC
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if (reg->chcr.STR)
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{
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if(psHu8(DMAC_ENABLER+2) == 1) //DMA is suspended so we can allow writes to anything
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{
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//If it stops the DMA, we need to clear any pending interrupts so the DMA doesnt continue.
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if(chcr.STR == 0)
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{
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//DevCon.Warning(L"16bit %s DMA Stopped on Suspend", ChcrName(mem));
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if(ChannelNumber(mem) == 1)
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{
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cpuClearInt( 10 );
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QueuedDMA._u16 &= ~(1 << 10); //Clear any queued DMA requests for this channel
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}
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else if(ChannelNumber(mem) == 2)
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{
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cpuClearInt( 11 );
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QueuedDMA._u16 &= ~(1 << 11); //Clear any queued DMA requests for this channel
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}
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cpuClearInt( ChannelNumber(mem) );
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QueuedDMA._u16 &= ~(1 << ChannelNumber(mem)); //Clear any queued DMA requests for this channel
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}
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//Here we update the lower part of the CHCR, we dont touch the tag as it is only a 16bit value
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reg->chcr.set((reg->chcr.TAG << 16) | chcr.lower());
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return;
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}
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else //Else the DMA is running (Not Suspended), so we cant touch it!
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{
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//As the manual states "Fields other than STR can only be written to when the DMA is stopped"
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//Also "The DMA may not stop properly just by writing 0 to STR"
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//So the presumption is that STR can be written to (ala force stop the DMA) but nothing else
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if(chcr.STR == 0)
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{
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//DevCon.Warning(L"16bit Force Stopping %s (Current CHCR %x) while DMA active", ChcrName(mem), reg->chcr._u32, chcr._u32);
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reg->chcr.STR = 0;
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//We need to clear any existing DMA loops that are in progress else they will continue!
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if(ChannelNumber(mem) == 1)
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{
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cpuClearInt( 10 );
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QueuedDMA._u16 &= ~(1 << 10); //Clear any queued DMA requests for this channel
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}
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else if(ChannelNumber(mem) == 2)
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{
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cpuClearInt( 11 );
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QueuedDMA._u16 &= ~(1 << 11); //Clear any queued DMA requests for this channel
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}
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cpuClearInt( ChannelNumber(mem) );
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QueuedDMA._u16 &= ~(1 << ChannelNumber(mem)); //Clear any queued DMA requests for this channel
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}
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//else DevCon.Warning(L"16bit Attempted to change %s modes while DMA active, ignoring", ChcrName(mem));
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return;
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}
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}
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reg->chcr.set((reg->chcr.TAG << 16) | chcr.lower());
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if (reg->chcr.STR && dmacRegs->ctrl.DMAE && !psHu8(DMAC_ENABLER+2))
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{
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func();
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}
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else if(reg->chcr.STR)
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{
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//DevCon.Warning(L"16bit %s DMA Start while DMAC Disabled\n",ChcrName(mem));
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QueuedDMA._u16 |= (1 << ChannelNumber(mem)); //Queue the DMA up to be started then the DMA's are Enabled and or the Suspend is lifted
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}
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}
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static void DmaExec( void (*func)(), u32 mem, u32 value )
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{
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DMACh *reg = &psH_DMACh(mem);
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tDMA_CHCR chcr(value);
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//It's invalid for the hardware to write a DMA while it is active, not without Suspending the DMAC
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if (reg->chcr.STR)
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{
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const uint channel = ChannelNumber(mem);
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if(psHu8(DMAC_ENABLER+2) == 1) //DMA is suspended so we can allow writes to anything
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{
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//If it stops the DMA, we need to clear any pending interrupts so the DMA doesnt continue.
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if(chcr.STR == 0)
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{
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//DevCon.Warning(L"32bit %s DMA Stopped on Suspend", ChcrName(mem));
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if(ChannelNumber(mem) == 1)
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if(channel == 1)
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{
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cpuClearInt( 10 );
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QueuedDMA._u16 &= ~(1 << 10); //Clear any queued DMA requests for this channel
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}
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else if(ChannelNumber(mem) == 2)
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else if(channel == 2)
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{
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cpuClearInt( 11 );
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QueuedDMA._u16 &= ~(1 << 11); //Clear any queued DMA requests for this channel
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}
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cpuClearInt( ChannelNumber(mem) );
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QueuedDMA._u16 &= ~(1 << ChannelNumber(mem)); //Clear any queued DMA requests for this channel
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cpuClearInt( channel );
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QueuedDMA._u16 &= ~(1 << channel); //Clear any queued DMA requests for this channel
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}
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//Sanity Check for possible future bug fix0rs ;p
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//Spams on Persona 4 opening.
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@ -263,19 +108,19 @@ static void DmaExec( void (*func)(), u32 mem, u32 value )
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reg->chcr.STR = 0;
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//We need to clear any existing DMA loops that are in progress else they will continue!
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if(ChannelNumber(mem) == 1)
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if(channel == 1)
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{
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cpuClearInt( 10 );
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QueuedDMA._u16 &= ~(1 << 10); //Clear any queued DMA requests for this channel
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}
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else if(ChannelNumber(mem) == 2)
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else if(channel == 2)
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{
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cpuClearInt( 11 );
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QueuedDMA._u16 &= ~(1 << 11); //Clear any queued DMA requests for this channel
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}
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cpuClearInt( ChannelNumber(mem) );
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QueuedDMA._u16 &= ~(1 << ChannelNumber(mem)); //Clear any queued DMA requests for this channel
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cpuClearInt( channel );
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QueuedDMA._u16 &= ~(1 << channel); //Clear any queued DMA requests for this channel
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}
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//else DevCon.Warning(L"32bit Attempted to change %s CHCR (Currently %x) with %x while DMA active, ignoring QWC = %x", ChcrName(mem), reg->chcr._u32, chcr._u32, reg->qwc);
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return;
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@ -298,6 +143,23 @@ static void DmaExec( void (*func)(), u32 mem, u32 value )
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} //else QueuedDMA._u16 &~= (1 << ChannelNumber(mem)); //
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}
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// DmaExec8 should only be called for the second byte of CHCR.
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// Testing Note: dark cloud 2 uses 8 bit DMAs register writes.
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static _f void DmaExec8( void (*func)(), u32 mem, u8 value )
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{
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pxAssumeMsg( (mem & 0xf) == 1, "DmaExec8 should only be called for the second byte of CHCR" );
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// The calling function calls this when the second byte (bits 8->15) is written. Only bit 8
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// is effective, and it is the STR (start) bit. :)
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DmaExec( func, mem & ~0xf, (u32)value<<8 );
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}
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static _f void DmaExec16( void (*func)(), u32 mem, u16 value )
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{
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DmaExec( func, mem, (u32)value );
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}
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/////////////////////////////////////////////////////////////////////////
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// Hardware WRITE 8 bit
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