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Improved handling of jNO_DEFAULT so that it performs a sanity check in Devel builds [currently applies to Pcsx2 only since we don't have a standard define macro for devbuild in the plugins]. 

Cleaned up and abbreviated logging for the new IOP HwRead/Write handlers.

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1131 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
Jake.Stine 2009-05-04 14:12:21 +00:00
parent b02d6a19dd
commit 8ab8adabf1
4 changed files with 96 additions and 94 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

41
common/include/Pcsx2Defs.h
View File

@ -30,6 +30,8 @@
#include "Pcsx2Types.h"
// Renamed ARRAYSIZE to ArraySize -- looks nice and gets rid of Windows.h conflicts (air)
// Notes: I'd have used ARRAY_SIZE instead but ran into cross-platform lib conflicts with
// that as well. >_<
#ifndef ArraySize
#define ArraySize(x) (sizeof(x)/sizeof((x)[0]))
#endif
@ -39,29 +41,42 @@
// This is primarily useful for the default case switch optimizer, which enables VC to
// generate more compact switches.
#ifdef NDEBUG
# define jBREAKPOINT() ((void) 0)
# ifdef _MSC_VER
# define jASSUME(exp) (__assume(exp))
#ifndef jASSUME
# ifdef NDEBUG
# define jBREAKPOINT() ((void) 0)
# ifdef _MSC_VER
# define jASSUME(exp) (__assume(exp))
# else
# define jASSUME(exp) ((void) sizeof(exp))
# endif
# else
# define jASSUME(exp) ((void) sizeof(exp))
# if defined(_MSC_VER)
# define jBREAKPOINT() do { __asm int 3 } while(0)
# else
# define jBREAKPOINT() ((void) *(volatile char *) 0)
# endif
# define jASSUME(exp) if(exp) ; else jBREAKPOINT()
# endif
#else
# if defined(_MSC_VER)
# define jBREAKPOINT() do { __asm int 3 } while(0)
# else
# define jBREAKPOINT() ((void) *(volatile char *) 0)
# endif
# define jASSUME(exp) if(exp) ; else jBREAKPOINT()
#endif
// disable the default case in a switch
//////////////////////////////////////////////////////////////////////////////////////////
// jNO_DEFAULT -- disables the default case in a switch, which improves switch optimization
// under MSVC.
//
// How it Works: jASSUME turns into an __assume(0) under msvc compilers, which when specified
// in the default: case of a switch tells the compiler that the case is unreachable, and so
// the compiler will not generate any code, LUTs, or conditionals to handle it. In debug
// builds the default case will cause an assertion (meaning the jNO_DEFAULT has been used
// incorrectly, and that the default case is in fact used and needs to be handled).
//
#ifndef jNO_DEFAULT
#define jNO_DEFAULT \
{ \
default: \
jASSUME(0); \
break; \
}
#endif
/* common defines */
#ifndef C_ASSERT

25
pcsx2/PrecompiledHeader.h
View File

@ -12,6 +12,7 @@
#ifdef PCSX2_DEVBUILD
# define _SECURE_SCL 1
# define _SECURE_SCL_THROWS 1
# pragma warning(disable:4244) // disable warning C4244: '=' : conversion from 'big' to 'small', possible loss of data
#else
# define _SECURE_SCL 0
#endif
@ -19,15 +20,25 @@
#define NOMINMAX // Disables other libs inclusion of their own min/max macros (we use std instead)
#if defined (__linux__) // some distributions are lower case
# define __LINUX__
#ifndef _WIN32
# include <unistd.h> // Non-Windows platforms need this
#endif
#ifdef _WIN32
// disable warning C4244: '=' : conversion from 'big' to 'small', possible loss of data
# pragma warning(disable:4244)
#else
# include <unistd.h> // Non-Windows platforms need this
//////////////////////////////////////////////////////////////////////////////////////////
// Custom version of jNO_DEFAULT macro for devel builds.
// Raises an exception if the default case is reached. This notifies us that a jNO_DEFAULT
// directive has been used incorrectly.
//
// MSVC Note: To stacktrace LogicError exceptions, add Exception::LogicError to the C++ First-
// Chance Exception list (under Debug->Exceptions menu).
//
#ifdef PCSX2_DEVBUILD
#define jNO_DEFAULT \
{ \
default: \
throw Exception::LogicError( "Incorrect usage of jNO_DEFAULT detected (default case is not unreachable!)" ); \
break; \
}
#endif
//////////////////////////////////////////////////////////////////////////////////////////

71
pcsx2/ps2/Iop/IopHwRead.cpp
View File

@ -50,28 +50,28 @@ u8 __fastcall iopHwRead8_Page1( u32 addr )
default:
if( masked_addr >= 0x100 && masked_addr < 0x130 )
{
DevCon::Notice( "*Hardware Read8 from Counter16 [ignored] [addr=0x%02x]", params addr, psxHu8(addr) );
DevCon::Notice( "HwRead8 from Counter16 [ignored], addr 0x%08x = 0x%02x", params addr, psxHu8(addr) );
ret = psxHu8( addr );
}
else if( masked_addr >= 0x480 && masked_addr < 0x4a0 )
{
DevCon::Notice( "*Hardware Read8 from Counter32 [ignored] [addr=0x%02x]", params addr, psxHu8(addr) );
DevCon::Notice( "HwRead8 from Counter32 [ignored], addr 0x%08x = 0x%02x", params addr, psxHu8(addr) );
ret = psxHu8( addr );
}
else if( (masked_addr >= pgmsk(HW_USB_START)) && (masked_addr < pgmsk(HW_USB_END)) )
{
ret = USBread8( addr );
PSXHW_LOG( "Hardware Read8 from USB: addr 0x%08x = 0x%02x", addr, ret );
PSXHW_LOG( "HwRead8 from USB, addr 0x%08x = 0x%02x", addr, ret );
}
else
{
ret = psxHu8(addr);
PSXHW_LOG( "*Unknown Hardware Read8 from addr 0x%08x = 0x%02x", addr, ret );
PSXHW_LOG( "HwRead8 from Unknown, addr 0x%08x = 0x%02x", addr, ret );
}
return ret;
}
PSXHW_LOG( "*Hardware Read8 from %s, addr 0x%08x = 0x%02x", _log_GetIopHwName<u8>( addr ), addr, ret );
PSXHW_LOG( "HwRead8 from %s, addr 0x%08x = 0x%02x", _log_GetIopHwName<u8>( addr ), addr, ret );
return ret;
}
@ -88,7 +88,7 @@ u8 __fastcall iopHwRead8_Page3( u32 addr )
else
ret = psxHu8( addr );
PSXHW_LOG( "Hardware Read8 from %s, addr 0x%08x = 0x%02x", _log_GetIopHwName<u8>( addr ), addr, psxHu8(addr) );
PSXHW_LOG( "HwRead8 from %s, addr 0x%08x = 0x%02x", _log_GetIopHwName<u8>( addr ), addr, psxHu8(addr) );
return ret;
}
@ -106,7 +106,7 @@ u8 __fastcall iopHwRead8_Page8( u32 addr )
else
ret = psxHu8( addr );
PSXHW_LOG( "Hardware Read8 from %s, addr 0x%08x = 0x%02x", _log_GetIopHwName<u8>( addr ), addr, psxHu8(addr) );
PSXHW_LOG( "HwRead8 from %s, addr 0x%08x = 0x%02x", _log_GetIopHwName<u8>( addr ), addr, psxHu8(addr) );
return ret;
}
@ -215,7 +215,7 @@ static __forceinline T _HwRead_16or32_Page1( u32 addr )
ret = SPU2read( addr );
else
{
DevCon::Notice( "*PCSX2* SPU2 Hardware Read32 (addr=0x%08X)? What manner of trickery is this?!", params addr );
DevCon::Notice( "HwRead32 from SPU2? (addr=0x%08X) .. What manner of trickery is this?!", params addr );
ret = psxHu32(addr);
}
}
@ -311,7 +311,7 @@ static __forceinline T _HwRead_16or32_Page1( u32 addr )
}
}
PSXHW_LOG( "Hardware Read%s from %s, addr 0x%08x = 0x%04x",
PSXHW_LOG( "HwRead%s from %s, addr 0x%08x = 0x%04x",
(sizeof(T) == 2) ? "16" : "32", _log_GetIopHwName<T>( addr ), addr, ret
);
return ret;
@ -336,7 +336,7 @@ u16 __fastcall iopHwRead16_Page3( u32 addr )
jASSUME( (addr >> 12) == 0x1f803 );
u16 ret = psxHu16(addr);
PSXHW_LOG( "Hardware Read16 from %s, addr 0x%08x = 0x%04x", _log_GetIopHwName<u16>( addr ), addr, ret );
PSXHW_LOG( "HwRead16 from %s, addr 0x%08x = 0x%04x", _log_GetIopHwName<u16>( addr ), addr, ret );
return ret;
}
@ -348,7 +348,7 @@ u16 __fastcall iopHwRead16_Page8( u32 addr )
jASSUME( (addr >> 12) == 0x1f808 );
u16 ret = psxHu16(addr);
PSXHW_LOG( "Hardware Read16 from %s, addr 0x%08x = 0x%04x", _log_GetIopHwName<u16>( addr ), addr, ret );
PSXHW_LOG( "HwRead16 from %s, addr 0x%08x = 0x%04x", _log_GetIopHwName<u16>( addr ), addr, ret );
return ret;
}
@ -366,7 +366,7 @@ u32 __fastcall iopHwRead32_Page3( u32 addr )
// all addresses are assumed to be prefixed with 0x1f803xxx:
jASSUME( (addr >> 12) == 0x1f803 );
const u32 ret = psxHu32(addr);
PSXHW_LOG( "Hardware Read32 from %s, addr 0x%08x = 0x%08x", _log_GetIopHwName<u32>( addr ), addr, ret );
PSXHW_LOG( "HwRead32 from %s, addr 0x%08x = 0x%08x", _log_GetIopHwName<u32>( addr ), addr, ret );
return ret;
}
@ -399,34 +399,25 @@ u32 __fastcall iopHwRead32_Page8( u32 addr )
{
switch( masked_addr )
{
mcase(HW_SIO2_CTRL):
ret = sio2_getCtrl();
break;
mcase(HW_SIO2_RECV1):
ret = sio2_getRecv1();
break;
mcase(HW_SIO2_RECV2):
ret = sio2_getRecv2();
break;
mcase(HW_SIO2_RECV3):
ret = sio2_getRecv3();
break;
mcase(0x1f808278):
ret = sio2_get8278();
break;
mcase(0x1f80827C):
ret = sio2_get827C();
break;
mcase(HW_SIO2_INTR):
ret = sio2_getIntr();
break;
mcase(HW_SIO2_CTRL): ret = sio2_getCtrl(); break;
mcase(HW_SIO2_RECV1): ret = sio2_getRecv1(); break;
mcase(HW_SIO2_RECV2): ret = sio2_getRecv2(); break;
mcase(HW_SIO2_RECV3): ret = sio2_getRecv3(); break;
mcase(0x1f808278): ret = sio2_get8278(); break;
mcase(0x1f80827C): ret = sio2_get827C(); break;
mcase(HW_SIO2_INTR): ret = sio2_getIntr(); break;
// HW_SIO2_FIFO -- A yet unknown: Should this be ignored on 32 bit writes, or handled as a
// 4-byte FIFO input?
// The old IOP system just ignored it, so that's what we do here. I've included commented code
// for treating it as a 16/32 bit write though [which si what the SIO does, for example).
mcase(HW_SIO2_FIFO):
//ret = sio2_fifoOut();
//ret |= sio2_fifoOut() << 8;
//ret |= sio2_fifoOut() << 16;
//ret |= sio2_fifoOut() << 24;
//break;
default:
ret = psxHu32(addr);
break;
@ -435,7 +426,7 @@ u32 __fastcall iopHwRead32_Page8( u32 addr )
}
else ret = psxHu32(addr);
PSXHW_LOG( "Hardware Read32 from %s, addr 0x%08x = 0x%02x", _log_GetIopHwName<u32>( addr ), addr, ret );
PSXHW_LOG( "HwRead32 from %s, addr 0x%08x = 0x%02x", _log_GetIopHwName<u32>( addr ), addr, ret );
return ret;
}

53
pcsx2/ps2/Iop/IopHwWrite.cpp
View File

@ -49,12 +49,12 @@ void __fastcall iopHwWrite8_Page1( u32 addr, u8 val )
default:
if( masked_addr >= 0x100 && masked_addr < 0x130 )
{
DevCon::Notice( "*Hardware Write8 to Counter16 [ignored] [addr=0x%02x]", params addr, psxHu8(addr) );
DevCon::Notice( "HwWrite8 to Counter16 [ignored], addr 0x%08x = 0x%02x", params addr, psxHu8(addr) );
psxHu8( addr ) = val;
}
else if( masked_addr >= 0x480 && masked_addr < 0x4a0 )
{
DevCon::Notice( "*Hardware Write8 to Counter32 [ignored] [addr=0x%02x]", params addr, psxHu8(addr) );
DevCon::Notice( "HwWrite8 to Counter32 [ignored], addr 0x%08x = 0x%02x", params addr, psxHu8(addr) );
psxHu8( addr ) = val;
}
else if( masked_addr >= pgmsk(HW_USB_START) && masked_addr < pgmsk(HW_USB_END) )
@ -68,7 +68,7 @@ void __fastcall iopHwWrite8_Page1( u32 addr, u8 val )
break;
}
PSXHW_LOG( "*Hardware Write8 to %s, addr 0x%08x = 0x%02x\n", _log_GetIopHwName<u8>(addr), addr, val );
PSXHW_LOG( "HwWrite8 to %s, addr 0x%08x = 0x%02x\n", _log_GetIopHwName<u8>(addr), addr, val );
}
static char g_pbuf[1024];
@ -98,7 +98,7 @@ void __fastcall iopHwWrite8_Page3( u32 addr, u8 val )
}
}
PSXHW_LOG( "Hardware Write8 to %s, addr 0x%08x = 0x%02x", _log_GetIopHwName<u8>(addr), addr, psxHu8(addr) );
PSXHW_LOG( "HwWrite8 to %s, addr 0x%08x = 0x%02x", _log_GetIopHwName<u8>(addr), addr, psxHu8(addr) );
psxHu8( addr ) = val;
}
@ -112,7 +112,7 @@ void __fastcall iopHwWrite8_Page8( u32 addr, u8 val )
else
psxHu8( addr ) = val;
PSXHW_LOG( "Hardware Write8 to %s, addr 0x%08x = 0x%02x", _log_GetIopHwName<u8>(addr), addr, psxHu8(addr) );
PSXHW_LOG( "HwWrite8 to %s, addr 0x%08x = 0x%02x", _log_GetIopHwName<u8>(addr), addr, psxHu8(addr) );
}
@ -210,7 +210,7 @@ static __forceinline void _HwWrite_16or32_Page1( u32 addr, T val )
SPU2write( addr, val );
else
{
DevCon::Notice( "*PCSX2* SPU2 Hardware Write32 (addr=0x%08X)? What manner of trickery is this?!", params addr );
DevCon::Notice( "HwWrite32 to SPU2? (addr=0x%08X) .. What manner of trickery is this?!", params addr );
//psxHu(addr) = val;
}
}
@ -423,7 +423,7 @@ static __forceinline void _HwWrite_16or32_Page1( u32 addr, T val )
}
}
PSXHW_LOG( "Hardware Write%s to %s, addr 0x%08x = 0x%04x",
PSXHW_LOG( "HwWrite%s to %s, addr 0x%08x = 0x%04x",
sizeof(T) == 2 ? "16" : "32", _log_GetIopHwName<T>( addr ), addr, val
);
}
@ -441,7 +441,7 @@ void __fastcall iopHwWrite16_Page3( u32 addr, u16 val )
// all addresses are assumed to be prefixed with 0x1f803xxx:
jASSUME( (addr >> 12) == 0x1f803 );
psxHu16(addr) = val;
PSXHW_LOG( "Hardware Write16 to %s, addr 0x%08x = 0x%04x", _log_GetIopHwName<u16>( addr ), addr, val );
PSXHW_LOG( "HwWrite16 to %s, addr 0x%08x = 0x%04x", _log_GetIopHwName<u16>( addr ), addr, val );
}
void __fastcall iopHwWrite16_Page8( u32 addr, u16 val )
@ -449,7 +449,7 @@ void __fastcall iopHwWrite16_Page8( u32 addr, u16 val )
// all addresses are assumed to be prefixed with 0x1f808xxx:
jASSUME( (addr >> 12) == 0x1f808 );
psxHu16(addr) = val;
PSXHW_LOG( "Hardware Write16 to %s, addr 0x%08x = 0x%04x", _log_GetIopHwName<u16>( addr ), addr, val );
PSXHW_LOG( "HwWrite16 to %s, addr 0x%08x = 0x%04x", _log_GetIopHwName<u16>( addr ), addr, val );
}
//////////////////////////////////////////////////////////////////////////////////////////
@ -464,7 +464,7 @@ void __fastcall iopHwWrite32_Page3( u32 addr, u32 val )
// all addresses are assumed to be prefixed with 0x1f803xxx:
jASSUME( (addr >> 12) == 0x1f803 );
psxHu16(addr) = val;
PSXHW_LOG( "Hardware Write32 to %s, addr 0x%08x = 0x%04x", _log_GetIopHwName<u16>( addr ), addr, val );
PSXHW_LOG( "HwWrite32 to %s, addr 0x%08x = 0x%04x", _log_GetIopHwName<u16>( addr ), addr, val );
}
void __fastcall iopHwWrite32_Page8( u32 addr, u32 val )
@ -493,36 +493,21 @@ void __fastcall iopHwWrite32_Page8( u32 addr, u32 val )
{
switch( masked_addr )
{
case 0x264: // unknown / reserved.
case 0x26C: // recv1 [read-only]
case 0x270: // recv2 [read-only]
case 0x274: // recv3 [read-only]
mcase(HW_SIO2_CTRL): sio2_setCtrl( val ); break;
mcase(0x1f808278): sio2_set8278( val ); break;
mcase(0x1f80827C): sio2_set827C( val ); break;
mcase(HW_SIO2_INTR): sio2_setIntr( val ); break;
// Other SIO2 registers are read-only, no-ops on write.
default:
psxHu32(addr) = val;
break;
case 0x268:
sio2_setCtrl( val );
break;
case 0x278:
sio2_set8278( val );
break;
case 0x27C:
sio2_set827C( val );
break;
case 0x280:
sio2_setIntr( val );
break;
jNO_DEFAULT;
break;
}
}
}
else psxHu32(addr) = val;
PSXHW_LOG( "Hardware Write32 to %s, addr 0x%08x = 0x%02x", _log_GetIopHwName<u32>( addr ), addr, val );
PSXHW_LOG( "HwWrite32 to %s, addr 0x%08x = 0x%02x", _log_GetIopHwName<u32>( addr ), addr, val );
}