mirror of https://github.com/PCSX2/pcsx2.git
messed around with some DMA functions, might fix DMA errors. GIFdma should also be faster, since now it only freezes MMX and XMM regs when it needs to. also did some very minor code cleanups.
p.s. GIFdma() is a mess, it needs to get cleaned-up in the future. git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@150 a6443dda-0b58-4228-96e9-037be469359c
This commit is contained in:
cottonvibes
Gregory Hainaut
parent
7a70299529
commit
88ea5fb921
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@ -797,14 +797,11 @@ void mechaDecryptBytes(unsigned char* buffer, int size)
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int shiftAmount = (cdvd.decSet>>4) & 7;
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int doXor = (cdvd.decSet) & 1;
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int doShift = (cdvd.decSet) & 2;
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unsigned char key = cdvd.Key[4];
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for(i=0; i<size; i++)
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for (i=0; i<size; i++)
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{
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if(doXor)
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buffer[i] ^= key;
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if(doShift)
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buffer[i] = (buffer[i]>>shiftAmount) | (buffer[i]<<(8-shiftAmount));
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if (doXor) buffer[i] ^= cdvd.Key[4];
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if (doShift) buffer[i] = (buffer[i]>>shiftAmount) | (buffer[i]<<(8-shiftAmount));
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}
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}
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159
pcsx2/GS.cpp
159
pcsx2/GS.cpp
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@ -1070,53 +1070,37 @@ int gscount = 0;
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static int prevcycles = 0;
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static u32* prevtag = NULL;
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void GIFdma() {
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void GIFdma()
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{
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u32 *ptag;
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gscycles= prevcycles ? prevcycles: gscycles;
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u32 id;
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gscycles= prevcycles ? prevcycles: gscycles;
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/*if ((psHu32(DMAC_CTRL) & 0xC0)) {
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SysPrintf("DMA Stall Control %x\n",(psHu32(DMAC_CTRL) & 0xC0));
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}*/
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if( (psHu32(GIF_CTRL) & 8) ) {
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// temporarily stop
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if( (psHu32(GIF_CTRL) & 8) ) { // temporarily stop
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SysPrintf("Gif dma temp paused?\n");
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return;
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}
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#ifdef GIF_LOG
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GIF_LOG("dmaGIFstart chcr = %lx, madr = %lx, qwc = %lx\n"
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" tadr = %lx, asr0 = %lx, asr1 = %lx\n",
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gif->chcr, gif->madr, gif->qwc,
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gif->tadr, gif->asr0, gif->asr1);
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#endif
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GIF_LOG("dmaGIFstart chcr = %lx, madr = %lx, qwc = %lx\n tadr = %lx, asr0 = %lx, asr1 = %lx\n", gif->chcr, gif->madr, gif->qwc, gif->tadr, gif->asr0, gif->asr1);
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#ifndef GSPATH3FIX
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if (psHu32(GIF_MODE) & 0x4) {
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} else
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if (vif1Regs->mskpath3 || psHu32(GIF_MODE) & 0x1) {
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gif->chcr &= ~0x100;
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psHu32(GIF_STAT)&= ~0xE00; // OPH=0 | APATH=0
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hwDmacIrq(2);
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return;
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if ( !(psHu32(GIF_MODE) & 0x4) ) {
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if (vif1Regs->mskpath3 || psHu32(GIF_MODE) & 0x1) {
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gif->chcr &= ~0x100;
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psHu32(GIF_STAT)&= ~0xE00; // OPH=0 | APATH=0
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hwDmacIrq(2);
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return;
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}
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}
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#endif
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FreezeXMMRegs(1);
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FreezeMMXRegs(1);
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if ((psHu32(DMAC_CTRL) & 0xC0) == 0x80 && prevcycles != 0) { // STD == GIF
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SysPrintf("GS Stall Control Source = %x, Drain = %x\n MADR = %x, STADR = %x", (psHu32(0xe000) >> 4) & 0x3, (psHu32(0xe000) >> 6) & 0x3,gif->madr, psHu32(DMAC_STADR));
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SysPrintf("GS Stall Control Source = %x, Drain = %x\n MADR = %x, STADR = %x", (psHu32(0xe000) >> 4) & 0x3, (psHu32(0xe000) >> 6) & 0x3, gif->madr, psHu32(DMAC_STADR));
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if( gif->madr + (gif->qwc * 16) > psHu32(DMAC_STADR) ) {
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INT(2, gscycles);
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gscycles = 0;
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FreezeXMMRegs(0);
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FreezeMMXRegs(0);
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return;
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}
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prevcycles = 0;
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@ -1129,55 +1113,48 @@ void GIFdma() {
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psHu32(GIF_STAT)|= 0x10000000; // FQC=31, hack ;)
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#ifdef GSPATH3FIX
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if (vif1Regs->mskpath3 || psHu32(GIF_MODE) & 0x1){
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if(gif->qwc == 0){
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if((gif->chcr & 0x10e) == 0x104){
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ptag = (u32*)dmaGetAddr(gif->tadr); //Set memory pointer to TADR
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if (vif1Regs->mskpath3 || psHu32(GIF_MODE) & 0x1) {
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if(gif->qwc == 0) {
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if((gif->chcr & 0x10e) == 0x104) {
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ptag = (u32*)dmaGetAddr(gif->tadr); //Set memory pointer to TADR
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if (ptag == NULL) { //Is ptag empty?
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psHu32(DMAC_STAT)|= 1<<15; //If yes, set BEIS (BUSERR) in DMAC_STAT register
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FreezeXMMRegs(0);
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FreezeMMXRegs(0);
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return;
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}
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gscycles += 2;
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gif->chcr = ( gif->chcr & 0xFFFF ) | ( (*ptag) & 0xFFFF0000 ); //Transfer upper part of tag to CHCR bits 31-15
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id = (ptag[0] >> 28) & 0x7; //ID for DmaChain copied from bit 28 of the tag
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gif->qwc = (u16)ptag[0]; //QWC set to lower 16bits of the tag
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gif->madr = ptag[1]; //MADR = ADDR field
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gspath3done = hwDmacSrcChainWithStack(gif, id);
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#ifdef GIF_LOG
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GIF_LOG("PTH3 MASK gifdmaChain %8.8x_%8.8x size=%d, id=%d, addr=%lx\n",
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ptag[1], ptag[0], gif->qwc, id, gif->madr);
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#endif
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if ((gif->chcr & 0x80) && ptag[0] >> 31) { //Check TIE bit of CHCR and IRQ bit of tag
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#ifdef GIF_LOG
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GIF_LOG("PATH3 MSK dmaIrq Set\n");
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#endif
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SysPrintf("GIF TIE\n");
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gspath3done |= 1;
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}
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if (ptag == NULL) { //Is ptag empty?
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psHu32(DMAC_STAT)|= 1<<15; //If yes, set BEIS (BUSERR) in DMAC_STAT register
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return;
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}
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gscycles += 2;
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gif->chcr = ( gif->chcr & 0xFFFF ) | ( (*ptag) & 0xFFFF0000 ); //Transfer upper part of tag to CHCR bits 31-15
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id = (ptag[0] >> 28) & 0x7; //ID for DmaChain copied from bit 28 of the tag
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gif->qwc = (u16)ptag[0]; //QWC set to lower 16bits of the tag
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gif->madr = ptag[1]; //MADR = ADDR field
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gspath3done = hwDmacSrcChainWithStack(gif, id);
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GIF_LOG("PTH3 MASK gifdmaChain %8.8x_%8.8x size=%d, id=%d, addr=%lx\n", ptag[1], ptag[0], gif->qwc, id, gif->madr);
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if ((gif->chcr & 0x80) && ptag[0] >> 31) { //Check TIE bit of CHCR and IRQ bit of tag
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GIF_LOG("PATH3 MSK dmaIrq Set\n");
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SysPrintf("GIF TIE\n");
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gspath3done |= 1;
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}
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}
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}
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GIFchain();
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FreezeXMMRegs(1);
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FreezeMMXRegs(1);
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GIFchain();
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FreezeXMMRegs(0); // Theres a comment below that says not to unfreeze the xmm regs, so not sure about this.
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FreezeMMXRegs(0);
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if((gspath3done == 1 || (gif->chcr & 0xc) == 0) && gif->qwc == 0){
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if(gif->qwc > 0)SysPrintf("Horray\n");
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if(gif->qwc > 0) SysPrintf("Horray\n");
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gspath3done = 0;
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gif->chcr &= ~0x100;
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//psHu32(GIF_MODE)&= ~0x4;
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GSCSRr &= ~0xC000;
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GSCSRr |= 0x4000;
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Path3transfer = 0;
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psHu32(GIF_STAT)&= ~0xE00; // OPH=0 | APATH=0
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psHu32(GIF_STAT)&= ~0x1F000000; // QFC=0
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psHu32(GIF_STAT)&= ~0x1F000E00; // OPH=0 | APATH=0 | QFC=0
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hwDmacIrq(DMAC_GIF);
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}
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FreezeXMMRegs(0);
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FreezeMMXRegs(0);
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//Dont unfreeze xmm regs here, Masked PATH3 can only be called by VIF, which is already handling it.
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return;
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}
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@ -1189,28 +1166,27 @@ void GIFdma() {
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if ((psHu32(DMAC_CTRL) & 0xC0) == 0x80 && (gif->chcr & 0xc) == 0) {
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SysPrintf("DMA Stall Control on GIF normal\n");
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}
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GIFchain();
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if(gif->qwc == 0 && (gif->chcr & 0xc) == 0)gspath3done = 1;
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FreezeXMMRegs(1);
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FreezeMMXRegs(1);
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GIFchain(); //Transfers the data set by the switch
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FreezeXMMRegs(0);
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FreezeMMXRegs(0);
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if(gif->qwc == 0 && (gif->chcr & 0xc) == 0) gspath3done = 1;
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}
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else {
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// Chain Mode
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//#ifndef GSPATH3FIX
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while (gspath3done == 0 && gif->qwc == 0) { //Loop if the transfers aren't intermittent
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//#endif
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ptag = (u32*)dmaGetAddr(gif->tadr); //Set memory pointer to TADR
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if (ptag == NULL) { //Is ptag empty?
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psHu32(DMAC_STAT)|= 1<<15; //If yes, set BEIS (BUSERR) in DMAC_STAT register
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FreezeXMMRegs(0);
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FreezeMMXRegs(0);
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return;
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}
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gscycles+=2; // Add 1 cycles from the QW read for the tag
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// Transfer dma tag if tte is set
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if (gif->chcr & 0x40) {
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//u32 temptag[4] = {0};
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#ifdef PCSX2_DEVBUILD
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//SysPrintf("GIF TTE: %x_%x\n", ptag[3], ptag[2]);
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#endif
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//temptag[0] = ptag[2];
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//temptag[1] = ptag[3];
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@ -1223,13 +1199,8 @@ void GIFdma() {
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gif->qwc = (u16)ptag[0]; //QWC set to lower 16bits of the tag
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gif->madr = ptag[1]; //MADR = ADDR field
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gspath3done = hwDmacSrcChainWithStack(gif, id);
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#ifdef GIF_LOG
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GIF_LOG("gifdmaChain %8.8x_%8.8x size=%d, id=%d, addr=%lx\n",
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ptag[1], ptag[0], gif->qwc, id, gif->madr);
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#endif
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GIF_LOG("gifdmaChain %8.8x_%8.8x size=%d, id=%d, addr=%lx\n", ptag[1], ptag[0], gif->qwc, id, gif->madr);
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if ((psHu32(DMAC_CTRL) & 0xC0) == 0x80) { // STD == GIF
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// there are still bugs, need to also check if gif->madr +16*qwc >= stadr, if not, stall
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@ -1241,28 +1212,22 @@ void GIFdma() {
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hwDmacIrq(13);
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INT(2, gscycles);
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gscycles = 0;
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FreezeXMMRegs(0);
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FreezeMMXRegs(0);
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return;
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}
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}
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GIFchain(); //Transfers the data set by the switch
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FreezeXMMRegs(1);
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FreezeMMXRegs(1);
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GIFchain(); //Transfers the data set by the switch
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FreezeXMMRegs(0);
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FreezeMMXRegs(0);
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if ((gif->chcr & 0x80) && ptag[0] >> 31) { //Check TIE bit of CHCR and IRQ bit of tag
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#ifdef GIF_LOG
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if ((gif->chcr & 0x80) && ptag[0] >> 31) { //Check TIE bit of CHCR and IRQ bit of tag
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GIF_LOG("dmaIrq Set\n");
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#endif
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//SysPrintf("GIF TIE\n");
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// SysPrintf("GSdmaIrq Set\n");
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gspath3done = 1;
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//gif->qwc = 0;
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//break;
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}
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//#ifndef GSPATH3FIX
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}
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//#endif
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}
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prevtag = NULL;
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prevcycles = 0;
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@ -1270,17 +1235,13 @@ void GIFdma() {
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INT(2, gscycles);
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gscycles = 0;
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}
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FreezeXMMRegs(0);
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FreezeMMXRegs(0);
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}
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void dmaGIF() {
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/*if(vif1Regs->mskpath3 || (psHu32(GIF_MODE) & 0x1)){
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INT(2, 48); //Wait time for the buffer to fill, fixes some timing problems in path 3 masking
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} //It takes the time of 24 QW for the BUS to become ready - The Punisher, And1 Streetball
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else*/
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//if(vif1Regs->mskpath3 || (psHu32(GIF_MODE) & 0x1)){
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// INT(2, 48); //Wait time for the buffer to fill, fixes some timing problems in path 3 masking
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//} //It takes the time of 24 QW for the BUS to become ready - The Punisher, And1 Streetball
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//else
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gspath3done = 0; // For some reason this doesnt clear? So when the system starts the thread, we will clear it :)
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if(gif->qwc > 0 && (gif->chcr & 0x4) == 0x4)
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@ -1295,8 +1256,6 @@ void dmaGIF() {
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GIFdma();
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}
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#define spr0 ((DMACh*)&PS2MEM_HW[0xD000])
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static unsigned int mfifocycles;
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21
pcsx2/Hw.h
21
pcsx2/Hw.h
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@ -317,24 +317,21 @@ extern __forceinline u8* dmaGetAddr(u32 mem)
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u8* p, *pbase;
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mem &= ~0xf;
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#ifdef _DEBUG
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if( (mem & 0xffff0000) == 0x10000000 )
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SysPrintf("dma to/from %x!\n", mem);
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#endif
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if( mem == 0x50000000 ) // reserved scratch pad mem
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return NULL;
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if( (mem&0xffff0000) == 0x50000000 ) {// reserved scratch pad mem
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SysPrintf("dmaGetAddr: reserved scratch pad mem\n");
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return (u8*)&PS2MEM_SCRATCH[(mem) & 0x3ff0];
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}
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p = (u8*)dmaGetAddrBase(mem); //, *pbase;
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p = (u8*)dmaGetAddrBase(mem);
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#ifdef _WIN32
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// do manual LUT since IPU/SPR seems to use addrs 0x3000xxxx quite often
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// do manual LUT since IPU/SPR seems to use addrs 0x3000xxxx quite often
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// linux doesn't suffer from this because it has better vm support
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#ifndef PCSX2_RELEASE
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if( memLUT[ (p-PS2MEM_BASE)>>12 ].aPFNs == NULL ) {
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SysPrintf("*PCSX2*: DMA error: %8.8x\n", mem);
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return NULL;
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SysPrintf("dmaGetAddr: memLUT PFN warning\n");
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return p;
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}
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#endif
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pbase = (u8*)memLUT[ (p-PS2MEM_BASE)>>12 ].aVFNs[0];
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if( pbase != NULL )
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p = pbase + ((u32)p&0xfff);
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@ -262,11 +262,12 @@ int _checkXMMreg(int type, int reg, int mode)
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for (i=0; i<XMMREGS; i++) {
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if (xmmregs[i].inuse && xmmregs[i].type == (type&0xff) && xmmregs[i].reg == reg ) {
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if( !(xmmregs[i].mode & MODE_READ) && (mode&(MODE_READ|MODE_READHALF)) ) {
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if(mode&MODE_READ)
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if ( !(xmmregs[i].mode & MODE_READ) ) {
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if (mode & MODE_READ) {
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SSEX_MOVDQA_M128_to_XMM(i, (uptr)_XMMGetAddr(xmmregs[i].type, xmmregs[i].reg, xmmregs[i].VU ? &VU1 : &VU0));
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else {
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if( cpucaps.hasStreamingSIMD2Extensions && g_xmmtypes[i]==XMMT_INT )
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}
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else if (mode & MODE_READHALF) {
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if( cpucaps.hasStreamingSIMD2Extensions && g_xmmtypes[i] == XMMT_INT )
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SSE2_MOVQ_M64_to_XMM(i, (uptr)_XMMGetAddr(xmmregs[i].type, xmmregs[i].reg, xmmregs[i].VU ? &VU1 : &VU0));
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else
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SSE_MOVLPS_M64_to_XMM(i, (uptr)_XMMGetAddr(xmmregs[i].type, xmmregs[i].reg, xmmregs[i].VU ? &VU1 : &VU0));
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@ -347,7 +348,7 @@ int _allocFPtoXMMreg(int xmmreg, int fpreg, int mode) {
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if (xmmregs[i].type != XMMTYPE_FPREG) continue;
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if (xmmregs[i].reg != fpreg) continue;
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if( !(xmmregs[i].mode & MODE_READ) && (mode&MODE_READ)) {
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if( !(xmmregs[i].mode & MODE_READ) && (mode & MODE_READ)) {
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SSE_MOVSS_M32_to_XMM(i, (uptr)&fpuRegs.fpr[fpreg].f);
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xmmregs[i].mode |= MODE_READ;
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}
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@ -791,28 +792,25 @@ void _deleteFPtoXMMreg(int reg, int flush)
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{
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int i;
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for (i=0; i<XMMREGS; i++) {
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if (xmmregs[i].inuse && xmmregs[i].type == XMMTYPE_FPREG && xmmregs[i].reg == reg ) {
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switch(flush) {
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case 0:
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_freeXMMreg(i);
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break;
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return;
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case 1:
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case 2:
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if( flush == 1 && (xmmregs[i].mode & MODE_WRITE) ) {
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if (xmmregs[i].mode & MODE_WRITE) {
|
||||
SSE_MOVSS_XMM_to_M32((uptr)&fpuRegs.fpr[reg].UL, i);
|
||||
// get rid of MODE_WRITE since don't want to flush again
|
||||
xmmregs[i].mode &= ~MODE_WRITE;
|
||||
xmmregs[i].mode |= MODE_READ;
|
||||
}
|
||||
return;
|
||||
|
||||
if( flush == 2 )
|
||||
xmmregs[i].inuse = 0;
|
||||
break;
|
||||
case 2:
|
||||
xmmregs[i].inuse = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1308,8 +1308,9 @@ void eeFPURecompileCode(R5900FNPTR_INFO xmmcode, R5900FNPTR_INFO fpucode, int xm
|
|||
}
|
||||
|
||||
if( xmminfo & XMMINFO_READS ) {
|
||||
if( (!(xmminfo&XMMINFO_READT)||mmregt>=0) && (g_pCurInstInfo->fpuregs[_Fs_] & EEINST_LASTUSE) )
|
||||
if( ( !(xmminfo & XMMINFO_READT) || (mmregt >= 0) ) && (g_pCurInstInfo->fpuregs[_Fs_] & EEINST_LASTUSE) ) {
|
||||
mmregs = _checkXMMreg(XMMTYPE_FPREG, _Fs_, MODE_READ);
|
||||
}
|
||||
else mmregs = _allocFPtoXMMreg(-1, _Fs_, MODE_READ);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue