mirror of https://github.com/PCSX2/pcsx2.git
further optimized recQFSRV thanks to some suggestions by Jake.
git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@599 a6443dda-0b58-4228-96e9-037be469359c
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@ -1713,52 +1713,57 @@ CPU_SSE_XMMCACHE_END
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}
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////////////////////////////////////////////////////
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// 15 bytes
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#define QFSRV_bytes 15
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// Both Macros are 16 bytes so we can use a shift instead of a Mul instruction
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#define QFSRVhelper0() { \
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ajmp[0] = JMP32(0); \
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x86Ptr += 11; \
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}
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#define QFSRVhelper(shift1, shift2) { \
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SSE2_PSRLDQ_I8_to_XMM(EEREC_D, shift1); \
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SSE2_PSLLDQ_I8_to_XMM(t0reg, shift2); \
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ajmp[shift1] = JMP32(0); \
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x86Ptr += 1; \
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}
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void recQFSRV()
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{
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if ( ! _Rd_ ) return;
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if ( !_Rd_ ) return;
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//SysPrintf("recQFSRV()\n");
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CPU_SSE2_XMMCACHE_START( XMMINFO_READS | XMMINFO_READT | XMMINFO_WRITED)
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CPU_SSE2_XMMCACHE_START( XMMINFO_READS | XMMINFO_READT | XMMINFO_WRITED )
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u32 *ajmp[16];
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int i, j;
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int t0reg = _allocTempXMMreg(XMMT_INT, -1);
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int x86temp = _allocX86reg(EDX, X86TYPE_TEMP, 0, 0); // Use EDX because MUL32R modifies EDX and EAX
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SSE2_MOVDQA_XMM_to_XMM(t0reg, EEREC_S);
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SSE2_MOVDQA_XMM_to_XMM(EEREC_D, EEREC_T);
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MOV32MtoR(x86temp, (uptr)&cpuRegs.sa);
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SHR32ItoR(x86temp, 3);
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AND32I8toR(x86temp, 0xf); // This can possibly be removed but keeping it incase theres garbage in SA (cottonvibes)
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MOV32ItoR(EAX, QFSRV_bytes);
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MUL32R(x86temp);
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ADD32ItoR(EAX, (uptr)x86Ptr + 7); // ADD32 = 5 bytes, JMPR = 2 bytes
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MOV32MtoR(EAX, (uptr)&cpuRegs.sa);
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SHL32ItoR(EAX, 1); // Multiply SA bytes by 16 bytes (the amount of bytes in QFSRVhelper() macros)
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AND32I8toR(EAX, 0xf0); // This can possibly be removed but keeping it incase theres garbage in SA (cottonvibes)
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ADD32ItoEAX((uptr)x86Ptr + 7); // ADD32 = 5 bytes, JMPR = 2 bytes
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JMPR(EAX); // Jumps to a QFSRVhelper() case below (a total of 16 different cases)
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// Cases 0 to 15:
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for (i = 0, j = 16; i < 16; i++, j--) {
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// Case 0:
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QFSRVhelper0();
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// Cases 1 to 15:
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for (i = 1, j = 15; i < 16; i++, j--) {
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QFSRVhelper(i, j);
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}
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// Set jump addresses for the JMP32's in QFSRVhelper()
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for (i = 0; i < 16; i++) {
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for (i = 1; i < 16; i++) {
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x86SetJ32(ajmp[i]);
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}
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// Concatenate the regs after appropriate shifts have been made
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SSE2_POR_XMM_to_XMM(EEREC_D, t0reg);
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x86SetJ32(ajmp[0]); // Case 0 jumps to here (to skip the POR)
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_freeXMMreg(t0reg);
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_freeX86reg(x86temp);
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CPU_SSE_XMMCACHE_END
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//recCall( Interp::QFSRV, _Rd_ );
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@ -272,6 +272,13 @@ __forceinline void CLC( void )
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write8( 0xF8 );
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}
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// NOP 1-byte
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__forceinline void NOP( void )
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{
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write8(0x90);
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}
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////////////////////////////////////
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// mov instructions /
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////////////////////////////////////
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@ -1017,6 +1024,13 @@ __forceinline void ADD64RtoR( x86IntRegType to, x86IntRegType from )
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ModRM( 3, from, to );
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}
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/* add imm32 to EAX */
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void ADD32ItoEAX( u32 from )
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{
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write8( 0x05 );
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write32( from );
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}
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/* add imm32 to r32 */
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__forceinline void ADD32ItoR( x86IntRegType to, u32 from )
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{
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@ -1029,15 +1043,15 @@ __forceinline void ADD32ItoR( x86IntRegType to, u32 from )
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}
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else
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{
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if ( to == EAX) {
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write8( 0x05 );
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if ( to == EAX ) {
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ADD32ItoEAX(from);
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}
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else {
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write8( 0x81 );
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ModRM( 3, 0, to );
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}
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write32( from );
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}
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}
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}
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/* add imm32 to m32 */
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@ -222,6 +222,7 @@ extern void CMOV32MtoR( int cc, int to, uptr from );
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extern void STC( void );
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extern void CLC( void );
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extern void NOP( void );
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////////////////////////////////////
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// mov instructions //
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@ -419,8 +420,10 @@ extern void ADD64ItoR( x86IntRegType to, u32 from );
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// add m64 to r64
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extern void ADD64MtoR( x86IntRegType to, uptr from );
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// add imm32 to EAX
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extern void ADD32ItoEAX( u32 from );
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// add imm32 to r32
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extern void ADD32ItoR( x86IntRegType to, u32 from );
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extern void ADD32ItoR( x86IntRegType to, u32 from );
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// add imm32 to m32
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extern void ADD32ItoM( uptr to, u32 from );
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// add imm32 to [r32+off]
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