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Implemented the handlers for channel 8 (dev9) in the new iop dmac. No plugins support the changes yet so don't enable it. 

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2571 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
gigaherz 2010-02-06 22:18:26 +00:00
parent 19b9ef1cea
commit 86d96ffbf2
5 changed files with 87 additions and 9 deletions
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39
common/include/PS2Edefs.h
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@ -16,13 +16,16 @@
#ifndef __PS2EDEFS_H__ #ifndef __PS2EDEFS_H__
#define __PS2EDEFS_H__ #define __PS2EDEFS_H__
// Global enable/disable flag, disables all the parts if off
//#define ENABLE_NEW_IOPDMA //#define ENABLE_NEW_IOPDMA
// Parts of the dmac, each one can be turned on independently
#ifdef ENABLE_NEW_IOPDMA #ifdef ENABLE_NEW_IOPDMA
//#define ENABLE_NEW_IOPDMA_SPU2 //#define ENABLE_NEW_IOPDMA_SPU2 /* working */
//#define ENABLE_NEW_IOPDMA_SIO //#define ENABLE_NEW_IOPDMA_SIO /* working */
//#define ENABLE_NEW_IOPDMA_CDVD //#define ENABLE_NEW_IOPDMA_CDVD /* NOT IMPLEMENTED */
//#define ENABLE_NEW_IOPDMA_SIF /* NOT IMPLEMENTED */
//#define ENABLE_NEW_IOPDMA_DEV9 /* untested (no plugins) */
#endif #endif
/* /*
@ -100,12 +103,16 @@ typedef struct _keyEvent {
#define PS2E_GS_VERSION 0x0006 #define PS2E_GS_VERSION 0x0006
#define PS2E_PAD_VERSION 0x0002 // -=[ OBSOLETE ]=- #define PS2E_PAD_VERSION 0x0002 // -=[ OBSOLETE ]=-
#ifdef ENABLE_NEW_IOPDMA_SPU2 #ifdef ENABLE_NEW_IOPDMA_SPU2
#define PS2E_SPU2_VERSION 0x0006 # define PS2E_SPU2_VERSION 0x0006
#else #else
#define PS2E_SPU2_VERSION 0x0005 # define PS2E_SPU2_VERSION 0x0005
#endif #endif
#define PS2E_CDVD_VERSION 0x0005 #define PS2E_CDVD_VERSION 0x0005
#define PS2E_DEV9_VERSION 0x0003 #ifdef ENABLE_NEW_IOPDMA_DEV9
# define PS2E_DEV9_VERSION 0x0004
#else
# define PS2E_DEV9_VERSION 0x0003
#endif
#define PS2E_USB_VERSION 0x0003 #define PS2E_USB_VERSION 0x0003
#define PS2E_FW_VERSION 0x0002 #define PS2E_FW_VERSION 0x0002
#define PS2E_SIO_VERSION 0x0001 #define PS2E_SIO_VERSION 0x0001
@ -449,8 +456,14 @@ u32 CALLBACK DEV9read32(u32 addr);
void CALLBACK DEV9write8(u32 addr, u8 value); void CALLBACK DEV9write8(u32 addr, u8 value);
void CALLBACK DEV9write16(u32 addr, u16 value); void CALLBACK DEV9write16(u32 addr, u16 value);
void CALLBACK DEV9write32(u32 addr, u32 value); void CALLBACK DEV9write32(u32 addr, u32 value);
#ifdef ENABLE_NEW_IOPDMA_DEV9
s32 CALLBACK DEV9dmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
s32 CALLBACK DEV9dmaWrite(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
void CALLBACK DEV9dmaInterrupt(s32 channel);
#else
void CALLBACK DEV9readDMA8Mem(u32 *pMem, int size); void CALLBACK DEV9readDMA8Mem(u32 *pMem, int size);
void CALLBACK DEV9writeDMA8Mem(u32 *pMem, int size); void CALLBACK DEV9writeDMA8Mem(u32 *pMem, int size);
#endif
// cycles = IOP cycles before calling callback, // cycles = IOP cycles before calling callback,
// if callback returns 1 the irq is triggered, else not // if callback returns 1 the irq is triggered, else not
void CALLBACK DEV9irqCallback(DEV9callback callback); void CALLBACK DEV9irqCallback(DEV9callback callback);
@ -663,8 +676,14 @@ typedef u32 (CALLBACK* _DEV9read32)(u32 mem);
typedef void (CALLBACK* _DEV9write8)(u32 mem, u8 value); typedef void (CALLBACK* _DEV9write8)(u32 mem, u8 value);
typedef void (CALLBACK* _DEV9write16)(u32 mem, u16 value); typedef void (CALLBACK* _DEV9write16)(u32 mem, u16 value);
typedef void (CALLBACK* _DEV9write32)(u32 mem, u32 value); typedef void (CALLBACK* _DEV9write32)(u32 mem, u32 value);
#ifdef ENABLE_NEW_IOPDMA_DEV9
typedef s32 (CALLBACK* _DEV9dmaRead)(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
typedef s32 (CALLBACK* _DEV9dmaWrite)(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
typedef void (CALLBACK* _DEV9dmaInterrupt)(s32 channel);
#else
typedef void (CALLBACK* _DEV9readDMA8Mem)(u32 *pMem, int size); typedef void (CALLBACK* _DEV9readDMA8Mem)(u32 *pMem, int size);
typedef void (CALLBACK* _DEV9writeDMA8Mem)(u32 *pMem, int size); typedef void (CALLBACK* _DEV9writeDMA8Mem)(u32 *pMem, int size);
#endif
typedef void (CALLBACK* _DEV9irqCallback)(DEV9callback callback); typedef void (CALLBACK* _DEV9irqCallback)(DEV9callback callback);
typedef DEV9handler (CALLBACK* _DEV9irqHandler)(void); typedef DEV9handler (CALLBACK* _DEV9irqHandler)(void);
@ -770,8 +789,14 @@ extern _DEV9read32 DEV9read32;
extern _DEV9write8 DEV9write8; extern _DEV9write8 DEV9write8;
extern _DEV9write16 DEV9write16; extern _DEV9write16 DEV9write16;
extern _DEV9write32 DEV9write32; extern _DEV9write32 DEV9write32;
#ifdef ENABLE_NEW_IOPDMA_DEV9
extern _DEV9dmaRead DEV9dmaRead;
extern _DEV9dmaWrite DEV9dmaWrite;
extern _DEV9dmaInterrupt DEV9dmaInterrupt;
#else
extern _DEV9readDMA8Mem DEV9readDMA8Mem; extern _DEV9readDMA8Mem DEV9readDMA8Mem;
extern _DEV9writeDMA8Mem DEV9writeDMA8Mem; extern _DEV9writeDMA8Mem DEV9writeDMA8Mem;
#endif
extern _DEV9irqCallback DEV9irqCallback; extern _DEV9irqCallback DEV9irqCallback;
extern _DEV9irqHandler DEV9irqHandler; extern _DEV9irqHandler DEV9irqHandler;

35
pcsx2/IopDma.cpp
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@ -141,6 +141,7 @@ int psxDma7Interrupt()
} }
#endif #endif
#ifndef ENABLE_NEW_IOPDMA_DEV9
void psxDma8(u32 madr, u32 bcr, u32 chcr) void psxDma8(u32 madr, u32 bcr, u32 chcr)
{ {
const int size = (bcr >> 16) * (bcr & 0xFFFF) * 8; const int size = (bcr >> 16) * (bcr & 0xFFFF) * 8;
@ -164,6 +165,7 @@ void psxDma8(u32 madr, u32 bcr, u32 chcr)
HW_DMA8_CHCR &= ~0x01000000; HW_DMA8_CHCR &= ~0x01000000;
psxDmaInterrupt2(1); psxDmaInterrupt2(1);
} }
#endif
void psxDma9(u32 madr, u32 bcr, u32 chcr) void psxDma9(u32 madr, u32 bcr, u32 chcr)
{ {
@ -281,6 +283,7 @@ s32 spu2DmaWrite(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed)
#ifdef ENABLE_NEW_IOPDMA_SPU2 #ifdef ENABLE_NEW_IOPDMA_SPU2
return SPU2dmaWrite(channel,data,bytesLeft,bytesProcessed); return SPU2dmaWrite(channel,data,bytesLeft,bytesProcessed);
#else #else
*bytesProcessed=0;
return 0; return 0;
#endif #endif
} }
@ -292,6 +295,32 @@ void spu2DmaInterrupt(s32 channel)
#endif #endif
} }
s32 dev9DmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed)
{
#ifdef ENABLE_NEW_IOPDMA_DEV9
return DEV9dmaRead(channel,data,bytesLeft,bytesProcessed);
#else
*bytesProcessed=0;
return 0;
#endif
}
s32 dev9DmaWrite(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed)
{
#ifdef ENABLE_NEW_IOPDMA_DEV9
return DEV9dmaWrite(channel,data,bytesLeft,bytesProcessed);
#else
return 0;
#endif
}
void dev9DmaInterrupt(s32 channel)
{
#ifdef ENABLE_NEW_IOPDMA_DEV9
DEV9dmaInterrupt(channel);
#endif
}
//typedef s32(* DmaHandler)(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed); //typedef s32(* DmaHandler)(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
//typedef void (* DmaIHandler)(s32 channel); //typedef void (* DmaIHandler)(s32 channel);
@ -358,7 +387,11 @@ const DmaHandlerInfo IopDmaHandlers[DMA_CHANNEL_MAX] =
#else #else
{"SPU2 Core1", _D__}, //7: Spu2 Core1 {"SPU2 Core1", _D__}, //7: Spu2 Core1
#endif #endif
{"Dev9", _DRW},// CHANNEL_BASE2(1), dev9DmaRead, dev9DmaWrite, dev9DmaInterrupt}, //8: Dev9 #ifdef ENABLE_NEW_IOPDMA_DEV9
{"Dev9", _ERW, CHANNEL_BASE2(1), dev9DmaRead, dev9DmaWrite, dev9DmaInterrupt}, //8: Dev9
#else
{"Dev9", _D__}, //8: Dev9
#endif
{"Sif0", _DRW},// CHANNEL_BASE2(2), sif0DmaRead, sif0DmaWrite, sif0DmaInterrupt}, //9: SIF0 {"Sif0", _DRW},// CHANNEL_BASE2(2), sif0DmaRead, sif0DmaWrite, sif0DmaInterrupt}, //9: SIF0
{"Sif1", _DRW},// CHANNEL_BASE2(3), sif1DmaRead, sif1DmaWrite, sif1DmaInterrupt}, //10: SIF1 {"Sif1", _DRW},// CHANNEL_BASE2(3), sif1DmaRead, sif1DmaWrite, sif1DmaInterrupt}, //10: SIF1
#ifdef ENABLE_NEW_IOPDMA_SIO #ifdef ENABLE_NEW_IOPDMA_SIO

6
pcsx2/IopDma.h
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@ -65,10 +65,14 @@ extern void cdvdDmaInterrupt(s32 channel);
extern void psxDma2(u32 madr, u32 bcr, u32 chcr); extern void psxDma2(u32 madr, u32 bcr, u32 chcr);
extern void psxDma3(u32 madr, u32 bcr, u32 chcr); extern void psxDma3(u32 madr, u32 bcr, u32 chcr);
extern void psxDma4(u32 madr, u32 bcr, u32 chcr);
extern void psxDma6(u32 madr, u32 bcr, u32 chcr); extern void psxDma6(u32 madr, u32 bcr, u32 chcr);
#ifndef ENABLE_NEW_IOPDMA_SPU2
extern void psxDma4(u32 madr, u32 bcr, u32 chcr);
extern void psxDma7(u32 madr, u32 bcr, u32 chcr); extern void psxDma7(u32 madr, u32 bcr, u32 chcr);
#endif
#ifndef ENABLE_NEW_IOPDMA_DEV9
extern void psxDma8(u32 madr, u32 bcr, u32 chcr); extern void psxDma8(u32 madr, u32 bcr, u32 chcr);
#endif
extern void psxDma9(u32 madr, u32 bcr, u32 chcr); extern void psxDma9(u32 madr, u32 bcr, u32 chcr);
extern void psxDma10(u32 madr, u32 bcr, u32 chcr); extern void psxDma10(u32 madr, u32 bcr, u32 chcr);

12
pcsx2/PluginManager.cpp
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@ -233,8 +233,14 @@ _DEV9read32 DEV9read32;
_DEV9write8 DEV9write8; _DEV9write8 DEV9write8;
_DEV9write16 DEV9write16; _DEV9write16 DEV9write16;
_DEV9write32 DEV9write32; _DEV9write32 DEV9write32;
#ifdef ENABLE_NEW_IOPDMA_DEV9
_DEV9dmaRead DEV9dmaRead;
_DEV9dmaWrite DEV9dmaWrite;
_DEV9dmaInterrupt DEV9dmaInterrupt;
#else
_DEV9readDMA8Mem DEV9readDMA8Mem; _DEV9readDMA8Mem DEV9readDMA8Mem;
_DEV9writeDMA8Mem DEV9writeDMA8Mem; _DEV9writeDMA8Mem DEV9writeDMA8Mem;
#endif
_DEV9irqCallback DEV9irqCallback; _DEV9irqCallback DEV9irqCallback;
_DEV9irqHandler DEV9irqHandler; _DEV9irqHandler DEV9irqHandler;
@ -517,8 +523,14 @@ static const LegacyApi_ReqMethod s_MethMessReq_DEV9[] =
{ "DEV9write8", (vMeth**)&DEV9write8, NULL }, { "DEV9write8", (vMeth**)&DEV9write8, NULL },
{ "DEV9write16", (vMeth**)&DEV9write16, NULL }, { "DEV9write16", (vMeth**)&DEV9write16, NULL },
{ "DEV9write32", (vMeth**)&DEV9write32, NULL }, { "DEV9write32", (vMeth**)&DEV9write32, NULL },
#ifdef ENABLE_NEW_IOPDMA_DEV9
{ "DEV9dmaRead", (vMeth**)&DEV9dmaRead, NULL },
{ "DEV9dmaWrite", (vMeth**)&DEV9dmaWrite, NULL },
{ "DEV9dmaInterrupt", (vMeth**)&DEV9dmaInterrupt, NULL },
#else
{ "DEV9readDMA8Mem", (vMeth**)&DEV9readDMA8Mem, NULL }, { "DEV9readDMA8Mem", (vMeth**)&DEV9readDMA8Mem, NULL },
{ "DEV9writeDMA8Mem", (vMeth**)&DEV9writeDMA8Mem, NULL }, { "DEV9writeDMA8Mem", (vMeth**)&DEV9writeDMA8Mem, NULL },
#endif
{ "DEV9irqCallback", (vMeth**)&DEV9irqCallback, NULL }, { "DEV9irqCallback", (vMeth**)&DEV9irqCallback, NULL },
{ "DEV9irqHandler", (vMeth**)&DEV9irqHandler, NULL }, { "DEV9irqHandler", (vMeth**)&DEV9irqHandler, NULL },

4
pcsx2/ps2/Iop/IopHwWrite.cpp
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@ -379,7 +379,11 @@ static __forceinline void _HwWrite_16or32_Page1( u32 addr, T val )
mcase(0x1f801518): // DMA8 CHCR -- DEV9 mcase(0x1f801518): // DMA8 CHCR -- DEV9
psxHu(addr) = val; psxHu(addr) = val;
#ifdef ENABLE_NEW_IOPDMA_DEV9
DmaExecNew2(8);
#else
DmaExec2(8); DmaExec2(8);
#endif
break; break;
mcase(0x1f801528): // DMA9 CHCR -- SIF0 mcase(0x1f801528): // DMA9 CHCR -- SIF0