mirror of https://github.com/PCSX2/pcsx2.git
Implemented the handlers for channel 8 (dev9) in the new iop dmac. No plugins support the changes yet so don't enable it.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2571 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
gigaherz
parent
19b9ef1cea
commit
86d96ffbf2
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@ -16,13 +16,16 @@
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#ifndef __PS2EDEFS_H__
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#define __PS2EDEFS_H__
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// Global enable/disable flag, disables all the parts if off
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//#define ENABLE_NEW_IOPDMA
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// Parts of the dmac, each one can be turned on independently
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#ifdef ENABLE_NEW_IOPDMA
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//#define ENABLE_NEW_IOPDMA_SPU2
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//#define ENABLE_NEW_IOPDMA_SIO
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//#define ENABLE_NEW_IOPDMA_CDVD
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//#define ENABLE_NEW_IOPDMA_SPU2 /* working */
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//#define ENABLE_NEW_IOPDMA_SIO /* working */
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//#define ENABLE_NEW_IOPDMA_CDVD /* NOT IMPLEMENTED */
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//#define ENABLE_NEW_IOPDMA_SIF /* NOT IMPLEMENTED */
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//#define ENABLE_NEW_IOPDMA_DEV9 /* untested (no plugins) */
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#endif
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/*
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@ -100,12 +103,16 @@ typedef struct _keyEvent {
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#define PS2E_GS_VERSION 0x0006
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#define PS2E_PAD_VERSION 0x0002 // -=[ OBSOLETE ]=-
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#ifdef ENABLE_NEW_IOPDMA_SPU2
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#define PS2E_SPU2_VERSION 0x0006
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# define PS2E_SPU2_VERSION 0x0006
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#else
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#define PS2E_SPU2_VERSION 0x0005
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# define PS2E_SPU2_VERSION 0x0005
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#endif
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#define PS2E_CDVD_VERSION 0x0005
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#define PS2E_DEV9_VERSION 0x0003
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#ifdef ENABLE_NEW_IOPDMA_DEV9
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# define PS2E_DEV9_VERSION 0x0004
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#else
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# define PS2E_DEV9_VERSION 0x0003
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#endif
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#define PS2E_USB_VERSION 0x0003
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#define PS2E_FW_VERSION 0x0002
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#define PS2E_SIO_VERSION 0x0001
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@ -449,8 +456,14 @@ u32 CALLBACK DEV9read32(u32 addr);
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void CALLBACK DEV9write8(u32 addr, u8 value);
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void CALLBACK DEV9write16(u32 addr, u16 value);
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void CALLBACK DEV9write32(u32 addr, u32 value);
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#ifdef ENABLE_NEW_IOPDMA_DEV9
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s32 CALLBACK DEV9dmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
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s32 CALLBACK DEV9dmaWrite(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
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void CALLBACK DEV9dmaInterrupt(s32 channel);
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#else
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void CALLBACK DEV9readDMA8Mem(u32 *pMem, int size);
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void CALLBACK DEV9writeDMA8Mem(u32 *pMem, int size);
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#endif
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// cycles = IOP cycles before calling callback,
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// if callback returns 1 the irq is triggered, else not
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void CALLBACK DEV9irqCallback(DEV9callback callback);
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@ -663,8 +676,14 @@ typedef u32 (CALLBACK* _DEV9read32)(u32 mem);
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typedef void (CALLBACK* _DEV9write8)(u32 mem, u8 value);
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typedef void (CALLBACK* _DEV9write16)(u32 mem, u16 value);
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typedef void (CALLBACK* _DEV9write32)(u32 mem, u32 value);
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#ifdef ENABLE_NEW_IOPDMA_DEV9
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typedef s32 (CALLBACK* _DEV9dmaRead)(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
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typedef s32 (CALLBACK* _DEV9dmaWrite)(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
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typedef void (CALLBACK* _DEV9dmaInterrupt)(s32 channel);
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#else
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typedef void (CALLBACK* _DEV9readDMA8Mem)(u32 *pMem, int size);
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typedef void (CALLBACK* _DEV9writeDMA8Mem)(u32 *pMem, int size);
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#endif
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typedef void (CALLBACK* _DEV9irqCallback)(DEV9callback callback);
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typedef DEV9handler (CALLBACK* _DEV9irqHandler)(void);
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@ -770,8 +789,14 @@ extern _DEV9read32 DEV9read32;
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extern _DEV9write8 DEV9write8;
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extern _DEV9write16 DEV9write16;
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extern _DEV9write32 DEV9write32;
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#ifdef ENABLE_NEW_IOPDMA_DEV9
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extern _DEV9dmaRead DEV9dmaRead;
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extern _DEV9dmaWrite DEV9dmaWrite;
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extern _DEV9dmaInterrupt DEV9dmaInterrupt;
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#else
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extern _DEV9readDMA8Mem DEV9readDMA8Mem;
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extern _DEV9writeDMA8Mem DEV9writeDMA8Mem;
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#endif
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extern _DEV9irqCallback DEV9irqCallback;
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extern _DEV9irqHandler DEV9irqHandler;
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@ -141,6 +141,7 @@ int psxDma7Interrupt()
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}
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#endif
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#ifndef ENABLE_NEW_IOPDMA_DEV9
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void psxDma8(u32 madr, u32 bcr, u32 chcr)
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{
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const int size = (bcr >> 16) * (bcr & 0xFFFF) * 8;
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@ -164,6 +165,7 @@ void psxDma8(u32 madr, u32 bcr, u32 chcr)
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HW_DMA8_CHCR &= ~0x01000000;
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psxDmaInterrupt2(1);
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}
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#endif
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void psxDma9(u32 madr, u32 bcr, u32 chcr)
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{
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@ -281,6 +283,7 @@ s32 spu2DmaWrite(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed)
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#ifdef ENABLE_NEW_IOPDMA_SPU2
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return SPU2dmaWrite(channel,data,bytesLeft,bytesProcessed);
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#else
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*bytesProcessed=0;
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return 0;
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#endif
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}
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@ -292,6 +295,32 @@ void spu2DmaInterrupt(s32 channel)
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#endif
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}
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s32 dev9DmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed)
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{
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#ifdef ENABLE_NEW_IOPDMA_DEV9
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return DEV9dmaRead(channel,data,bytesLeft,bytesProcessed);
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#else
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*bytesProcessed=0;
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return 0;
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#endif
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}
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s32 dev9DmaWrite(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed)
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{
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#ifdef ENABLE_NEW_IOPDMA_DEV9
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return DEV9dmaWrite(channel,data,bytesLeft,bytesProcessed);
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#else
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return 0;
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#endif
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}
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void dev9DmaInterrupt(s32 channel)
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{
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#ifdef ENABLE_NEW_IOPDMA_DEV9
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DEV9dmaInterrupt(channel);
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#endif
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}
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//typedef s32(* DmaHandler)(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
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//typedef void (* DmaIHandler)(s32 channel);
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@ -358,7 +387,11 @@ const DmaHandlerInfo IopDmaHandlers[DMA_CHANNEL_MAX] =
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#else
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{"SPU2 Core1", _D__}, //7: Spu2 Core1
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#endif
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{"Dev9", _DRW},// CHANNEL_BASE2(1), dev9DmaRead, dev9DmaWrite, dev9DmaInterrupt}, //8: Dev9
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#ifdef ENABLE_NEW_IOPDMA_DEV9
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{"Dev9", _ERW, CHANNEL_BASE2(1), dev9DmaRead, dev9DmaWrite, dev9DmaInterrupt}, //8: Dev9
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#else
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{"Dev9", _D__}, //8: Dev9
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#endif
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{"Sif0", _DRW},// CHANNEL_BASE2(2), sif0DmaRead, sif0DmaWrite, sif0DmaInterrupt}, //9: SIF0
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{"Sif1", _DRW},// CHANNEL_BASE2(3), sif1DmaRead, sif1DmaWrite, sif1DmaInterrupt}, //10: SIF1
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#ifdef ENABLE_NEW_IOPDMA_SIO
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@ -65,10 +65,14 @@ extern void cdvdDmaInterrupt(s32 channel);
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extern void psxDma2(u32 madr, u32 bcr, u32 chcr);
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extern void psxDma3(u32 madr, u32 bcr, u32 chcr);
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extern void psxDma4(u32 madr, u32 bcr, u32 chcr);
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extern void psxDma6(u32 madr, u32 bcr, u32 chcr);
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#ifndef ENABLE_NEW_IOPDMA_SPU2
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extern void psxDma4(u32 madr, u32 bcr, u32 chcr);
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extern void psxDma7(u32 madr, u32 bcr, u32 chcr);
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#endif
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#ifndef ENABLE_NEW_IOPDMA_DEV9
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extern void psxDma8(u32 madr, u32 bcr, u32 chcr);
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#endif
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extern void psxDma9(u32 madr, u32 bcr, u32 chcr);
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extern void psxDma10(u32 madr, u32 bcr, u32 chcr);
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@ -233,8 +233,14 @@ _DEV9read32 DEV9read32;
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_DEV9write8 DEV9write8;
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_DEV9write16 DEV9write16;
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_DEV9write32 DEV9write32;
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#ifdef ENABLE_NEW_IOPDMA_DEV9
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_DEV9dmaRead DEV9dmaRead;
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_DEV9dmaWrite DEV9dmaWrite;
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_DEV9dmaInterrupt DEV9dmaInterrupt;
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#else
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_DEV9readDMA8Mem DEV9readDMA8Mem;
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_DEV9writeDMA8Mem DEV9writeDMA8Mem;
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#endif
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_DEV9irqCallback DEV9irqCallback;
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_DEV9irqHandler DEV9irqHandler;
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@ -517,8 +523,14 @@ static const LegacyApi_ReqMethod s_MethMessReq_DEV9[] =
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{ "DEV9write8", (vMeth**)&DEV9write8, NULL },
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{ "DEV9write16", (vMeth**)&DEV9write16, NULL },
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{ "DEV9write32", (vMeth**)&DEV9write32, NULL },
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#ifdef ENABLE_NEW_IOPDMA_DEV9
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{ "DEV9dmaRead", (vMeth**)&DEV9dmaRead, NULL },
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{ "DEV9dmaWrite", (vMeth**)&DEV9dmaWrite, NULL },
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{ "DEV9dmaInterrupt", (vMeth**)&DEV9dmaInterrupt, NULL },
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#else
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{ "DEV9readDMA8Mem", (vMeth**)&DEV9readDMA8Mem, NULL },
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{ "DEV9writeDMA8Mem", (vMeth**)&DEV9writeDMA8Mem, NULL },
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#endif
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{ "DEV9irqCallback", (vMeth**)&DEV9irqCallback, NULL },
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{ "DEV9irqHandler", (vMeth**)&DEV9irqHandler, NULL },
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@ -379,7 +379,11 @@ static __forceinline void _HwWrite_16or32_Page1( u32 addr, T val )
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mcase(0x1f801518): // DMA8 CHCR -- DEV9
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psxHu(addr) = val;
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#ifdef ENABLE_NEW_IOPDMA_DEV9
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DmaExecNew2(8);
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#else
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DmaExec2(8);
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#endif
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break;
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mcase(0x1f801528): // DMA9 CHCR -- SIF0
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