mirror of https://github.com/PCSX2/pcsx2.git
changed the counters algorithm again; some games didn't like the algorithm from 228...
git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@240 a6443dda-0b58-4228-96e9-037be469359c
This commit is contained in:
cottonvibes
Gregory Hainaut
parent
c9e333b4d5
commit
86c35c57b0
118
pcsx2/Counters.c
118
pcsx2/Counters.c
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@ -52,7 +52,7 @@ void rcntSet() {
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u32 c;
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int i;
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nextCounter = 0xffffffff;
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nextCounter = HBLANK_TIME_;
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nextsCounter = cpuRegs.cycle;
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for (i = 0; i < 4; i++) {
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@ -67,6 +67,7 @@ void rcntSet() {
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}
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//Calculate HBlank
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/*
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if (counters[4].mode & MODE_HBLANK) { //hBlank
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if (Config.PsxType&1) { if (HBLANK_TIME_PAL < nextCounter) nextCounter = HBLANK_TIME_PAL; }
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else if (HBLANK_TIME_NTSC < nextCounter) nextCounter = HBLANK_TIME_NTSC;
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@ -74,7 +75,7 @@ void rcntSet() {
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else { //not hBlank (drawing part of the scanline)
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if (Config.PsxType&1) { if (HRENDER_TIME_PAL < nextCounter) nextCounter = HRENDER_TIME_PAL; }
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else if (HRENDER_TIME_NTSC < nextCounter) nextCounter = HRENDER_TIME_NTSC;
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}
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}*/
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}
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void rcntInit() {
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@ -144,7 +145,7 @@ void UpdateVSyncRate() {
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counters[4].sCycle = cpuRegs.cycle; // Update Counter 4's Start Cycle to match CPU's cycle
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counters[5].mode = MODE_VRENDER; // Counter 5 takes care of vSync/vBlanks
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counters[5].rate = MODE_VBLANK1; // Rate is just used to alternate between vBlank1 and vBlank2 modes (because of interlacing, one half-frame can have a different number of vBlank scanlines)
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counters[5].sCycle = cpuRegs.cycle; // Update Counter 5's Start Cycle to match CPU's cycle
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if (Config.CustomFps > 0) {
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iTicks = GetTickFrequency() / Config.CustomFps;
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@ -339,6 +340,19 @@ __forceinline void frameLimit()
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}
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}
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__forceinline void VBlankStart()
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{
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psxVBlankStart(); // psxCounters vBlank Start
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if (gates) rcntStartGate(0x8); // Counters Start Gate code
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}
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__forceinline void VBlankEnd()
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{
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psxVBlankEnd(); // psxCounters vBlank End
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if (gates) rcntEndGate(0x8); // Counters End Gate Code
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SysUpdate(); // check for and handle keyevents
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}
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__forceinline void VSyncStart() // VSync Start (240 hsyncs)
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{
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vSyncDebugStuff(); // EE Profiling and Debug code
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@ -346,8 +360,8 @@ __forceinline void VSyncStart() // VSync Start (240 hsyncs)
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if (!(GSIMR&0x800)) gsIrq(); //GS Irq
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hwIntcIrq(2); // HW Irq
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VBlankStart();
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if (Config.Patch) applypatch(1); // Apply patches (ToDo: clean up patch code)
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}
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__forceinline void VSyncEnd() // VSync End (22 hsyncs)
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@ -365,110 +379,64 @@ __forceinline void VSyncEnd() // VSync End (22 hsyncs)
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}
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hwIntcIrq(3); // HW Irq
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VBlankEnd();
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frameLimit(); // limit FPS (also handles frameskip and VUskip)
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}
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__forceinline void VBlankStart()
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{
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psxVBlankStart(); // psxCounters vSync Start
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if (gates) rcntStartGate(0x8); // Counters Start Gate code
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}
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__forceinline void VBlankEnd()
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{
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psxVBlankEnd(); // psxCounters vBlank End
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if (gates) rcntEndGate(0x8); // Counters End Gate Code
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SysUpdate(); // check for and handle keyevents
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}
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#define hScanlineOptimization(diff, compareValue, incrementCounters) { \
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if (diff >= compareValue) { \
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u32 increment = (diff / compareValue); \
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SysPrintf("Counters Optimization\n"); \
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counters[4].count += increment; \
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if (incrementCounters) { \
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/*Update counters using the hblank as the clock*/ \
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if ((counters[0].mode & 0x83) == 0x83) counters[0].count += (increment * HBLANK_COUNTER_SPEED); \
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if ((counters[1].mode & 0x83) == 0x83) counters[1].count += (increment * HBLANK_COUNTER_SPEED); \
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if ((counters[2].mode & 0x83) == 0x83) counters[2].count += (increment * HBLANK_COUNTER_SPEED); \
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if ((counters[3].mode & 0x83) == 0x83) counters[3].count += (increment * HBLANK_COUNTER_SPEED); \
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u32 increment = (diff / compareValue); \
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/* if counter's count increases on hblank gate's off signal OR if counter increases every hblank, THEN add to the counter */ \
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if ( (!(counters[0].mode & 0x30) && (gates & (1<<0))) || (((counters[0].mode & 0x83) == 0x83) && !(gates & (1<<0))) ) counters[0].count += (increment * HBLANK_COUNTER_SPEED); \
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if ( (!(counters[1].mode & 0x30) && (gates & (1<<1))) || (((counters[1].mode & 0x83) == 0x83) && !(gates & (1<<1))) ) counters[1].count += (increment * HBLANK_COUNTER_SPEED); \
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if ( (!(counters[2].mode & 0x30) && (gates & (1<<2))) || (((counters[2].mode & 0x83) == 0x83) && !(gates & (1<<2))) ) counters[2].count += (increment * HBLANK_COUNTER_SPEED); \
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if ( (!(counters[3].mode & 0x30) && (gates & (1<<3))) || (((counters[3].mode & 0x83) == 0x83) && !(gates & (1<<3))) ) counters[3].count += (increment * HBLANK_COUNTER_SPEED); \
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} \
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} \
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}
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int hScanline()
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__forceinline void hScanline()
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{
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u32 difference = (cpuRegs.cycle - counters[4].sCycle);
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if (counters[4].mode & MODE_HBLANK) { //HBLANK Start
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if (difference >= HBLANK_TIME_ ) {
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//hScanlineOptimization(difference, (SCANLINE_ + HBLANK_TIME_), 1);
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hScanlineOptimization(difference, (SCANLINE_ + HBLANK_TIME_), 1);
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rcntStartGate(0);
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psxCheckStartGate(0);
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counters[4].sCycle = cpuRegs.cycle;
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counters[4].mode ^= MODE_HBLANK;
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counters[4].mode = MODE_HRENDER;
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}
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}
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else { //HBLANK END / HRENDER Begin
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if (difference >= (HRENDER_TIME_)) {
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//hScanlineOptimization(difference, (SCANLINE_ + HRENDER_TIME_), 0);
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hScanlineOptimization(difference, (SCANLINE_ + HRENDER_TIME_), 1);
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if (CSRw & 0x4) GSCSRr |= 4; // signal
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if (!(GSIMR&0x400)) gsIrq();
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if (gates) rcntEndGate(0);
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if (psxhblankgate) psxCheckEndGate(0);
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counters[4].count += HBLANK_COUNTER_SPEED; //increment counter!
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counters[4].sCycle = cpuRegs.cycle;
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counters[4].mode ^= MODE_HBLANK;
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return 0; // Count Incremented
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counters[4].mode = MODE_HBLANK;
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}
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}
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return 1; // Count not Incremented
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}
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void vSync()
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{
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if (hScanline()) return; // render the next scanline; if no-change, then exit function
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hScanline();
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switch (counters[5].mode) {
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case MODE_VRENDER: //vRender is running
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if (counters[4].count > SCANLINES_VRENDER_) { // Check if should change state to VBlank
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//VRENDER END/VBLANK START CODE HERE:
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VBlankStart();
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counters[4].count -= SCANLINES_VRENDER_;
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counters[5].mode = MODE_VBLANK; // Set to VBLANK MODE
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}
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break;
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case MODE_VBLANK: //vBlank is running
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if (counters[5].rate == MODE_VBLANK1) {
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if (counters[4].count > SCANLINES_VBLANK1_) { //Check if should change state to VSYNC
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//VBLANK END/VSYNC START CODE HERE:
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VBlankEnd();
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VSyncStart();
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counters[4].count -= SCANLINES_VBLANK1_;
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counters[5].mode = MODE_VSYNC; // Set to VSYNC MODE
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counters[5].rate = MODE_VBLANK2;
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}
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}
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else {
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if (counters[4].count > SCANLINES_VBLANK2_) { //Check if should change state to VSYNC
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//VBLANK END/VSYNC START CODE HERE:
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VBlankEnd();
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VSyncStart();
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counters[4].count -= SCANLINES_VBLANK2_;
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counters[5].mode = MODE_VSYNC; // Set to VSYNC MODE
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counters[5].rate = MODE_VBLANK1;
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}
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}
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break;
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case MODE_VSYNC: //vSync is running
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if (counters[4].count > SCANLINES_VSYNC_) { //Check if should change state to VRENDER
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//VSYNC END/RENDER START CODE HERE:
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VSyncEnd();
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counters[4].count -= SCANLINES_VSYNC_;
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counters[5].mode = MODE_VRENDER; // Set to VRENDER MODE
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}
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break;
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if ((cpuRegs.cycle - counters[5].sCycle) >= (VSYNC_ / 2)) {
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if (counters[5].mode == MODE_VSYNC) {
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VSyncEnd();
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counters[5].mode = MODE_VRENDER;
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}
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else {
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VSyncStart();
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counters[5].mode = MODE_VSYNC;
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}
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counters[5].sCycle = cpuRegs.cycle;
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}
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}
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@ -602,8 +570,8 @@ void rcntStartGate(unsigned int mode) {
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switch (counters[i].mode & 0x30) {
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case 0x00: //Count When Signal is low (off)
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counters[i].mode &= ~0x80; // Stop Counting since signal is On
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rcntUpd(i);
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counters[i].mode |= 0x80;
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break;
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case 0x10: //Reset and start counting on Vsync start
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case 0x30: //Reset and start counting on Vsync start and end
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@ -624,9 +592,9 @@ void rcntEndGate(unsigned int mode) {
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switch (counters[i].mode & 0x30) {
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case 0x00: //Count When Signal is low (off)
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counters[i].mode |= 0x80; // Start Counting since signal is Off
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counters[i].count = rcntRcount(i);
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rcntUpd(i);
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counters[i].mode &= ~0x80;
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break;
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case 0x20: //Reset and start counting on Vsync end
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case 0x30: //Reset and start counting on Vsync start and end
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@ -35,10 +35,11 @@ typedef struct {
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//------------------------------------------------------------------
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// NTSC Timing Information!!! (some scanline info is guessed)
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//------------------------------------------------------------------
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#define SCANLINE_NTSC 18743 //(PS2CLK / 15734.25)
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#define HRENDER_TIME_NTSC 15528 //time from hblank end to hblank start (PS2CLK / 18991.368423051722991900181367568)
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#define HBLANK_TIME_NTSC 3215 //time from hblank start to hblank end (PS2CLK / 91738.91105912572817760653181028)
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#define SCANLINE_NTSC (PS2CLK / 15734.25)//18743
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#define HRENDER_TIME_NTSC (u32)(SCANLINE_NTSC / 2)//15528 //time from hblank end to hblank start (PS2CLK / 18991.368423051722991900181367568)
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#define HBLANK_TIME_NTSC (u32)(SCANLINE_NTSC / 2)//3215 //time from hblank start to hblank end (PS2CLK / 91738.91105912572817760653181028)
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#define VSYNC_NTSC (PS2CLK / 59.94) //hz
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#define VSYNC_HALF_NTSC (VSYNC_NTSC / 2) //hz
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#define SCANLINES_TOTAL_NTSC 525 // total number of scanlines
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#define SCANLINES_VSYNC_NTSC 3 // scanlines that are used for syncing every half-frame
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@ -49,10 +50,11 @@ typedef struct {
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//------------------------------------------------------------------
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// PAL Timing Information!!! (some scanline info is guessed)
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//------------------------------------------------------------------
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#define SCANLINE_PAL 18874
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#define HRENDER_TIME_PAL 15335 //time from hblank end to hblank start
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#define HBLANK_TIME_PAL 3539 //time from hblank start to hblank end
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#define VSYNC_PAL (PS2CLK / 50) //hz
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#define SCANLINE_PAL (PS2CLK / 15625)//18874
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#define HRENDER_TIME_PAL (u32)(SCANLINE_PAL / 2)//15335 //time from hblank end to hblank start
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#define HBLANK_TIME_PAL (u32)(SCANLINE_PAL / 2)//3539 //time from hblank start to hblank end
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#define VSYNC_PAL (PS2CLK / 50) //hz
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#define VSYNC_HALF_PAL (VSYNC_PAL / 2) //hz
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#define SCANLINES_TOTAL_PAL 625 // total number of scanlines
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#define SCANLINES_VSYNC_PAL 5 // scanlines that are used for syncing every half-frame
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@ -67,6 +69,7 @@ typedef struct {
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#define HRENDER_TIME_ (u32)((Config.PsxType&1) ? HRENDER_TIME_PAL : HRENDER_TIME_NTSC) * HBLANK_TIMER_SLOWDOWN
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#define HBLANK_TIME_ (u32)((Config.PsxType&1) ? HBLANK_TIME_PAL : HBLANK_TIME_NTSC) * HBLANK_TIMER_SLOWDOWN
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#define VSYNC_ (u32)((Config.PsxType&1) ? VSYNC_PAL : VSYNC_NTSC)
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#define VSYNC_HALF_ (u32)((Config.PsxType&1) ? VSYNC_HALF_PAL : VSYNC_HALF_NTSC)
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#define SCANLINES_TOTAL_ (u32)((Config.PsxType&1) ? SCANLINES_TOTAL_PAL : SCANLINES_TOTAL_NTSC)
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#define SCANLINES_VSYNC_ (u32)((Config.PsxType&1) ? SCANLINES_VSYNC_PAL : SCANLINES_VSYNC_NTSC)
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