From d2da341f6eb1d171d6cc697ac31a02925494dc0a Mon Sep 17 00:00:00 2001 From: TheLastRar Date: Mon, 13 Jan 2025 21:06:05 +0000 Subject: [PATCH] 3rdparty: Sync vixl to commit e6076e92c416422ea1fbde815e8e327f68658ac1 --- .../vixl/include/vixl/aarch64/abi-aarch64.h | 4 +- .../include/vixl/aarch64/assembler-aarch64.h | 141 + .../include/vixl/aarch64/constants-aarch64.h | 4241 +++++++++-------- .../aarch64/cpu-features-auditor-aarch64.h | 3 + .../include/vixl/aarch64/debugger-aarch64.h | 276 ++ .../vixl/aarch64/decoder-constants-aarch64.h | 2 +- .../aarch64/decoder-visitor-map-aarch64.h | 25 +- .../include/vixl/aarch64/disasm-aarch64.h | 7 + .../vixl/aarch64/instructions-aarch64.h | 28 +- .../vixl/aarch64/macro-assembler-aarch64.h | 100 +- .../include/vixl/aarch64/operands-aarch64.h | 6 +- .../include/vixl/aarch64/registers-aarch64.h | 5 +- .../include/vixl/aarch64/simulator-aarch64.h | 494 +- .../vixl/include/vixl/assembler-base-vixl.h | 3 + 3rdparty/vixl/include/vixl/code-buffer-vixl.h | 29 + .../vixl/code-generation-scopes-vixl.h | 21 +- .../include/vixl/compiler-intrinsics-vixl.h | 4 +- 3rdparty/vixl/include/vixl/cpu-features.h | 3 +- 3rdparty/vixl/include/vixl/globals-vixl.h | 16 +- 3rdparty/vixl/include/vixl/invalset-vixl.h | 31 +- .../vixl/include/vixl/pool-manager-impl.h | 8 +- 3rdparty/vixl/include/vixl/pool-manager.h | 3 +- 3rdparty/vixl/include/vixl/utils-vixl.h | 49 +- .../vixl/src/aarch64/assembler-aarch64.cc | 371 +- .../aarch64/cpu-features-auditor-aarch64.cc | 218 +- 3rdparty/vixl/src/aarch64/decoder-aarch64.cc | 3 +- 3rdparty/vixl/src/aarch64/disasm-aarch64.cc | 165 +- .../vixl/src/aarch64/instructions-aarch64.cc | 8 + 3rdparty/vixl/src/aarch64/logic-aarch64.cc | 1005 +++- .../src/aarch64/macro-assembler-aarch64.cc | 99 +- 3rdparty/vixl/src/aarch64/operands-aarch64.cc | 4 +- .../vixl/src/aarch64/pointer-auth-aarch64.cc | 6 +- .../vixl/src/aarch64/registers-aarch64.cc | 11 +- 3rdparty/vixl/src/code-buffer-vixl.cc | 98 +- 3rdparty/vixl/src/compiler-intrinsics-vixl.cc | 1 + 3rdparty/vixl/src/cpu-features.cc | 3 +- 3rdparty/vixl/vixl.vcxproj | 1 + 3rdparty/vixl/vixl.vcxproj.filters | 3 + 38 files changed, 4870 insertions(+), 2625 deletions(-) create mode 100644 3rdparty/vixl/include/vixl/aarch64/debugger-aarch64.h diff --git a/3rdparty/vixl/include/vixl/aarch64/abi-aarch64.h b/3rdparty/vixl/include/vixl/aarch64/abi-aarch64.h index 7e6cd9a41f..388cf10f2d 100644 --- a/3rdparty/vixl/include/vixl/aarch64/abi-aarch64.h +++ b/3rdparty/vixl/include/vixl/aarch64/abi-aarch64.h @@ -159,8 +159,8 @@ template <> inline GenericOperand ABI::GetReturnGenericOperand() const { return GenericOperand(); } -} -} // namespace vixl::aarch64 +} // namespace aarch64 +} // namespace vixl #endif // VIXL_AARCH64_ABI_AARCH64_H_ diff --git a/3rdparty/vixl/include/vixl/aarch64/assembler-aarch64.h b/3rdparty/vixl/include/vixl/aarch64/assembler-aarch64.h index 636fbdb913..c1e4e6a787 100644 --- a/3rdparty/vixl/include/vixl/aarch64/assembler-aarch64.h +++ b/3rdparty/vixl/include/vixl/aarch64/assembler-aarch64.h @@ -33,6 +33,7 @@ #include "../globals-vixl.h" #include "../invalset-vixl.h" #include "../utils-vixl.h" + #include "operands-aarch64.h" namespace vixl { @@ -403,6 +404,15 @@ enum LoadStoreScalingOption { // Assembler. class Assembler : public vixl::internal::AssemblerBase { public: + explicit Assembler( + PositionIndependentCodeOption pic = PositionIndependentCode) + : pic_(pic), cpu_features_(CPUFeatures::AArch64LegacyBaseline()) {} + explicit Assembler( + size_t capacity, + PositionIndependentCodeOption pic = PositionIndependentCode) + : AssemblerBase(capacity), + pic_(pic), + cpu_features_(CPUFeatures::AArch64LegacyBaseline()) {} Assembler(byte* buffer, size_t capacity, PositionIndependentCodeOption pic = PositionIndependentCode) @@ -2148,6 +2158,9 @@ class Assembler : public vixl::internal::AssemblerBase { // System instruction with pre-encoded op (op1:crn:crm:op2). void sys(int op, const Register& xt = xzr); + // System instruction with result. + void sysl(int op, const Register& xt = xzr); + // System data cache operation. void dc(DataCacheOp op, const Register& rt); @@ -3608,6 +3621,117 @@ class Assembler : public vixl::internal::AssemblerBase { // Unsigned 8-bit integer matrix multiply-accumulate (vector). void ummla(const VRegister& vd, const VRegister& vn, const VRegister& vm); + // Bit Clear and exclusive-OR. + void bcax(const VRegister& vd, + const VRegister& vn, + const VRegister& vm, + const VRegister& va); + + // Three-way Exclusive-OR. + void eor3(const VRegister& vd, + const VRegister& vn, + const VRegister& vm, + const VRegister& va); + + // Exclusive-OR and Rotate. + void xar(const VRegister& vd, + const VRegister& vn, + const VRegister& vm, + int rotate); + + // Rotate and Exclusive-OR + void rax1(const VRegister& vd, const VRegister& vn, const VRegister& vm); + + // SHA1 hash update (choose). + void sha1c(const VRegister& vd, const VRegister& vn, const VRegister& vm); + + // SHA1 fixed rotate. + void sha1h(const VRegister& sd, const VRegister& sn); + + // SHA1 hash update (majority). + void sha1m(const VRegister& vd, const VRegister& vn, const VRegister& vm); + + // SHA1 hash update (parity). + void sha1p(const VRegister& vd, const VRegister& vn, const VRegister& vm); + + // SHA1 schedule update 0. + void sha1su0(const VRegister& vd, const VRegister& vn, const VRegister& vm); + + // SHA1 schedule update 1. + void sha1su1(const VRegister& vd, const VRegister& vn); + + // SHA256 hash update (part 1). + void sha256h(const VRegister& vd, const VRegister& vn, const VRegister& vm); + + // SHA256 hash update (part 2). + void sha256h2(const VRegister& vd, const VRegister& vn, const VRegister& vm); + + // SHA256 schedule update 0. + void sha256su0(const VRegister& vd, const VRegister& vn); + + // SHA256 schedule update 1. + void sha256su1(const VRegister& vd, const VRegister& vn, const VRegister& vm); + + // SHA512 hash update part 1. + void sha512h(const VRegister& vd, const VRegister& vn, const VRegister& vm); + + // SHA512 hash update part 2. + void sha512h2(const VRegister& vd, const VRegister& vn, const VRegister& vm); + + // SHA512 schedule Update 0. + void sha512su0(const VRegister& vd, const VRegister& vn); + + // SHA512 schedule Update 1. + void sha512su1(const VRegister& vd, const VRegister& vn, const VRegister& vm); + + // AES single round decryption. + void aesd(const VRegister& vd, const VRegister& vn); + + // AES single round encryption. + void aese(const VRegister& vd, const VRegister& vn); + + // AES inverse mix columns. + void aesimc(const VRegister& vd, const VRegister& vn); + + // AES mix columns. + void aesmc(const VRegister& vd, const VRegister& vn); + + // SM3PARTW1. + void sm3partw1(const VRegister& vd, const VRegister& vn, const VRegister& vm); + + // SM3PARTW2. + void sm3partw2(const VRegister& vd, const VRegister& vn, const VRegister& vm); + + // SM3SS1. + void sm3ss1(const VRegister& vd, + const VRegister& vn, + const VRegister& vm, + const VRegister& va); + + // SM3TT1A. + void sm3tt1a(const VRegister& vd, + const VRegister& vn, + const VRegister& vm, + int index); + + // SM3TT1B. + void sm3tt1b(const VRegister& vd, + const VRegister& vn, + const VRegister& vm, + int index); + + // SM3TT2A. + void sm3tt2a(const VRegister& vd, + const VRegister& vn, + const VRegister& vm, + int index); + + // SM3TT2B. + void sm3tt2b(const VRegister& vd, + const VRegister& vn, + const VRegister& vm, + int index); + // Scalable Vector Extensions. // Absolute value (predicated). @@ -7062,6 +7186,21 @@ class Assembler : public vixl::internal::AssemblerBase { // Unsigned Minimum. void umin(const Register& rd, const Register& rn, const Operand& op); + // Check feature status. + void chkfeat(const Register& rd); + + // Guarded Control Stack Push. + void gcspushm(const Register& rt); + + // Guarded Control Stack Pop. + void gcspopm(const Register& rt); + + // Guarded Control Stack Switch Stack 1. + void gcsss1(const Register& rt); + + // Guarded Control Stack Switch Stack 2. + void gcsss2(const Register& rt); + // Emit generic instructions. // Emit raw instructions into the instruction stream. @@ -7530,6 +7669,8 @@ class Assembler : public vixl::internal::AssemblerBase { static Instr VFormat(VRegister vd) { if (vd.Is64Bits()) { switch (vd.GetLanes()) { + case 1: + return NEON_1D; case 2: return NEON_2S; case 4: diff --git a/3rdparty/vixl/include/vixl/aarch64/constants-aarch64.h b/3rdparty/vixl/include/vixl/aarch64/constants-aarch64.h index 6982271e7f..bcfed30d95 100644 --- a/3rdparty/vixl/include/vixl/aarch64/constants-aarch64.h +++ b/3rdparty/vixl/include/vixl/aarch64/constants-aarch64.h @@ -394,7 +394,8 @@ enum SystemHint { BTI = 32, BTI_c = 34, BTI_j = 36, - BTI_jc = 38 + BTI_jc = 38, + CHKFEAT = 40 }; enum BranchTargetIdentifier { @@ -501,7 +502,7 @@ class SystemRegisterEncoder { // System/special register names. // This information is not encoded as one field but as the concatenation of // multiple fields (Op0, Op1, Crn, Crm, Op2). -enum SystemRegister { +enum SystemRegister : uint32_t { NZCV = SystemRegisterEncoder<3, 3, 4, 2, 0>::value, FPCR = SystemRegisterEncoder<3, 3, 4, 4, 0>::value, RNDR = SystemRegisterEncoder<3, 3, 2, 4, 0>::value, // Random number. @@ -518,11 +519,11 @@ class CacheOpEncoder { (op2 << SysOp2_offset)) >> SysOp_offset; }; -enum InstructionCacheOp { +enum InstructionCacheOp : uint32_t { IVAU = CacheOpEncoder<3, 7, 5, 1>::value }; -enum DataCacheOp { +enum DataCacheOp : uint32_t { CVAC = CacheOpEncoder<3, 7, 10, 1>::value, CVAU = CacheOpEncoder<3, 7, 11, 1>::value, CVAP = CacheOpEncoder<3, 7, 12, 1>::value, @@ -539,6 +540,13 @@ enum DataCacheOp { CIGDVAC = CacheOpEncoder<3, 7, 14, 5>::value }; +enum GCSOp : uint32_t { + GCSPUSHM = CacheOpEncoder<3, 7, 7, 0>::value, + GCSPOPM = CacheOpEncoder<3, 7, 7, 1>::value, + GCSSS1 = CacheOpEncoder<3, 7, 7, 2>::value, + GCSSS2 = CacheOpEncoder<3, 7, 7, 3>::value +}; + // Some SVE instructions support a predicate constraint pattern. This is // interpreted as a VL-dependent value, and is typically used to initialise // predicates, or to otherwise limit the number of processed elements. @@ -591,30 +599,30 @@ enum SVEPredicateConstraint { // Generic fields. enum GenericInstrField : uint32_t { - SixtyFourBits = 0x80000000u, - ThirtyTwoBits = 0x00000000u, + SixtyFourBits = 0x80000000, + ThirtyTwoBits = 0x00000000, - FPTypeMask = 0x00C00000u, - FP16 = 0x00C00000u, - FP32 = 0x00000000u, - FP64 = 0x00400000u + FPTypeMask = 0x00C00000, + FP16 = 0x00C00000, + FP32 = 0x00000000, + FP64 = 0x00400000 }; enum NEONFormatField : uint32_t { - NEONFormatFieldMask = 0x40C00000u, - NEON_Q = 0x40000000u, - NEON_8B = 0x00000000u, + NEONFormatFieldMask = 0x40C00000, + NEON_Q = 0x40000000, + NEON_8B = 0x00000000, NEON_16B = NEON_8B | NEON_Q, - NEON_4H = 0x00400000u, + NEON_4H = 0x00400000, NEON_8H = NEON_4H | NEON_Q, - NEON_2S = 0x00800000u, + NEON_2S = 0x00800000, NEON_4S = NEON_2S | NEON_Q, - NEON_1D = 0x00C00000u, - NEON_2D = 0x00C00000u | NEON_Q + NEON_1D = 0x00C00000, + NEON_2D = 0x00C00000 | NEON_Q }; enum NEONFPFormatField : uint32_t { - NEONFPFormatFieldMask = 0x40400000u, + NEONFPFormatFieldMask = 0x40400000, NEON_FP_4H = FP16, NEON_FP_2S = FP32, NEON_FP_8H = FP16 | NEON_Q, @@ -623,27 +631,27 @@ enum NEONFPFormatField : uint32_t { }; enum NEONLSFormatField : uint32_t { - NEONLSFormatFieldMask = 0x40000C00u, - LS_NEON_8B = 0x00000000u, + NEONLSFormatFieldMask = 0x40000C00, + LS_NEON_8B = 0x00000000, LS_NEON_16B = LS_NEON_8B | NEON_Q, - LS_NEON_4H = 0x00000400u, + LS_NEON_4H = 0x00000400, LS_NEON_8H = LS_NEON_4H | NEON_Q, - LS_NEON_2S = 0x00000800u, + LS_NEON_2S = 0x00000800, LS_NEON_4S = LS_NEON_2S | NEON_Q, - LS_NEON_1D = 0x00000C00u, + LS_NEON_1D = 0x00000C00, LS_NEON_2D = LS_NEON_1D | NEON_Q }; enum NEONScalarFormatField : uint32_t { - NEONScalarFormatFieldMask = 0x00C00000u, - NEONScalar = 0x10000000u, - NEON_B = 0x00000000u, - NEON_H = 0x00400000u, - NEON_S = 0x00800000u, - NEON_D = 0x00C00000u + NEONScalarFormatFieldMask = 0x00C00000, + NEONScalar = 0x10000000, + NEON_B = 0x00000000, + NEON_H = 0x00400000, + NEON_S = 0x00800000, + NEON_D = 0x00C00000 }; -enum SVESizeField { +enum SVESizeField : uint32_t { SVESizeFieldMask = 0x00C00000, SVE_B = 0x00000000, SVE_H = 0x00400000, @@ -653,21 +661,21 @@ enum SVESizeField { // PC relative addressing. enum PCRelAddressingOp : uint32_t { - PCRelAddressingFixed = 0x10000000u, - PCRelAddressingFMask = 0x1F000000u, - PCRelAddressingMask = 0x9F000000u, - ADR = PCRelAddressingFixed | 0x00000000u, - ADRP = PCRelAddressingFixed | 0x80000000u + PCRelAddressingFixed = 0x10000000, + PCRelAddressingFMask = 0x1F000000, + PCRelAddressingMask = 0x9F000000, + ADR = PCRelAddressingFixed | 0x00000000, + ADRP = PCRelAddressingFixed | 0x80000000 }; // Add/sub (immediate, shifted and extended.) const int kSFOffset = 31; enum AddSubOp : uint32_t { - AddSubOpMask = 0x60000000u, - AddSubSetFlagsBit = 0x20000000u, - ADD = 0x00000000u, + AddSubOpMask = 0x60000000, + AddSubSetFlagsBit = 0x20000000, + ADD = 0x00000000, ADDS = ADD | AddSubSetFlagsBit, - SUB = 0x40000000u, + SUB = 0x40000000, SUBS = SUB | AddSubSetFlagsBit }; @@ -678,9 +686,9 @@ enum AddSubOp : uint32_t { V(SUBS) enum AddSubImmediateOp : uint32_t { - AddSubImmediateFixed = 0x11000000u, - AddSubImmediateFMask = 0x1F800000u, - AddSubImmediateMask = 0xFF800000u, + AddSubImmediateFixed = 0x11000000, + AddSubImmediateFMask = 0x1F800000, + AddSubImmediateMask = 0xFF800000, #define ADD_SUB_IMMEDIATE(A) \ A##_w_imm = AddSubImmediateFixed | A, \ A##_x_imm = AddSubImmediateFixed | A | SixtyFourBits @@ -688,10 +696,10 @@ enum AddSubImmediateOp : uint32_t { #undef ADD_SUB_IMMEDIATE }; -enum AddSubShiftedOp : uint32_t { - AddSubShiftedFixed = 0x0B000000u, - AddSubShiftedFMask = 0x1F200000u, - AddSubShiftedMask = 0xFF200000u, +enum AddSubShiftedOp : uint32_t { + AddSubShiftedFixed = 0x0B000000, + AddSubShiftedFMask = 0x1F200000, + AddSubShiftedMask = 0xFF200000, #define ADD_SUB_SHIFTED(A) \ A##_w_shift = AddSubShiftedFixed | A, \ A##_x_shift = AddSubShiftedFixed | A | SixtyFourBits @@ -700,9 +708,9 @@ enum AddSubShiftedOp : uint32_t { }; enum AddSubExtendedOp : uint32_t { - AddSubExtendedFixed = 0x0B200000u, - AddSubExtendedFMask = 0x1F200000u, - AddSubExtendedMask = 0xFFE00000u, + AddSubExtendedFixed = 0x0B200000, + AddSubExtendedFMask = 0x1F200000, + AddSubExtendedMask = 0xFFE00000, #define ADD_SUB_EXTENDED(A) \ A##_w_ext = AddSubExtendedFixed | A, \ A##_x_ext = AddSubExtendedFixed | A | SixtyFourBits @@ -712,9 +720,9 @@ enum AddSubExtendedOp : uint32_t { // Add/sub with carry. enum AddSubWithCarryOp : uint32_t { - AddSubWithCarryFixed = 0x1A000000u, - AddSubWithCarryFMask = 0x1FE00000u, - AddSubWithCarryMask = 0xFFE0FC00u, + AddSubWithCarryFixed = 0x1A000000, + AddSubWithCarryFMask = 0x1FE00000, + AddSubWithCarryMask = 0xFFE0FC00, ADC_w = AddSubWithCarryFixed | ADD, ADC_x = AddSubWithCarryFixed | ADD | SixtyFourBits, ADC = ADC_w, @@ -729,41 +737,41 @@ enum AddSubWithCarryOp : uint32_t { // Rotate right into flags. enum RotateRightIntoFlagsOp : uint32_t { - RotateRightIntoFlagsFixed = 0x1A000400u, - RotateRightIntoFlagsFMask = 0x1FE07C00u, - RotateRightIntoFlagsMask = 0xFFE07C10u, - RMIF = RotateRightIntoFlagsFixed | 0xA0000000u + RotateRightIntoFlagsFixed = 0x1A000400, + RotateRightIntoFlagsFMask = 0x1FE07C00, + RotateRightIntoFlagsMask = 0xFFE07C10, + RMIF = RotateRightIntoFlagsFixed | 0xA0000000 }; // Evaluate into flags. enum EvaluateIntoFlagsOp : uint32_t { - EvaluateIntoFlagsFixed = 0x1A000800u, - EvaluateIntoFlagsFMask = 0x1FE03C00u, - EvaluateIntoFlagsMask = 0xFFE07C1Fu, - SETF8 = EvaluateIntoFlagsFixed | 0x2000000Du, - SETF16 = EvaluateIntoFlagsFixed | 0x2000400Du + EvaluateIntoFlagsFixed = 0x1A000800, + EvaluateIntoFlagsFMask = 0x1FE03C00, + EvaluateIntoFlagsMask = 0xFFE07C1F, + SETF8 = EvaluateIntoFlagsFixed | 0x2000000D, + SETF16 = EvaluateIntoFlagsFixed | 0x2000400D }; // Logical (immediate and shifted register). enum LogicalOp : uint32_t { - LogicalOpMask = 0x60200000u, - NOT = 0x00200000u, - AND = 0x00000000u, + LogicalOpMask = 0x60200000, + NOT = 0x00200000, + AND = 0x00000000, BIC = AND | NOT, - ORR = 0x20000000u, + ORR = 0x20000000, ORN = ORR | NOT, - EOR = 0x40000000u, + EOR = 0x40000000, EON = EOR | NOT, - ANDS = 0x60000000u, + ANDS = 0x60000000, BICS = ANDS | NOT }; // Logical immediate. enum LogicalImmediateOp : uint32_t { - LogicalImmediateFixed = 0x12000000u, - LogicalImmediateFMask = 0x1F800000u, - LogicalImmediateMask = 0xFF800000u, + LogicalImmediateFixed = 0x12000000, + LogicalImmediateFMask = 0x1F800000, + LogicalImmediateMask = 0xFF800000, AND_w_imm = LogicalImmediateFixed | AND, AND_x_imm = LogicalImmediateFixed | AND | SixtyFourBits, ORR_w_imm = LogicalImmediateFixed | ORR, @@ -776,9 +784,9 @@ enum LogicalImmediateOp : uint32_t { // Logical shifted register. enum LogicalShiftedOp : uint32_t { - LogicalShiftedFixed = 0x0A000000u, - LogicalShiftedFMask = 0x1F000000u, - LogicalShiftedMask = 0xFF200000u, + LogicalShiftedFixed = 0x0A000000, + LogicalShiftedFMask = 0x1F000000, + LogicalShiftedMask = 0xFF200000, AND_w = LogicalShiftedFixed | AND, AND_x = LogicalShiftedFixed | AND | SixtyFourBits, AND_shift = AND_w, @@ -807,12 +815,12 @@ enum LogicalShiftedOp : uint32_t { // Move wide immediate. enum MoveWideImmediateOp : uint32_t { - MoveWideImmediateFixed = 0x12800000u, - MoveWideImmediateFMask = 0x1F800000u, - MoveWideImmediateMask = 0xFF800000u, - MOVN = 0x00000000u, - MOVZ = 0x40000000u, - MOVK = 0x60000000u, + MoveWideImmediateFixed = 0x12800000, + MoveWideImmediateFMask = 0x1F800000, + MoveWideImmediateMask = 0xFF800000, + MOVN = 0x00000000, + MOVZ = 0x40000000, + MOVK = 0x60000000, MOVN_w = MoveWideImmediateFixed | MOVN, MOVN_x = MoveWideImmediateFixed | MOVN | SixtyFourBits, MOVZ_w = MoveWideImmediateFixed | MOVZ, @@ -824,89 +832,89 @@ enum MoveWideImmediateOp : uint32_t { // Bitfield. const int kBitfieldNOffset = 22; enum BitfieldOp : uint32_t { - BitfieldFixed = 0x13000000u, - BitfieldFMask = 0x1F800000u, - BitfieldMask = 0xFF800000u, - SBFM_w = BitfieldFixed | 0x00000000u, - SBFM_x = BitfieldFixed | 0x80000000u, + BitfieldFixed = 0x13000000, + BitfieldFMask = 0x1F800000, + BitfieldMask = 0xFF800000, + SBFM_w = BitfieldFixed | 0x00000000, + SBFM_x = BitfieldFixed | 0x80000000, SBFM = SBFM_w, - BFM_w = BitfieldFixed | 0x20000000u, - BFM_x = BitfieldFixed | 0xA0000000u, + BFM_w = BitfieldFixed | 0x20000000, + BFM_x = BitfieldFixed | 0xA0000000, BFM = BFM_w, - UBFM_w = BitfieldFixed | 0x40000000u, - UBFM_x = BitfieldFixed | 0xC0000000u, + UBFM_w = BitfieldFixed | 0x40000000, + UBFM_x = BitfieldFixed | 0xC0000000, UBFM = UBFM_w // Bitfield N field. }; // Extract. enum ExtractOp : uint32_t { - ExtractFixed = 0x13800000u, - ExtractFMask = 0x1F800000u, - ExtractMask = 0xFFA00000u, - EXTR_w = ExtractFixed | 0x00000000u, - EXTR_x = ExtractFixed | 0x80000000u, + ExtractFixed = 0x13800000, + ExtractFMask = 0x1F800000, + ExtractMask = 0xFFA00000, + EXTR_w = ExtractFixed | 0x00000000, + EXTR_x = ExtractFixed | 0x80000000, EXTR = EXTR_w }; // Unconditional branch. enum UnconditionalBranchOp : uint32_t { - UnconditionalBranchFixed = 0x14000000u, - UnconditionalBranchFMask = 0x7C000000u, - UnconditionalBranchMask = 0xFC000000u, - B = UnconditionalBranchFixed | 0x00000000u, - BL = UnconditionalBranchFixed | 0x80000000u + UnconditionalBranchFixed = 0x14000000, + UnconditionalBranchFMask = 0x7C000000, + UnconditionalBranchMask = 0xFC000000, + B = UnconditionalBranchFixed | 0x00000000, + BL = UnconditionalBranchFixed | 0x80000000 }; // Unconditional branch to register. enum UnconditionalBranchToRegisterOp : uint32_t { - UnconditionalBranchToRegisterFixed = 0xD6000000u, - UnconditionalBranchToRegisterFMask = 0xFE000000u, - UnconditionalBranchToRegisterMask = 0xFFFFFC00u, - BR = UnconditionalBranchToRegisterFixed | 0x001F0000u, - BLR = UnconditionalBranchToRegisterFixed | 0x003F0000u, - RET = UnconditionalBranchToRegisterFixed | 0x005F0000u, + UnconditionalBranchToRegisterFixed = 0xD6000000, + UnconditionalBranchToRegisterFMask = 0xFE000000, + UnconditionalBranchToRegisterMask = 0xFFFFFC00, + BR = UnconditionalBranchToRegisterFixed | 0x001F0000, + BLR = UnconditionalBranchToRegisterFixed | 0x003F0000, + RET = UnconditionalBranchToRegisterFixed | 0x005F0000, - BRAAZ = UnconditionalBranchToRegisterFixed | 0x001F0800u, - BRABZ = UnconditionalBranchToRegisterFixed | 0x001F0C00u, - BLRAAZ = UnconditionalBranchToRegisterFixed | 0x003F0800u, - BLRABZ = UnconditionalBranchToRegisterFixed | 0x003F0C00u, - RETAA = UnconditionalBranchToRegisterFixed | 0x005F0800u, - RETAB = UnconditionalBranchToRegisterFixed | 0x005F0C00u, - BRAA = UnconditionalBranchToRegisterFixed | 0x011F0800u, - BRAB = UnconditionalBranchToRegisterFixed | 0x011F0C00u, - BLRAA = UnconditionalBranchToRegisterFixed | 0x013F0800u, - BLRAB = UnconditionalBranchToRegisterFixed | 0x013F0C00u + BRAAZ = UnconditionalBranchToRegisterFixed | 0x001F0800, + BRABZ = UnconditionalBranchToRegisterFixed | 0x001F0C00, + BLRAAZ = UnconditionalBranchToRegisterFixed | 0x003F0800, + BLRABZ = UnconditionalBranchToRegisterFixed | 0x003F0C00, + RETAA = UnconditionalBranchToRegisterFixed | 0x005F0800, + RETAB = UnconditionalBranchToRegisterFixed | 0x005F0C00, + BRAA = UnconditionalBranchToRegisterFixed | 0x011F0800, + BRAB = UnconditionalBranchToRegisterFixed | 0x011F0C00, + BLRAA = UnconditionalBranchToRegisterFixed | 0x013F0800, + BLRAB = UnconditionalBranchToRegisterFixed | 0x013F0C00 }; // Compare and branch. enum CompareBranchOp : uint32_t { - CompareBranchFixed = 0x34000000u, - CompareBranchFMask = 0x7E000000u, - CompareBranchMask = 0xFF000000u, - CBZ_w = CompareBranchFixed | 0x00000000u, - CBZ_x = CompareBranchFixed | 0x80000000u, + CompareBranchFixed = 0x34000000, + CompareBranchFMask = 0x7E000000, + CompareBranchMask = 0xFF000000, + CBZ_w = CompareBranchFixed | 0x00000000, + CBZ_x = CompareBranchFixed | 0x80000000, CBZ = CBZ_w, - CBNZ_w = CompareBranchFixed | 0x01000000u, - CBNZ_x = CompareBranchFixed | 0x81000000u, + CBNZ_w = CompareBranchFixed | 0x01000000, + CBNZ_x = CompareBranchFixed | 0x81000000, CBNZ = CBNZ_w }; // Test and branch. enum TestBranchOp : uint32_t { - TestBranchFixed = 0x36000000u, - TestBranchFMask = 0x7E000000u, - TestBranchMask = 0x7F000000u, - TBZ = TestBranchFixed | 0x00000000u, - TBNZ = TestBranchFixed | 0x01000000u + TestBranchFixed = 0x36000000, + TestBranchFMask = 0x7E000000, + TestBranchMask = 0x7F000000, + TBZ = TestBranchFixed | 0x00000000, + TBNZ = TestBranchFixed | 0x01000000 }; // Conditional branch. enum ConditionalBranchOp : uint32_t { - ConditionalBranchFixed = 0x54000000u, - ConditionalBranchFMask = 0xFE000000u, - ConditionalBranchMask = 0xFF000010u, - B_cond = ConditionalBranchFixed | 0x00000000u + ConditionalBranchFixed = 0x54000000, + ConditionalBranchFMask = 0xFE000000, + ConditionalBranchMask = 0xFF000010, + B_cond = ConditionalBranchFixed | 0x00000000 }; // System. @@ -915,122 +923,123 @@ enum ConditionalBranchOp : uint32_t { // instructions are split into more than one enum. enum SystemOp : uint32_t { - SystemFixed = 0xD5000000u, - SystemFMask = 0xFFC00000u + SystemFixed = 0xD5000000, + SystemFMask = 0xFFC00000 }; enum SystemSysRegOp : uint32_t { - SystemSysRegFixed = 0xD5100000u, - SystemSysRegFMask = 0xFFD00000u, - SystemSysRegMask = 0xFFF00000u, - MRS = SystemSysRegFixed | 0x00200000u, - MSR = SystemSysRegFixed | 0x00000000u + SystemSysRegFixed = 0xD5100000, + SystemSysRegFMask = 0xFFD00000, + SystemSysRegMask = 0xFFF00000, + MRS = SystemSysRegFixed | 0x00200000, + MSR = SystemSysRegFixed | 0x00000000 }; enum SystemPStateOp : uint32_t { - SystemPStateFixed = 0xD5004000u, - SystemPStateFMask = 0xFFF8F000u, - SystemPStateMask = 0xFFFFF0FFu, - CFINV = SystemPStateFixed | 0x0000001Fu, - XAFLAG = SystemPStateFixed | 0x0000003Fu, - AXFLAG = SystemPStateFixed | 0x0000005Fu + SystemPStateFixed = 0xD5004000, + SystemPStateFMask = 0xFFF8F000, + SystemPStateMask = 0xFFFFF0FF, + CFINV = SystemPStateFixed | 0x0000001F, + XAFLAG = SystemPStateFixed | 0x0000003F, + AXFLAG = SystemPStateFixed | 0x0000005F }; enum SystemHintOp : uint32_t { - SystemHintFixed = 0xD503201Fu, - SystemHintFMask = 0xFFFFF01Fu, - SystemHintMask = 0xFFFFF01Fu, - HINT = SystemHintFixed | 0x00000000u + SystemHintFixed = 0xD503201F, + SystemHintFMask = 0xFFFFF01F, + SystemHintMask = 0xFFFFF01F, + HINT = SystemHintFixed | 0x00000000 }; enum SystemSysOp : uint32_t { - SystemSysFixed = 0xD5080000u, - SystemSysFMask = 0xFFF80000u, - SystemSysMask = 0xFFF80000u, - SYS = SystemSysFixed | 0x00000000u + SystemSysFixed = 0xD5080000, + SystemSysFMask = 0xFFF80000, + SystemSysMask = 0xFFF80000, + SYS = SystemSysFixed | 0x00000000, + SYSL = SystemSysFixed | 0x00200000 }; // Exception. enum ExceptionOp : uint32_t { - ExceptionFixed = 0xD4000000u, - ExceptionFMask = 0xFF000000u, - ExceptionMask = 0xFFE0001Fu, - HLT = ExceptionFixed | 0x00400000u, - BRK = ExceptionFixed | 0x00200000u, - SVC = ExceptionFixed | 0x00000001u, - HVC = ExceptionFixed | 0x00000002u, - SMC = ExceptionFixed | 0x00000003u, - DCPS1 = ExceptionFixed | 0x00A00001u, - DCPS2 = ExceptionFixed | 0x00A00002u, - DCPS3 = ExceptionFixed | 0x00A00003u + ExceptionFixed = 0xD4000000, + ExceptionFMask = 0xFF000000, + ExceptionMask = 0xFFE0001F, + HLT = ExceptionFixed | 0x00400000, + BRK = ExceptionFixed | 0x00200000, + SVC = ExceptionFixed | 0x00000001, + HVC = ExceptionFixed | 0x00000002, + SMC = ExceptionFixed | 0x00000003, + DCPS1 = ExceptionFixed | 0x00A00001, + DCPS2 = ExceptionFixed | 0x00A00002, + DCPS3 = ExceptionFixed | 0x00A00003 }; enum MemBarrierOp : uint32_t { - MemBarrierFixed = 0xD503309Fu, - MemBarrierFMask = 0xFFFFF09Fu, - MemBarrierMask = 0xFFFFF0FFu, - DSB = MemBarrierFixed | 0x00000000u, - DMB = MemBarrierFixed | 0x00000020u, - ISB = MemBarrierFixed | 0x00000040u + MemBarrierFixed = 0xD503309F, + MemBarrierFMask = 0xFFFFF09F, + MemBarrierMask = 0xFFFFF0FF, + DSB = MemBarrierFixed | 0x00000000, + DMB = MemBarrierFixed | 0x00000020, + ISB = MemBarrierFixed | 0x00000040 }; enum SystemExclusiveMonitorOp : uint32_t { - SystemExclusiveMonitorFixed = 0xD503305Fu, - SystemExclusiveMonitorFMask = 0xFFFFF0FFu, - SystemExclusiveMonitorMask = 0xFFFFF0FFu, + SystemExclusiveMonitorFixed = 0xD503305F, + SystemExclusiveMonitorFMask = 0xFFFFF0FF, + SystemExclusiveMonitorMask = 0xFFFFF0FF, CLREX = SystemExclusiveMonitorFixed }; enum SystemPAuthOp : uint32_t { - SystemPAuthFixed = 0xD503211Fu, - SystemPAuthFMask = 0xFFFFFD1Fu, - SystemPAuthMask = 0xFFFFFFFFu, - PACIA1716 = SystemPAuthFixed | 0x00000100u, - PACIB1716 = SystemPAuthFixed | 0x00000140u, - AUTIA1716 = SystemPAuthFixed | 0x00000180u, - AUTIB1716 = SystemPAuthFixed | 0x000001C0u, - PACIAZ = SystemPAuthFixed | 0x00000300u, - PACIASP = SystemPAuthFixed | 0x00000320u, - PACIBZ = SystemPAuthFixed | 0x00000340u, - PACIBSP = SystemPAuthFixed | 0x00000360u, - AUTIAZ = SystemPAuthFixed | 0x00000380u, - AUTIASP = SystemPAuthFixed | 0x000003A0u, - AUTIBZ = SystemPAuthFixed | 0x000003C0u, - AUTIBSP = SystemPAuthFixed | 0x000003E0u, + SystemPAuthFixed = 0xD503211F, + SystemPAuthFMask = 0xFFFFFD1F, + SystemPAuthMask = 0xFFFFFFFF, + PACIA1716 = SystemPAuthFixed | 0x00000100, + PACIB1716 = SystemPAuthFixed | 0x00000140, + AUTIA1716 = SystemPAuthFixed | 0x00000180, + AUTIB1716 = SystemPAuthFixed | 0x000001C0, + PACIAZ = SystemPAuthFixed | 0x00000300, + PACIASP = SystemPAuthFixed | 0x00000320, + PACIBZ = SystemPAuthFixed | 0x00000340, + PACIBSP = SystemPAuthFixed | 0x00000360, + AUTIAZ = SystemPAuthFixed | 0x00000380, + AUTIASP = SystemPAuthFixed | 0x000003A0, + AUTIBZ = SystemPAuthFixed | 0x000003C0, + AUTIBSP = SystemPAuthFixed | 0x000003E0, // XPACLRI has the same fixed mask as System Hints and needs to be handled // differently. - XPACLRI = 0xD50320FFu + XPACLRI = 0xD50320FF }; // Any load or store. enum LoadStoreAnyOp : uint32_t { - LoadStoreAnyFMask = 0x0a000000u, - LoadStoreAnyFixed = 0x08000000u + LoadStoreAnyFMask = 0x0a000000, + LoadStoreAnyFixed = 0x08000000 }; // Any load pair or store pair. enum LoadStorePairAnyOp : uint32_t { - LoadStorePairAnyFMask = 0x3a000000u, - LoadStorePairAnyFixed = 0x28000000u + LoadStorePairAnyFMask = 0x3a000000, + LoadStorePairAnyFixed = 0x28000000 }; #define LOAD_STORE_PAIR_OP_LIST(V) \ - V(STP, w, 0x00000000u), \ - V(LDP, w, 0x00400000u), \ - V(LDPSW, x, 0x40400000u), \ - V(STP, x, 0x80000000u), \ - V(LDP, x, 0x80400000u), \ - V(STP, s, 0x04000000u), \ - V(LDP, s, 0x04400000u), \ - V(STP, d, 0x44000000u), \ - V(LDP, d, 0x44400000u), \ - V(STP, q, 0x84000000u), \ - V(LDP, q, 0x84400000u) + V(STP, w, 0x00000000), \ + V(LDP, w, 0x00400000), \ + V(LDPSW, x, 0x40400000), \ + V(STP, x, 0x80000000), \ + V(LDP, x, 0x80400000), \ + V(STP, s, 0x04000000), \ + V(LDP, s, 0x04400000), \ + V(STP, d, 0x44000000), \ + V(LDP, d, 0x44400000), \ + V(STP, q, 0x84000000), \ + V(LDP, q, 0x84400000) // Load/store pair (post, pre and offset.) enum LoadStorePairOp : uint32_t { - LoadStorePairMask = 0xC4400000u, + LoadStorePairMask = 0xC4400000, LoadStorePairLBit = 1 << 22, #define LOAD_STORE_PAIR(A, B, C) \ A##_##B = C @@ -1039,9 +1048,9 @@ enum LoadStorePairOp : uint32_t { }; enum LoadStorePairPostIndexOp : uint32_t { - LoadStorePairPostIndexFixed = 0x28800000u, - LoadStorePairPostIndexFMask = 0x3B800000u, - LoadStorePairPostIndexMask = 0xFFC00000u, + LoadStorePairPostIndexFixed = 0x28800000, + LoadStorePairPostIndexFMask = 0x3B800000, + LoadStorePairPostIndexMask = 0xFFC00000, #define LOAD_STORE_PAIR_POST_INDEX(A, B, C) \ A##_##B##_post = LoadStorePairPostIndexFixed | A##_##B LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_POST_INDEX) @@ -1049,9 +1058,9 @@ enum LoadStorePairPostIndexOp : uint32_t { }; enum LoadStorePairPreIndexOp : uint32_t { - LoadStorePairPreIndexFixed = 0x29800000u, - LoadStorePairPreIndexFMask = 0x3B800000u, - LoadStorePairPreIndexMask = 0xFFC00000u, + LoadStorePairPreIndexFixed = 0x29800000, + LoadStorePairPreIndexFMask = 0x3B800000, + LoadStorePairPreIndexMask = 0xFFC00000, #define LOAD_STORE_PAIR_PRE_INDEX(A, B, C) \ A##_##B##_pre = LoadStorePairPreIndexFixed | A##_##B LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_PRE_INDEX) @@ -1059,9 +1068,9 @@ enum LoadStorePairPreIndexOp : uint32_t { }; enum LoadStorePairOffsetOp : uint32_t { - LoadStorePairOffsetFixed = 0x29000000u, - LoadStorePairOffsetFMask = 0x3B800000u, - LoadStorePairOffsetMask = 0xFFC00000u, + LoadStorePairOffsetFixed = 0x29000000, + LoadStorePairOffsetFMask = 0x3B800000, + LoadStorePairOffsetMask = 0xFFC00000, #define LOAD_STORE_PAIR_OFFSET(A, B, C) \ A##_##B##_off = LoadStorePairOffsetFixed | A##_##B LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_OFFSET) @@ -1069,9 +1078,9 @@ enum LoadStorePairOffsetOp : uint32_t { }; enum LoadStorePairNonTemporalOp : uint32_t { - LoadStorePairNonTemporalFixed = 0x28000000u, - LoadStorePairNonTemporalFMask = 0x3B800000u, - LoadStorePairNonTemporalMask = 0xFFC00000u, + LoadStorePairNonTemporalFixed = 0x28000000, + LoadStorePairNonTemporalFMask = 0x3B800000, + LoadStorePairNonTemporalMask = 0xFFC00000, LoadStorePairNonTemporalLBit = 1 << 22, STNP_w = LoadStorePairNonTemporalFixed | STP_w, LDNP_w = LoadStorePairNonTemporalFixed | LDP_w, @@ -1086,72 +1095,72 @@ enum LoadStorePairNonTemporalOp : uint32_t { }; // Load with pointer authentication. -enum LoadStorePACOp { - LoadStorePACFixed = 0xF8200400u, - LoadStorePACFMask = 0xFF200400u, - LoadStorePACMask = 0xFFA00C00u, - LoadStorePACPreBit = 0x00000800u, - LDRAA = LoadStorePACFixed | 0x00000000u, +enum LoadStorePACOp : uint32_t { + LoadStorePACFixed = 0xF8200400, + LoadStorePACFMask = 0xFF200400, + LoadStorePACMask = 0xFFA00C00, + LoadStorePACPreBit = 0x00000800, + LDRAA = LoadStorePACFixed | 0x00000000, LDRAA_pre = LoadStorePACPreBit | LDRAA, - LDRAB = LoadStorePACFixed | 0x00800000u, + LDRAB = LoadStorePACFixed | 0x00800000, LDRAB_pre = LoadStorePACPreBit | LDRAB }; // Load literal. enum LoadLiteralOp : uint32_t { - LoadLiteralFixed = 0x18000000u, - LoadLiteralFMask = 0x3B000000u, - LoadLiteralMask = 0xFF000000u, - LDR_w_lit = LoadLiteralFixed | 0x00000000u, - LDR_x_lit = LoadLiteralFixed | 0x40000000u, - LDRSW_x_lit = LoadLiteralFixed | 0x80000000u, - PRFM_lit = LoadLiteralFixed | 0xC0000000u, - LDR_s_lit = LoadLiteralFixed | 0x04000000u, - LDR_d_lit = LoadLiteralFixed | 0x44000000u, - LDR_q_lit = LoadLiteralFixed | 0x84000000u + LoadLiteralFixed = 0x18000000, + LoadLiteralFMask = 0x3B000000, + LoadLiteralMask = 0xFF000000, + LDR_w_lit = LoadLiteralFixed | 0x00000000, + LDR_x_lit = LoadLiteralFixed | 0x40000000, + LDRSW_x_lit = LoadLiteralFixed | 0x80000000, + PRFM_lit = LoadLiteralFixed | 0xC0000000, + LDR_s_lit = LoadLiteralFixed | 0x04000000, + LDR_d_lit = LoadLiteralFixed | 0x44000000, + LDR_q_lit = LoadLiteralFixed | 0x84000000 }; #define LOAD_STORE_OP_LIST(V) \ - V(ST, RB, w, 0x00000000u), \ - V(ST, RH, w, 0x40000000u), \ - V(ST, R, w, 0x80000000u), \ - V(ST, R, x, 0xC0000000u), \ - V(LD, RB, w, 0x00400000u), \ - V(LD, RH, w, 0x40400000u), \ - V(LD, R, w, 0x80400000u), \ - V(LD, R, x, 0xC0400000u), \ - V(LD, RSB, x, 0x00800000u), \ - V(LD, RSH, x, 0x40800000u), \ - V(LD, RSW, x, 0x80800000u), \ - V(LD, RSB, w, 0x00C00000u), \ - V(LD, RSH, w, 0x40C00000u), \ - V(ST, R, b, 0x04000000u), \ - V(ST, R, h, 0x44000000u), \ - V(ST, R, s, 0x84000000u), \ - V(ST, R, d, 0xC4000000u), \ - V(ST, R, q, 0x04800000u), \ - V(LD, R, b, 0x04400000u), \ - V(LD, R, h, 0x44400000u), \ - V(LD, R, s, 0x84400000u), \ - V(LD, R, d, 0xC4400000u), \ - V(LD, R, q, 0x04C00000u) + V(ST, RB, w, 0x00000000), \ + V(ST, RH, w, 0x40000000), \ + V(ST, R, w, 0x80000000), \ + V(ST, R, x, 0xC0000000), \ + V(LD, RB, w, 0x00400000), \ + V(LD, RH, w, 0x40400000), \ + V(LD, R, w, 0x80400000), \ + V(LD, R, x, 0xC0400000), \ + V(LD, RSB, x, 0x00800000), \ + V(LD, RSH, x, 0x40800000), \ + V(LD, RSW, x, 0x80800000), \ + V(LD, RSB, w, 0x00C00000), \ + V(LD, RSH, w, 0x40C00000), \ + V(ST, R, b, 0x04000000), \ + V(ST, R, h, 0x44000000), \ + V(ST, R, s, 0x84000000), \ + V(ST, R, d, 0xC4000000), \ + V(ST, R, q, 0x04800000), \ + V(LD, R, b, 0x04400000), \ + V(LD, R, h, 0x44400000), \ + V(LD, R, s, 0x84400000), \ + V(LD, R, d, 0xC4400000), \ + V(LD, R, q, 0x04C00000) // Load/store (post, pre, offset and unsigned.) enum LoadStoreOp : uint32_t { - LoadStoreMask = 0xC4C00000u, - LoadStoreVMask = 0x04000000u, + LoadStoreMask = 0xC4C00000, + LoadStoreVMask = 0x04000000, #define LOAD_STORE(A, B, C, D) \ A##B##_##C = D LOAD_STORE_OP_LIST(LOAD_STORE), #undef LOAD_STORE - PRFM = 0xC0800000u + PRFM = 0xC0800000 }; // Load/store unscaled offset. enum LoadStoreUnscaledOffsetOp : uint32_t { - LoadStoreUnscaledOffsetFixed = 0x38000000u, - LoadStoreUnscaledOffsetFMask = 0x3B200C00u, - LoadStoreUnscaledOffsetMask = 0xFFE00C00u, + LoadStoreUnscaledOffsetFixed = 0x38000000, + LoadStoreUnscaledOffsetFMask = 0x3B200C00, + LoadStoreUnscaledOffsetMask = 0xFFE00C00, PRFUM = LoadStoreUnscaledOffsetFixed | PRFM, #define LOAD_STORE_UNSCALED(A, B, C, D) \ A##U##B##_##C = LoadStoreUnscaledOffsetFixed | D @@ -1161,9 +1170,9 @@ enum LoadStoreUnscaledOffsetOp : uint32_t { // Load/store post index. enum LoadStorePostIndex : uint32_t { - LoadStorePostIndexFixed = 0x38000400u, - LoadStorePostIndexFMask = 0x3B200C00u, - LoadStorePostIndexMask = 0xFFE00C00u, + LoadStorePostIndexFixed = 0x38000400, + LoadStorePostIndexFMask = 0x3B200C00, + LoadStorePostIndexMask = 0xFFE00C00, #define LOAD_STORE_POST_INDEX(A, B, C, D) \ A##B##_##C##_post = LoadStorePostIndexFixed | D LOAD_STORE_OP_LIST(LOAD_STORE_POST_INDEX) @@ -1172,9 +1181,9 @@ enum LoadStorePostIndex : uint32_t { // Load/store pre index. enum LoadStorePreIndex : uint32_t { - LoadStorePreIndexFixed = 0x38000C00u, - LoadStorePreIndexFMask = 0x3B200C00u, - LoadStorePreIndexMask = 0xFFE00C00u, + LoadStorePreIndexFixed = 0x38000C00, + LoadStorePreIndexFMask = 0x3B200C00, + LoadStorePreIndexMask = 0xFFE00C00, #define LOAD_STORE_PRE_INDEX(A, B, C, D) \ A##B##_##C##_pre = LoadStorePreIndexFixed | D LOAD_STORE_OP_LIST(LOAD_STORE_PRE_INDEX) @@ -1183,9 +1192,9 @@ enum LoadStorePreIndex : uint32_t { // Load/store unsigned offset. enum LoadStoreUnsignedOffset : uint32_t { - LoadStoreUnsignedOffsetFixed = 0x39000000u, - LoadStoreUnsignedOffsetFMask = 0x3B000000u, - LoadStoreUnsignedOffsetMask = 0xFFC00000u, + LoadStoreUnsignedOffsetFixed = 0x39000000, + LoadStoreUnsignedOffsetFMask = 0x3B000000, + LoadStoreUnsignedOffsetMask = 0xFFC00000, PRFM_unsigned = LoadStoreUnsignedOffsetFixed | PRFM, #define LOAD_STORE_UNSIGNED_OFFSET(A, B, C, D) \ A##B##_##C##_unsigned = LoadStoreUnsignedOffsetFixed | D @@ -1195,9 +1204,9 @@ enum LoadStoreUnsignedOffset : uint32_t { // Load/store register offset. enum LoadStoreRegisterOffset : uint32_t { - LoadStoreRegisterOffsetFixed = 0x38200800u, - LoadStoreRegisterOffsetFMask = 0x3B200C00u, - LoadStoreRegisterOffsetMask = 0xFFE00C00u, + LoadStoreRegisterOffsetFixed = 0x38200800, + LoadStoreRegisterOffsetFMask = 0x3B200C00, + LoadStoreRegisterOffsetMask = 0xFFE00C00, PRFM_reg = LoadStoreRegisterOffsetFixed | PRFM, #define LOAD_STORE_REGISTER_OFFSET(A, B, C, D) \ A##B##_##C##_reg = LoadStoreRegisterOffsetFixed | D @@ -1206,60 +1215,60 @@ enum LoadStoreRegisterOffset : uint32_t { }; enum LoadStoreExclusive : uint32_t { - LoadStoreExclusiveFixed = 0x08000000u, - LoadStoreExclusiveFMask = 0x3F000000u, - LoadStoreExclusiveMask = 0xFFE08000u, - STXRB_w = LoadStoreExclusiveFixed | 0x00000000u, - STXRH_w = LoadStoreExclusiveFixed | 0x40000000u, - STXR_w = LoadStoreExclusiveFixed | 0x80000000u, - STXR_x = LoadStoreExclusiveFixed | 0xC0000000u, - LDXRB_w = LoadStoreExclusiveFixed | 0x00400000u, - LDXRH_w = LoadStoreExclusiveFixed | 0x40400000u, - LDXR_w = LoadStoreExclusiveFixed | 0x80400000u, - LDXR_x = LoadStoreExclusiveFixed | 0xC0400000u, - STXP_w = LoadStoreExclusiveFixed | 0x80200000u, - STXP_x = LoadStoreExclusiveFixed | 0xC0200000u, - LDXP_w = LoadStoreExclusiveFixed | 0x80600000u, - LDXP_x = LoadStoreExclusiveFixed | 0xC0600000u, - STLXRB_w = LoadStoreExclusiveFixed | 0x00008000u, - STLXRH_w = LoadStoreExclusiveFixed | 0x40008000u, - STLXR_w = LoadStoreExclusiveFixed | 0x80008000u, - STLXR_x = LoadStoreExclusiveFixed | 0xC0008000u, - LDAXRB_w = LoadStoreExclusiveFixed | 0x00408000u, - LDAXRH_w = LoadStoreExclusiveFixed | 0x40408000u, - LDAXR_w = LoadStoreExclusiveFixed | 0x80408000u, - LDAXR_x = LoadStoreExclusiveFixed | 0xC0408000u, - STLXP_w = LoadStoreExclusiveFixed | 0x80208000u, - STLXP_x = LoadStoreExclusiveFixed | 0xC0208000u, - LDAXP_w = LoadStoreExclusiveFixed | 0x80608000u, - LDAXP_x = LoadStoreExclusiveFixed | 0xC0608000u, - STLRB_w = LoadStoreExclusiveFixed | 0x00808000u, - STLRH_w = LoadStoreExclusiveFixed | 0x40808000u, - STLR_w = LoadStoreExclusiveFixed | 0x80808000u, - STLR_x = LoadStoreExclusiveFixed | 0xC0808000u, - LDARB_w = LoadStoreExclusiveFixed | 0x00C08000u, - LDARH_w = LoadStoreExclusiveFixed | 0x40C08000u, - LDAR_w = LoadStoreExclusiveFixed | 0x80C08000u, - LDAR_x = LoadStoreExclusiveFixed | 0xC0C08000u, + LoadStoreExclusiveFixed = 0x08000000, + LoadStoreExclusiveFMask = 0x3F000000, + LoadStoreExclusiveMask = 0xFFE08000, + STXRB_w = LoadStoreExclusiveFixed | 0x00000000, + STXRH_w = LoadStoreExclusiveFixed | 0x40000000, + STXR_w = LoadStoreExclusiveFixed | 0x80000000, + STXR_x = LoadStoreExclusiveFixed | 0xC0000000, + LDXRB_w = LoadStoreExclusiveFixed | 0x00400000, + LDXRH_w = LoadStoreExclusiveFixed | 0x40400000, + LDXR_w = LoadStoreExclusiveFixed | 0x80400000, + LDXR_x = LoadStoreExclusiveFixed | 0xC0400000, + STXP_w = LoadStoreExclusiveFixed | 0x80200000, + STXP_x = LoadStoreExclusiveFixed | 0xC0200000, + LDXP_w = LoadStoreExclusiveFixed | 0x80600000, + LDXP_x = LoadStoreExclusiveFixed | 0xC0600000, + STLXRB_w = LoadStoreExclusiveFixed | 0x00008000, + STLXRH_w = LoadStoreExclusiveFixed | 0x40008000, + STLXR_w = LoadStoreExclusiveFixed | 0x80008000, + STLXR_x = LoadStoreExclusiveFixed | 0xC0008000, + LDAXRB_w = LoadStoreExclusiveFixed | 0x00408000, + LDAXRH_w = LoadStoreExclusiveFixed | 0x40408000, + LDAXR_w = LoadStoreExclusiveFixed | 0x80408000, + LDAXR_x = LoadStoreExclusiveFixed | 0xC0408000, + STLXP_w = LoadStoreExclusiveFixed | 0x80208000, + STLXP_x = LoadStoreExclusiveFixed | 0xC0208000, + LDAXP_w = LoadStoreExclusiveFixed | 0x80608000, + LDAXP_x = LoadStoreExclusiveFixed | 0xC0608000, + STLRB_w = LoadStoreExclusiveFixed | 0x00808000, + STLRH_w = LoadStoreExclusiveFixed | 0x40808000, + STLR_w = LoadStoreExclusiveFixed | 0x80808000, + STLR_x = LoadStoreExclusiveFixed | 0xC0808000, + LDARB_w = LoadStoreExclusiveFixed | 0x00C08000, + LDARH_w = LoadStoreExclusiveFixed | 0x40C08000, + LDAR_w = LoadStoreExclusiveFixed | 0x80C08000, + LDAR_x = LoadStoreExclusiveFixed | 0xC0C08000, // v8.1 Load/store LORegion ops - STLLRB = LoadStoreExclusiveFixed | 0x00800000u, - LDLARB = LoadStoreExclusiveFixed | 0x00C00000u, - STLLRH = LoadStoreExclusiveFixed | 0x40800000u, - LDLARH = LoadStoreExclusiveFixed | 0x40C00000u, - STLLR_w = LoadStoreExclusiveFixed | 0x80800000u, - LDLAR_w = LoadStoreExclusiveFixed | 0x80C00000u, - STLLR_x = LoadStoreExclusiveFixed | 0xC0800000u, - LDLAR_x = LoadStoreExclusiveFixed | 0xC0C00000u, + STLLRB = LoadStoreExclusiveFixed | 0x00800000, + LDLARB = LoadStoreExclusiveFixed | 0x00C00000, + STLLRH = LoadStoreExclusiveFixed | 0x40800000, + LDLARH = LoadStoreExclusiveFixed | 0x40C00000, + STLLR_w = LoadStoreExclusiveFixed | 0x80800000, + LDLAR_w = LoadStoreExclusiveFixed | 0x80C00000, + STLLR_x = LoadStoreExclusiveFixed | 0xC0800000, + LDLAR_x = LoadStoreExclusiveFixed | 0xC0C00000, // v8.1 Load/store exclusive ops - LSEBit_l = 0x00400000u, - LSEBit_o0 = 0x00008000u, - LSEBit_sz = 0x40000000u, - CASFixed = LoadStoreExclusiveFixed | 0x80A00000u, - CASBFixed = LoadStoreExclusiveFixed | 0x00A00000u, - CASHFixed = LoadStoreExclusiveFixed | 0x40A00000u, - CASPFixed = LoadStoreExclusiveFixed | 0x00200000u, + LSEBit_l = 0x00400000, + LSEBit_o0 = 0x00008000, + LSEBit_sz = 0x40000000, + CASFixed = LoadStoreExclusiveFixed | 0x80A00000, + CASBFixed = LoadStoreExclusiveFixed | 0x00A00000, + CASHFixed = LoadStoreExclusiveFixed | 0x40A00000, + CASPFixed = LoadStoreExclusiveFixed | 0x00200000, CAS_w = CASFixed, CAS_x = CASFixed | LSEBit_sz, CASA_w = CASFixed | LSEBit_l, @@ -1288,80 +1297,80 @@ enum LoadStoreExclusive : uint32_t { // Load/store RCpc unscaled offset. enum LoadStoreRCpcUnscaledOffsetOp : uint32_t { - LoadStoreRCpcUnscaledOffsetFixed = 0x19000000u, - LoadStoreRCpcUnscaledOffsetFMask = 0x3F200C00u, - LoadStoreRCpcUnscaledOffsetMask = 0xFFE00C00u, - STLURB = LoadStoreRCpcUnscaledOffsetFixed | 0x00000000u, - LDAPURB = LoadStoreRCpcUnscaledOffsetFixed | 0x00400000u, - LDAPURSB_x = LoadStoreRCpcUnscaledOffsetFixed | 0x00800000u, - LDAPURSB_w = LoadStoreRCpcUnscaledOffsetFixed | 0x00C00000u, - STLURH = LoadStoreRCpcUnscaledOffsetFixed | 0x40000000u, - LDAPURH = LoadStoreRCpcUnscaledOffsetFixed | 0x40400000u, - LDAPURSH_x = LoadStoreRCpcUnscaledOffsetFixed | 0x40800000u, - LDAPURSH_w = LoadStoreRCpcUnscaledOffsetFixed | 0x40C00000u, - STLUR_w = LoadStoreRCpcUnscaledOffsetFixed | 0x80000000u, - LDAPUR_w = LoadStoreRCpcUnscaledOffsetFixed | 0x80400000u, - LDAPURSW = LoadStoreRCpcUnscaledOffsetFixed | 0x80800000u, - STLUR_x = LoadStoreRCpcUnscaledOffsetFixed | 0xC0000000u, - LDAPUR_x = LoadStoreRCpcUnscaledOffsetFixed | 0xC0400000u + LoadStoreRCpcUnscaledOffsetFixed = 0x19000000, + LoadStoreRCpcUnscaledOffsetFMask = 0x3F200C00, + LoadStoreRCpcUnscaledOffsetMask = 0xFFE00C00, + STLURB = LoadStoreRCpcUnscaledOffsetFixed | 0x00000000, + LDAPURB = LoadStoreRCpcUnscaledOffsetFixed | 0x00400000, + LDAPURSB_x = LoadStoreRCpcUnscaledOffsetFixed | 0x00800000, + LDAPURSB_w = LoadStoreRCpcUnscaledOffsetFixed | 0x00C00000, + STLURH = LoadStoreRCpcUnscaledOffsetFixed | 0x40000000, + LDAPURH = LoadStoreRCpcUnscaledOffsetFixed | 0x40400000, + LDAPURSH_x = LoadStoreRCpcUnscaledOffsetFixed | 0x40800000, + LDAPURSH_w = LoadStoreRCpcUnscaledOffsetFixed | 0x40C00000, + STLUR_w = LoadStoreRCpcUnscaledOffsetFixed | 0x80000000, + LDAPUR_w = LoadStoreRCpcUnscaledOffsetFixed | 0x80400000, + LDAPURSW = LoadStoreRCpcUnscaledOffsetFixed | 0x80800000, + STLUR_x = LoadStoreRCpcUnscaledOffsetFixed | 0xC0000000, + LDAPUR_x = LoadStoreRCpcUnscaledOffsetFixed | 0xC0400000 }; #define ATOMIC_MEMORY_SIMPLE_OPC_LIST(V) \ - V(LDADD, 0x00000000u), \ - V(LDCLR, 0x00001000u), \ - V(LDEOR, 0x00002000u), \ - V(LDSET, 0x00003000u), \ - V(LDSMAX, 0x00004000u), \ - V(LDSMIN, 0x00005000u), \ - V(LDUMAX, 0x00006000u), \ - V(LDUMIN, 0x00007000u) + V(LDADD, 0x00000000), \ + V(LDCLR, 0x00001000), \ + V(LDEOR, 0x00002000), \ + V(LDSET, 0x00003000), \ + V(LDSMAX, 0x00004000), \ + V(LDSMIN, 0x00005000), \ + V(LDUMAX, 0x00006000), \ + V(LDUMIN, 0x00007000) // Atomic memory. enum AtomicMemoryOp : uint32_t { - AtomicMemoryFixed = 0x38200000u, - AtomicMemoryFMask = 0x3B200C00u, - AtomicMemoryMask = 0xFFE0FC00u, - SWPB = AtomicMemoryFixed | 0x00008000u, - SWPAB = AtomicMemoryFixed | 0x00808000u, - SWPLB = AtomicMemoryFixed | 0x00408000u, - SWPALB = AtomicMemoryFixed | 0x00C08000u, - SWPH = AtomicMemoryFixed | 0x40008000u, - SWPAH = AtomicMemoryFixed | 0x40808000u, - SWPLH = AtomicMemoryFixed | 0x40408000u, - SWPALH = AtomicMemoryFixed | 0x40C08000u, - SWP_w = AtomicMemoryFixed | 0x80008000u, - SWPA_w = AtomicMemoryFixed | 0x80808000u, - SWPL_w = AtomicMemoryFixed | 0x80408000u, - SWPAL_w = AtomicMemoryFixed | 0x80C08000u, - SWP_x = AtomicMemoryFixed | 0xC0008000u, - SWPA_x = AtomicMemoryFixed | 0xC0808000u, - SWPL_x = AtomicMemoryFixed | 0xC0408000u, - SWPAL_x = AtomicMemoryFixed | 0xC0C08000u, - LDAPRB = AtomicMemoryFixed | 0x0080C000u, - LDAPRH = AtomicMemoryFixed | 0x4080C000u, - LDAPR_w = AtomicMemoryFixed | 0x8080C000u, - LDAPR_x = AtomicMemoryFixed | 0xC080C000u, + AtomicMemoryFixed = 0x38200000, + AtomicMemoryFMask = 0x3B200C00, + AtomicMemoryMask = 0xFFE0FC00, + SWPB = AtomicMemoryFixed | 0x00008000, + SWPAB = AtomicMemoryFixed | 0x00808000, + SWPLB = AtomicMemoryFixed | 0x00408000, + SWPALB = AtomicMemoryFixed | 0x00C08000, + SWPH = AtomicMemoryFixed | 0x40008000, + SWPAH = AtomicMemoryFixed | 0x40808000, + SWPLH = AtomicMemoryFixed | 0x40408000, + SWPALH = AtomicMemoryFixed | 0x40C08000, + SWP_w = AtomicMemoryFixed | 0x80008000, + SWPA_w = AtomicMemoryFixed | 0x80808000, + SWPL_w = AtomicMemoryFixed | 0x80408000, + SWPAL_w = AtomicMemoryFixed | 0x80C08000, + SWP_x = AtomicMemoryFixed | 0xC0008000, + SWPA_x = AtomicMemoryFixed | 0xC0808000, + SWPL_x = AtomicMemoryFixed | 0xC0408000, + SWPAL_x = AtomicMemoryFixed | 0xC0C08000, + LDAPRB = AtomicMemoryFixed | 0x0080C000, + LDAPRH = AtomicMemoryFixed | 0x4080C000, + LDAPR_w = AtomicMemoryFixed | 0x8080C000, + LDAPR_x = AtomicMemoryFixed | 0xC080C000, - AtomicMemorySimpleFMask = 0x3B208C00u, - AtomicMemorySimpleOpMask = 0x00007000u, + AtomicMemorySimpleFMask = 0x3B208C00, + AtomicMemorySimpleOpMask = 0x00007000, #define ATOMIC_MEMORY_SIMPLE(N, OP) \ N##Op = OP, \ N##B = AtomicMemoryFixed | OP, \ - N##AB = AtomicMemoryFixed | OP | 0x00800000u, \ - N##LB = AtomicMemoryFixed | OP | 0x00400000u, \ - N##ALB = AtomicMemoryFixed | OP | 0x00C00000u, \ - N##H = AtomicMemoryFixed | OP | 0x40000000u, \ - N##AH = AtomicMemoryFixed | OP | 0x40800000u, \ - N##LH = AtomicMemoryFixed | OP | 0x40400000u, \ - N##ALH = AtomicMemoryFixed | OP | 0x40C00000u, \ - N##_w = AtomicMemoryFixed | OP | 0x80000000u, \ - N##A_w = AtomicMemoryFixed | OP | 0x80800000u, \ - N##L_w = AtomicMemoryFixed | OP | 0x80400000u, \ - N##AL_w = AtomicMemoryFixed | OP | 0x80C00000u, \ - N##_x = AtomicMemoryFixed | OP | 0xC0000000u, \ - N##A_x = AtomicMemoryFixed | OP | 0xC0800000u, \ - N##L_x = AtomicMemoryFixed | OP | 0xC0400000u, \ - N##AL_x = AtomicMemoryFixed | OP | 0xC0C00000u + N##AB = AtomicMemoryFixed | OP | 0x00800000, \ + N##LB = AtomicMemoryFixed | OP | 0x00400000, \ + N##ALB = AtomicMemoryFixed | OP | 0x00C00000, \ + N##H = AtomicMemoryFixed | OP | 0x40000000, \ + N##AH = AtomicMemoryFixed | OP | 0x40800000, \ + N##LH = AtomicMemoryFixed | OP | 0x40400000, \ + N##ALH = AtomicMemoryFixed | OP | 0x40C00000, \ + N##_w = AtomicMemoryFixed | OP | 0x80000000, \ + N##A_w = AtomicMemoryFixed | OP | 0x80800000, \ + N##L_w = AtomicMemoryFixed | OP | 0x80400000, \ + N##AL_w = AtomicMemoryFixed | OP | 0x80C00000, \ + N##_x = AtomicMemoryFixed | OP | 0xC0000000, \ + N##A_x = AtomicMemoryFixed | OP | 0xC0800000, \ + N##L_x = AtomicMemoryFixed | OP | 0xC0400000, \ + N##AL_x = AtomicMemoryFixed | OP | 0xC0C00000 ATOMIC_MEMORY_SIMPLE_OPC_LIST(ATOMIC_MEMORY_SIMPLE) #undef ATOMIC_MEMORY_SIMPLE @@ -1369,16 +1378,16 @@ enum AtomicMemoryOp : uint32_t { // Conditional compare. enum ConditionalCompareOp : uint32_t { - ConditionalCompareMask = 0x60000000u, - CCMN = 0x20000000u, - CCMP = 0x60000000u + ConditionalCompareMask = 0x60000000, + CCMN = 0x20000000, + CCMP = 0x60000000 }; // Conditional compare register. enum ConditionalCompareRegisterOp : uint32_t { - ConditionalCompareRegisterFixed = 0x1A400000u, - ConditionalCompareRegisterFMask = 0x1FE00800u, - ConditionalCompareRegisterMask = 0xFFE00C10u, + ConditionalCompareRegisterFixed = 0x1A400000, + ConditionalCompareRegisterFMask = 0x1FE00800, + ConditionalCompareRegisterMask = 0xFFE00C10, CCMN_w = ConditionalCompareRegisterFixed | CCMN, CCMN_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMN, CCMP_w = ConditionalCompareRegisterFixed | CCMP, @@ -1387,9 +1396,9 @@ enum ConditionalCompareRegisterOp : uint32_t { // Conditional compare immediate. enum ConditionalCompareImmediateOp : uint32_t { - ConditionalCompareImmediateFixed = 0x1A400800u, - ConditionalCompareImmediateFMask = 0x1FE00800u, - ConditionalCompareImmediateMask = 0xFFE00C10u, + ConditionalCompareImmediateFixed = 0x1A400800, + ConditionalCompareImmediateFMask = 0x1FE00800, + ConditionalCompareImmediateMask = 0xFFE00C10, CCMN_w_imm = ConditionalCompareImmediateFixed | CCMN, CCMN_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMN, CCMP_w_imm = ConditionalCompareImmediateFixed | CCMP, @@ -1398,198 +1407,198 @@ enum ConditionalCompareImmediateOp : uint32_t { // Conditional select. enum ConditionalSelectOp : uint32_t { - ConditionalSelectFixed = 0x1A800000u, - ConditionalSelectFMask = 0x1FE00000u, - ConditionalSelectMask = 0xFFE00C00u, - CSEL_w = ConditionalSelectFixed | 0x00000000u, - CSEL_x = ConditionalSelectFixed | 0x80000000u, + ConditionalSelectFixed = 0x1A800000, + ConditionalSelectFMask = 0x1FE00000, + ConditionalSelectMask = 0xFFE00C00, + CSEL_w = ConditionalSelectFixed | 0x00000000, + CSEL_x = ConditionalSelectFixed | 0x80000000, CSEL = CSEL_w, - CSINC_w = ConditionalSelectFixed | 0x00000400u, - CSINC_x = ConditionalSelectFixed | 0x80000400u, + CSINC_w = ConditionalSelectFixed | 0x00000400, + CSINC_x = ConditionalSelectFixed | 0x80000400, CSINC = CSINC_w, - CSINV_w = ConditionalSelectFixed | 0x40000000u, - CSINV_x = ConditionalSelectFixed | 0xC0000000u, + CSINV_w = ConditionalSelectFixed | 0x40000000, + CSINV_x = ConditionalSelectFixed | 0xC0000000, CSINV = CSINV_w, - CSNEG_w = ConditionalSelectFixed | 0x40000400u, - CSNEG_x = ConditionalSelectFixed | 0xC0000400u, + CSNEG_w = ConditionalSelectFixed | 0x40000400, + CSNEG_x = ConditionalSelectFixed | 0xC0000400, CSNEG = CSNEG_w }; // Data processing 1 source. enum DataProcessing1SourceOp : uint32_t { - DataProcessing1SourceFixed = 0x5AC00000u, - DataProcessing1SourceFMask = 0x5FE00000u, - DataProcessing1SourceMask = 0xFFFFFC00u, - RBIT = DataProcessing1SourceFixed | 0x00000000u, + DataProcessing1SourceFixed = 0x5AC00000, + DataProcessing1SourceFMask = 0x5FE00000, + DataProcessing1SourceMask = 0xFFFFFC00, + RBIT = DataProcessing1SourceFixed | 0x00000000, RBIT_w = RBIT, RBIT_x = RBIT | SixtyFourBits, - REV16 = DataProcessing1SourceFixed | 0x00000400u, + REV16 = DataProcessing1SourceFixed | 0x00000400, REV16_w = REV16, REV16_x = REV16 | SixtyFourBits, - REV = DataProcessing1SourceFixed | 0x00000800u, + REV = DataProcessing1SourceFixed | 0x00000800, REV_w = REV, REV32_x = REV | SixtyFourBits, - REV_x = DataProcessing1SourceFixed | SixtyFourBits | 0x00000C00u, - CLZ = DataProcessing1SourceFixed | 0x00001000u, + REV_x = DataProcessing1SourceFixed | SixtyFourBits | 0x00000C00, + CLZ = DataProcessing1SourceFixed | 0x00001000, CLZ_w = CLZ, CLZ_x = CLZ | SixtyFourBits, - CLS = DataProcessing1SourceFixed | 0x00001400u, + CLS = DataProcessing1SourceFixed | 0x00001400, CLS_w = CLS, CLS_x = CLS | SixtyFourBits, // Pointer authentication instructions in Armv8.3. - PACIA = DataProcessing1SourceFixed | 0x80010000u, - PACIB = DataProcessing1SourceFixed | 0x80010400u, - PACDA = DataProcessing1SourceFixed | 0x80010800u, - PACDB = DataProcessing1SourceFixed | 0x80010C00u, - AUTIA = DataProcessing1SourceFixed | 0x80011000u, - AUTIB = DataProcessing1SourceFixed | 0x80011400u, - AUTDA = DataProcessing1SourceFixed | 0x80011800u, - AUTDB = DataProcessing1SourceFixed | 0x80011C00u, - PACIZA = DataProcessing1SourceFixed | 0x80012000u, - PACIZB = DataProcessing1SourceFixed | 0x80012400u, - PACDZA = DataProcessing1SourceFixed | 0x80012800u, - PACDZB = DataProcessing1SourceFixed | 0x80012C00u, - AUTIZA = DataProcessing1SourceFixed | 0x80013000u, - AUTIZB = DataProcessing1SourceFixed | 0x80013400u, - AUTDZA = DataProcessing1SourceFixed | 0x80013800u, - AUTDZB = DataProcessing1SourceFixed | 0x80013C00u, - XPACI = DataProcessing1SourceFixed | 0x80014000u, - XPACD = DataProcessing1SourceFixed | 0x80014400u + PACIA = DataProcessing1SourceFixed | 0x80010000, + PACIB = DataProcessing1SourceFixed | 0x80010400, + PACDA = DataProcessing1SourceFixed | 0x80010800, + PACDB = DataProcessing1SourceFixed | 0x80010C00, + AUTIA = DataProcessing1SourceFixed | 0x80011000, + AUTIB = DataProcessing1SourceFixed | 0x80011400, + AUTDA = DataProcessing1SourceFixed | 0x80011800, + AUTDB = DataProcessing1SourceFixed | 0x80011C00, + PACIZA = DataProcessing1SourceFixed | 0x80012000, + PACIZB = DataProcessing1SourceFixed | 0x80012400, + PACDZA = DataProcessing1SourceFixed | 0x80012800, + PACDZB = DataProcessing1SourceFixed | 0x80012C00, + AUTIZA = DataProcessing1SourceFixed | 0x80013000, + AUTIZB = DataProcessing1SourceFixed | 0x80013400, + AUTDZA = DataProcessing1SourceFixed | 0x80013800, + AUTDZB = DataProcessing1SourceFixed | 0x80013C00, + XPACI = DataProcessing1SourceFixed | 0x80014000, + XPACD = DataProcessing1SourceFixed | 0x80014400 }; // Data processing 2 source. enum DataProcessing2SourceOp : uint32_t { - DataProcessing2SourceFixed = 0x1AC00000u, - DataProcessing2SourceFMask = 0x5FE00000u, - DataProcessing2SourceMask = 0xFFE0FC00u, - UDIV_w = DataProcessing2SourceFixed | 0x00000800u, - UDIV_x = DataProcessing2SourceFixed | 0x80000800u, + DataProcessing2SourceFixed = 0x1AC00000, + DataProcessing2SourceFMask = 0x5FE00000, + DataProcessing2SourceMask = 0xFFE0FC00, + UDIV_w = DataProcessing2SourceFixed | 0x00000800, + UDIV_x = DataProcessing2SourceFixed | 0x80000800, UDIV = UDIV_w, - SDIV_w = DataProcessing2SourceFixed | 0x00000C00u, - SDIV_x = DataProcessing2SourceFixed | 0x80000C00u, + SDIV_w = DataProcessing2SourceFixed | 0x00000C00, + SDIV_x = DataProcessing2SourceFixed | 0x80000C00, SDIV = SDIV_w, - LSLV_w = DataProcessing2SourceFixed | 0x00002000u, - LSLV_x = DataProcessing2SourceFixed | 0x80002000u, + LSLV_w = DataProcessing2SourceFixed | 0x00002000, + LSLV_x = DataProcessing2SourceFixed | 0x80002000, LSLV = LSLV_w, - LSRV_w = DataProcessing2SourceFixed | 0x00002400u, - LSRV_x = DataProcessing2SourceFixed | 0x80002400u, + LSRV_w = DataProcessing2SourceFixed | 0x00002400, + LSRV_x = DataProcessing2SourceFixed | 0x80002400, LSRV = LSRV_w, - ASRV_w = DataProcessing2SourceFixed | 0x00002800u, - ASRV_x = DataProcessing2SourceFixed | 0x80002800u, + ASRV_w = DataProcessing2SourceFixed | 0x00002800, + ASRV_x = DataProcessing2SourceFixed | 0x80002800, ASRV = ASRV_w, - RORV_w = DataProcessing2SourceFixed | 0x00002C00u, - RORV_x = DataProcessing2SourceFixed | 0x80002C00u, + RORV_w = DataProcessing2SourceFixed | 0x00002C00, + RORV_x = DataProcessing2SourceFixed | 0x80002C00, RORV = RORV_w, - PACGA = DataProcessing2SourceFixed | SixtyFourBits | 0x00003000u, - CRC32B = DataProcessing2SourceFixed | 0x00004000u, - CRC32H = DataProcessing2SourceFixed | 0x00004400u, - CRC32W = DataProcessing2SourceFixed | 0x00004800u, - CRC32X = DataProcessing2SourceFixed | SixtyFourBits | 0x00004C00u, - CRC32CB = DataProcessing2SourceFixed | 0x00005000u, - CRC32CH = DataProcessing2SourceFixed | 0x00005400u, - CRC32CW = DataProcessing2SourceFixed | 0x00005800u, - CRC32CX = DataProcessing2SourceFixed | SixtyFourBits | 0x00005C00u + PACGA = DataProcessing2SourceFixed | SixtyFourBits | 0x00003000, + CRC32B = DataProcessing2SourceFixed | 0x00004000, + CRC32H = DataProcessing2SourceFixed | 0x00004400, + CRC32W = DataProcessing2SourceFixed | 0x00004800, + CRC32X = DataProcessing2SourceFixed | SixtyFourBits | 0x00004C00, + CRC32CB = DataProcessing2SourceFixed | 0x00005000, + CRC32CH = DataProcessing2SourceFixed | 0x00005400, + CRC32CW = DataProcessing2SourceFixed | 0x00005800, + CRC32CX = DataProcessing2SourceFixed | SixtyFourBits | 0x00005C00 }; // Data processing 3 source. enum DataProcessing3SourceOp : uint32_t { - DataProcessing3SourceFixed = 0x1B000000u, - DataProcessing3SourceFMask = 0x1F000000u, - DataProcessing3SourceMask = 0xFFE08000u, - MADD_w = DataProcessing3SourceFixed | 0x00000000u, - MADD_x = DataProcessing3SourceFixed | 0x80000000u, + DataProcessing3SourceFixed = 0x1B000000, + DataProcessing3SourceFMask = 0x1F000000, + DataProcessing3SourceMask = 0xFFE08000, + MADD_w = DataProcessing3SourceFixed | 0x00000000, + MADD_x = DataProcessing3SourceFixed | 0x80000000, MADD = MADD_w, - MSUB_w = DataProcessing3SourceFixed | 0x00008000u, - MSUB_x = DataProcessing3SourceFixed | 0x80008000u, + MSUB_w = DataProcessing3SourceFixed | 0x00008000, + MSUB_x = DataProcessing3SourceFixed | 0x80008000, MSUB = MSUB_w, - SMADDL_x = DataProcessing3SourceFixed | 0x80200000u, - SMSUBL_x = DataProcessing3SourceFixed | 0x80208000u, - SMULH_x = DataProcessing3SourceFixed | 0x80400000u, - UMADDL_x = DataProcessing3SourceFixed | 0x80A00000u, - UMSUBL_x = DataProcessing3SourceFixed | 0x80A08000u, - UMULH_x = DataProcessing3SourceFixed | 0x80C00000u + SMADDL_x = DataProcessing3SourceFixed | 0x80200000, + SMSUBL_x = DataProcessing3SourceFixed | 0x80208000, + SMULH_x = DataProcessing3SourceFixed | 0x80400000, + UMADDL_x = DataProcessing3SourceFixed | 0x80A00000, + UMSUBL_x = DataProcessing3SourceFixed | 0x80A08000, + UMULH_x = DataProcessing3SourceFixed | 0x80C00000 }; // Floating point compare. enum FPCompareOp : uint32_t { - FPCompareFixed = 0x1E202000u, - FPCompareFMask = 0x5F203C00u, - FPCompareMask = 0xFFE0FC1Fu, - FCMP_h = FPCompareFixed | FP16 | 0x00000000u, - FCMP_s = FPCompareFixed | 0x00000000u, - FCMP_d = FPCompareFixed | FP64 | 0x00000000u, + FPCompareFixed = 0x1E202000, + FPCompareFMask = 0x5F203C00, + FPCompareMask = 0xFFE0FC1F, + FCMP_h = FPCompareFixed | FP16 | 0x00000000, + FCMP_s = FPCompareFixed | 0x00000000, + FCMP_d = FPCompareFixed | FP64 | 0x00000000, FCMP = FCMP_s, - FCMP_h_zero = FPCompareFixed | FP16 | 0x00000008u, - FCMP_s_zero = FPCompareFixed | 0x00000008u, - FCMP_d_zero = FPCompareFixed | FP64 | 0x00000008u, + FCMP_h_zero = FPCompareFixed | FP16 | 0x00000008, + FCMP_s_zero = FPCompareFixed | 0x00000008, + FCMP_d_zero = FPCompareFixed | FP64 | 0x00000008, FCMP_zero = FCMP_s_zero, - FCMPE_h = FPCompareFixed | FP16 | 0x00000010u, - FCMPE_s = FPCompareFixed | 0x00000010u, - FCMPE_d = FPCompareFixed | FP64 | 0x00000010u, + FCMPE_h = FPCompareFixed | FP16 | 0x00000010, + FCMPE_s = FPCompareFixed | 0x00000010, + FCMPE_d = FPCompareFixed | FP64 | 0x00000010, FCMPE = FCMPE_s, - FCMPE_h_zero = FPCompareFixed | FP16 | 0x00000018u, - FCMPE_s_zero = FPCompareFixed | 0x00000018u, - FCMPE_d_zero = FPCompareFixed | FP64 | 0x00000018u, + FCMPE_h_zero = FPCompareFixed | FP16 | 0x00000018, + FCMPE_s_zero = FPCompareFixed | 0x00000018, + FCMPE_d_zero = FPCompareFixed | FP64 | 0x00000018, FCMPE_zero = FCMPE_s_zero }; // Floating point conditional compare. enum FPConditionalCompareOp : uint32_t { - FPConditionalCompareFixed = 0x1E200400u, - FPConditionalCompareFMask = 0x5F200C00u, - FPConditionalCompareMask = 0xFFE00C10u, - FCCMP_h = FPConditionalCompareFixed | FP16 | 0x00000000u, - FCCMP_s = FPConditionalCompareFixed | 0x00000000u, - FCCMP_d = FPConditionalCompareFixed | FP64 | 0x00000000u, + FPConditionalCompareFixed = 0x1E200400, + FPConditionalCompareFMask = 0x5F200C00, + FPConditionalCompareMask = 0xFFE00C10, + FCCMP_h = FPConditionalCompareFixed | FP16 | 0x00000000, + FCCMP_s = FPConditionalCompareFixed | 0x00000000, + FCCMP_d = FPConditionalCompareFixed | FP64 | 0x00000000, FCCMP = FCCMP_s, - FCCMPE_h = FPConditionalCompareFixed | FP16 | 0x00000010u, - FCCMPE_s = FPConditionalCompareFixed | 0x00000010u, - FCCMPE_d = FPConditionalCompareFixed | FP64 | 0x00000010u, + FCCMPE_h = FPConditionalCompareFixed | FP16 | 0x00000010, + FCCMPE_s = FPConditionalCompareFixed | 0x00000010, + FCCMPE_d = FPConditionalCompareFixed | FP64 | 0x00000010, FCCMPE = FCCMPE_s }; // Floating point conditional select. enum FPConditionalSelectOp : uint32_t { - FPConditionalSelectFixed = 0x1E200C00u, - FPConditionalSelectFMask = 0x5F200C00u, - FPConditionalSelectMask = 0xFFE00C00u, - FCSEL_h = FPConditionalSelectFixed | FP16 | 0x00000000u, - FCSEL_s = FPConditionalSelectFixed | 0x00000000u, - FCSEL_d = FPConditionalSelectFixed | FP64 | 0x00000000u, + FPConditionalSelectFixed = 0x1E200C00, + FPConditionalSelectFMask = 0x5F200C00, + FPConditionalSelectMask = 0xFFE00C00, + FCSEL_h = FPConditionalSelectFixed | FP16 | 0x00000000, + FCSEL_s = FPConditionalSelectFixed | 0x00000000, + FCSEL_d = FPConditionalSelectFixed | FP64 | 0x00000000, FCSEL = FCSEL_s }; // Floating point immediate. enum FPImmediateOp : uint32_t { - FPImmediateFixed = 0x1E201000u, - FPImmediateFMask = 0x5F201C00u, - FPImmediateMask = 0xFFE01C00u, - FMOV_h_imm = FPImmediateFixed | FP16 | 0x00000000u, - FMOV_s_imm = FPImmediateFixed | 0x00000000u, - FMOV_d_imm = FPImmediateFixed | FP64 | 0x00000000u + FPImmediateFixed = 0x1E201000, + FPImmediateFMask = 0x5F201C00, + FPImmediateMask = 0xFFE01C00, + FMOV_h_imm = FPImmediateFixed | FP16 | 0x00000000, + FMOV_s_imm = FPImmediateFixed | 0x00000000, + FMOV_d_imm = FPImmediateFixed | FP64 | 0x00000000 }; // Floating point data processing 1 source. enum FPDataProcessing1SourceOp : uint32_t { - FPDataProcessing1SourceFixed = 0x1E204000u, - FPDataProcessing1SourceFMask = 0x5F207C00u, - FPDataProcessing1SourceMask = 0xFFFFFC00u, - FMOV_h = FPDataProcessing1SourceFixed | FP16 | 0x00000000u, - FMOV_s = FPDataProcessing1SourceFixed | 0x00000000u, - FMOV_d = FPDataProcessing1SourceFixed | FP64 | 0x00000000u, + FPDataProcessing1SourceFixed = 0x1E204000, + FPDataProcessing1SourceFMask = 0x5F207C00, + FPDataProcessing1SourceMask = 0xFFFFFC00, + FMOV_h = FPDataProcessing1SourceFixed | FP16 | 0x00000000, + FMOV_s = FPDataProcessing1SourceFixed | 0x00000000, + FMOV_d = FPDataProcessing1SourceFixed | FP64 | 0x00000000, FMOV = FMOV_s, - FABS_h = FPDataProcessing1SourceFixed | FP16 | 0x00008000u, - FABS_s = FPDataProcessing1SourceFixed | 0x00008000u, - FABS_d = FPDataProcessing1SourceFixed | FP64 | 0x00008000u, + FABS_h = FPDataProcessing1SourceFixed | FP16 | 0x00008000, + FABS_s = FPDataProcessing1SourceFixed | 0x00008000, + FABS_d = FPDataProcessing1SourceFixed | FP64 | 0x00008000, FABS = FABS_s, - FNEG_h = FPDataProcessing1SourceFixed | FP16 | 0x00010000u, - FNEG_s = FPDataProcessing1SourceFixed | 0x00010000u, - FNEG_d = FPDataProcessing1SourceFixed | FP64 | 0x00010000u, + FNEG_h = FPDataProcessing1SourceFixed | FP16 | 0x00010000, + FNEG_s = FPDataProcessing1SourceFixed | 0x00010000, + FNEG_d = FPDataProcessing1SourceFixed | FP64 | 0x00010000, FNEG = FNEG_s, - FSQRT_h = FPDataProcessing1SourceFixed | FP16 | 0x00018000u, - FSQRT_s = FPDataProcessing1SourceFixed | 0x00018000u, - FSQRT_d = FPDataProcessing1SourceFixed | FP64 | 0x00018000u, + FSQRT_h = FPDataProcessing1SourceFixed | FP16 | 0x00018000, + FSQRT_s = FPDataProcessing1SourceFixed | 0x00018000, + FSQRT_d = FPDataProcessing1SourceFixed | FP64 | 0x00018000, FSQRT = FSQRT_s, FCVT_ds = FPDataProcessing1SourceFixed | 0x00028000, FCVT_sd = FPDataProcessing1SourceFixed | FP64 | 0x00020000, @@ -1597,86 +1606,86 @@ enum FPDataProcessing1SourceOp : uint32_t { FCVT_hd = FPDataProcessing1SourceFixed | FP64 | 0x00038000, FCVT_sh = FPDataProcessing1SourceFixed | 0x00C20000, FCVT_dh = FPDataProcessing1SourceFixed | 0x00C28000, - FRINT32X_s = FPDataProcessing1SourceFixed | 0x00088000u, - FRINT32X_d = FPDataProcessing1SourceFixed | FP64 | 0x00088000u, + FRINT32X_s = FPDataProcessing1SourceFixed | 0x00088000, + FRINT32X_d = FPDataProcessing1SourceFixed | FP64 | 0x00088000, FRINT32X = FRINT32X_s, - FRINT32Z_s = FPDataProcessing1SourceFixed | 0x00080000u, - FRINT32Z_d = FPDataProcessing1SourceFixed | FP64 | 0x00080000u, + FRINT32Z_s = FPDataProcessing1SourceFixed | 0x00080000, + FRINT32Z_d = FPDataProcessing1SourceFixed | FP64 | 0x00080000, FRINT32Z = FRINT32Z_s, - FRINT64X_s = FPDataProcessing1SourceFixed | 0x00098000u, - FRINT64X_d = FPDataProcessing1SourceFixed | FP64 | 0x00098000u, + FRINT64X_s = FPDataProcessing1SourceFixed | 0x00098000, + FRINT64X_d = FPDataProcessing1SourceFixed | FP64 | 0x00098000, FRINT64X = FRINT64X_s, - FRINT64Z_s = FPDataProcessing1SourceFixed | 0x00090000u, - FRINT64Z_d = FPDataProcessing1SourceFixed | FP64 | 0x00090000u, + FRINT64Z_s = FPDataProcessing1SourceFixed | 0x00090000, + FRINT64Z_d = FPDataProcessing1SourceFixed | FP64 | 0x00090000, FRINT64Z = FRINT64Z_s, - FRINTN_h = FPDataProcessing1SourceFixed | FP16 | 0x00040000u, - FRINTN_s = FPDataProcessing1SourceFixed | 0x00040000u, - FRINTN_d = FPDataProcessing1SourceFixed | FP64 | 0x00040000u, + FRINTN_h = FPDataProcessing1SourceFixed | FP16 | 0x00040000, + FRINTN_s = FPDataProcessing1SourceFixed | 0x00040000, + FRINTN_d = FPDataProcessing1SourceFixed | FP64 | 0x00040000, FRINTN = FRINTN_s, - FRINTP_h = FPDataProcessing1SourceFixed | FP16 | 0x00048000u, - FRINTP_s = FPDataProcessing1SourceFixed | 0x00048000u, - FRINTP_d = FPDataProcessing1SourceFixed | FP64 | 0x00048000u, + FRINTP_h = FPDataProcessing1SourceFixed | FP16 | 0x00048000, + FRINTP_s = FPDataProcessing1SourceFixed | 0x00048000, + FRINTP_d = FPDataProcessing1SourceFixed | FP64 | 0x00048000, FRINTP = FRINTP_s, - FRINTM_h = FPDataProcessing1SourceFixed | FP16 | 0x00050000u, - FRINTM_s = FPDataProcessing1SourceFixed | 0x00050000u, - FRINTM_d = FPDataProcessing1SourceFixed | FP64 | 0x00050000u, + FRINTM_h = FPDataProcessing1SourceFixed | FP16 | 0x00050000, + FRINTM_s = FPDataProcessing1SourceFixed | 0x00050000, + FRINTM_d = FPDataProcessing1SourceFixed | FP64 | 0x00050000, FRINTM = FRINTM_s, - FRINTZ_h = FPDataProcessing1SourceFixed | FP16 | 0x00058000u, - FRINTZ_s = FPDataProcessing1SourceFixed | 0x00058000u, - FRINTZ_d = FPDataProcessing1SourceFixed | FP64 | 0x00058000u, + FRINTZ_h = FPDataProcessing1SourceFixed | FP16 | 0x00058000, + FRINTZ_s = FPDataProcessing1SourceFixed | 0x00058000, + FRINTZ_d = FPDataProcessing1SourceFixed | FP64 | 0x00058000, FRINTZ = FRINTZ_s, - FRINTA_h = FPDataProcessing1SourceFixed | FP16 | 0x00060000u, - FRINTA_s = FPDataProcessing1SourceFixed | 0x00060000u, - FRINTA_d = FPDataProcessing1SourceFixed | FP64 | 0x00060000u, + FRINTA_h = FPDataProcessing1SourceFixed | FP16 | 0x00060000, + FRINTA_s = FPDataProcessing1SourceFixed | 0x00060000, + FRINTA_d = FPDataProcessing1SourceFixed | FP64 | 0x00060000, FRINTA = FRINTA_s, - FRINTX_h = FPDataProcessing1SourceFixed | FP16 | 0x00070000u, - FRINTX_s = FPDataProcessing1SourceFixed | 0x00070000u, - FRINTX_d = FPDataProcessing1SourceFixed | FP64 | 0x00070000u, + FRINTX_h = FPDataProcessing1SourceFixed | FP16 | 0x00070000, + FRINTX_s = FPDataProcessing1SourceFixed | 0x00070000, + FRINTX_d = FPDataProcessing1SourceFixed | FP64 | 0x00070000, FRINTX = FRINTX_s, - FRINTI_h = FPDataProcessing1SourceFixed | FP16 | 0x00078000u, - FRINTI_s = FPDataProcessing1SourceFixed | 0x00078000u, - FRINTI_d = FPDataProcessing1SourceFixed | FP64 | 0x00078000u, + FRINTI_h = FPDataProcessing1SourceFixed | FP16 | 0x00078000, + FRINTI_s = FPDataProcessing1SourceFixed | 0x00078000, + FRINTI_d = FPDataProcessing1SourceFixed | FP64 | 0x00078000, FRINTI = FRINTI_s }; // Floating point data processing 2 source. enum FPDataProcessing2SourceOp : uint32_t { - FPDataProcessing2SourceFixed = 0x1E200800u, - FPDataProcessing2SourceFMask = 0x5F200C00u, - FPDataProcessing2SourceMask = 0xFFE0FC00u, - FMUL = FPDataProcessing2SourceFixed | 0x00000000u, + FPDataProcessing2SourceFixed = 0x1E200800, + FPDataProcessing2SourceFMask = 0x5F200C00, + FPDataProcessing2SourceMask = 0xFFE0FC00, + FMUL = FPDataProcessing2SourceFixed | 0x00000000, FMUL_h = FMUL | FP16, FMUL_s = FMUL, FMUL_d = FMUL | FP64, - FDIV = FPDataProcessing2SourceFixed | 0x00001000u, + FDIV = FPDataProcessing2SourceFixed | 0x00001000, FDIV_h = FDIV | FP16, FDIV_s = FDIV, FDIV_d = FDIV | FP64, - FADD = FPDataProcessing2SourceFixed | 0x00002000u, + FADD = FPDataProcessing2SourceFixed | 0x00002000, FADD_h = FADD | FP16, FADD_s = FADD, FADD_d = FADD | FP64, - FSUB = FPDataProcessing2SourceFixed | 0x00003000u, + FSUB = FPDataProcessing2SourceFixed | 0x00003000, FSUB_h = FSUB | FP16, FSUB_s = FSUB, FSUB_d = FSUB | FP64, - FMAX = FPDataProcessing2SourceFixed | 0x00004000u, + FMAX = FPDataProcessing2SourceFixed | 0x00004000, FMAX_h = FMAX | FP16, FMAX_s = FMAX, FMAX_d = FMAX | FP64, - FMIN = FPDataProcessing2SourceFixed | 0x00005000u, + FMIN = FPDataProcessing2SourceFixed | 0x00005000, FMIN_h = FMIN | FP16, FMIN_s = FMIN, FMIN_d = FMIN | FP64, - FMAXNM = FPDataProcessing2SourceFixed | 0x00006000u, + FMAXNM = FPDataProcessing2SourceFixed | 0x00006000, FMAXNM_h = FMAXNM | FP16, FMAXNM_s = FMAXNM, FMAXNM_d = FMAXNM | FP64, - FMINNM = FPDataProcessing2SourceFixed | 0x00007000u, + FMINNM = FPDataProcessing2SourceFixed | 0x00007000, FMINNM_h = FMINNM | FP16, FMINNM_s = FMINNM, FMINNM_d = FMINNM | FP64, - FNMUL = FPDataProcessing2SourceFixed | 0x00008000u, + FNMUL = FPDataProcessing2SourceFixed | 0x00008000, FNMUL_h = FNMUL | FP16, FNMUL_s = FNMUL, FNMUL_d = FNMUL | FP64 @@ -1684,152 +1693,152 @@ enum FPDataProcessing2SourceOp : uint32_t { // Floating point data processing 3 source. enum FPDataProcessing3SourceOp : uint32_t { - FPDataProcessing3SourceFixed = 0x1F000000u, - FPDataProcessing3SourceFMask = 0x5F000000u, - FPDataProcessing3SourceMask = 0xFFE08000u, - FMADD_h = FPDataProcessing3SourceFixed | 0x00C00000u, - FMSUB_h = FPDataProcessing3SourceFixed | 0x00C08000u, - FNMADD_h = FPDataProcessing3SourceFixed | 0x00E00000u, - FNMSUB_h = FPDataProcessing3SourceFixed | 0x00E08000u, - FMADD_s = FPDataProcessing3SourceFixed | 0x00000000u, - FMSUB_s = FPDataProcessing3SourceFixed | 0x00008000u, - FNMADD_s = FPDataProcessing3SourceFixed | 0x00200000u, - FNMSUB_s = FPDataProcessing3SourceFixed | 0x00208000u, - FMADD_d = FPDataProcessing3SourceFixed | 0x00400000u, - FMSUB_d = FPDataProcessing3SourceFixed | 0x00408000u, - FNMADD_d = FPDataProcessing3SourceFixed | 0x00600000u, - FNMSUB_d = FPDataProcessing3SourceFixed | 0x00608000u + FPDataProcessing3SourceFixed = 0x1F000000, + FPDataProcessing3SourceFMask = 0x5F000000, + FPDataProcessing3SourceMask = 0xFFE08000, + FMADD_h = FPDataProcessing3SourceFixed | 0x00C00000, + FMSUB_h = FPDataProcessing3SourceFixed | 0x00C08000, + FNMADD_h = FPDataProcessing3SourceFixed | 0x00E00000, + FNMSUB_h = FPDataProcessing3SourceFixed | 0x00E08000, + FMADD_s = FPDataProcessing3SourceFixed | 0x00000000, + FMSUB_s = FPDataProcessing3SourceFixed | 0x00008000, + FNMADD_s = FPDataProcessing3SourceFixed | 0x00200000, + FNMSUB_s = FPDataProcessing3SourceFixed | 0x00208000, + FMADD_d = FPDataProcessing3SourceFixed | 0x00400000, + FMSUB_d = FPDataProcessing3SourceFixed | 0x00408000, + FNMADD_d = FPDataProcessing3SourceFixed | 0x00600000, + FNMSUB_d = FPDataProcessing3SourceFixed | 0x00608000 }; // Conversion between floating point and integer. enum FPIntegerConvertOp : uint32_t { - FPIntegerConvertFixed = 0x1E200000u, - FPIntegerConvertFMask = 0x5F20FC00u, - FPIntegerConvertMask = 0xFFFFFC00u, - FCVTNS = FPIntegerConvertFixed | 0x00000000u, + FPIntegerConvertFixed = 0x1E200000, + FPIntegerConvertFMask = 0x5F20FC00, + FPIntegerConvertMask = 0xFFFFFC00, + FCVTNS = FPIntegerConvertFixed | 0x00000000, FCVTNS_wh = FCVTNS | FP16, FCVTNS_xh = FCVTNS | SixtyFourBits | FP16, FCVTNS_ws = FCVTNS, FCVTNS_xs = FCVTNS | SixtyFourBits, FCVTNS_wd = FCVTNS | FP64, FCVTNS_xd = FCVTNS | SixtyFourBits | FP64, - FCVTNU = FPIntegerConvertFixed | 0x00010000u, + FCVTNU = FPIntegerConvertFixed | 0x00010000, FCVTNU_wh = FCVTNU | FP16, FCVTNU_xh = FCVTNU | SixtyFourBits | FP16, FCVTNU_ws = FCVTNU, FCVTNU_xs = FCVTNU | SixtyFourBits, FCVTNU_wd = FCVTNU | FP64, FCVTNU_xd = FCVTNU | SixtyFourBits | FP64, - FCVTPS = FPIntegerConvertFixed | 0x00080000u, + FCVTPS = FPIntegerConvertFixed | 0x00080000, FCVTPS_wh = FCVTPS | FP16, FCVTPS_xh = FCVTPS | SixtyFourBits | FP16, FCVTPS_ws = FCVTPS, FCVTPS_xs = FCVTPS | SixtyFourBits, FCVTPS_wd = FCVTPS | FP64, FCVTPS_xd = FCVTPS | SixtyFourBits | FP64, - FCVTPU = FPIntegerConvertFixed | 0x00090000u, + FCVTPU = FPIntegerConvertFixed | 0x00090000, FCVTPU_wh = FCVTPU | FP16, FCVTPU_xh = FCVTPU | SixtyFourBits | FP16, FCVTPU_ws = FCVTPU, FCVTPU_xs = FCVTPU | SixtyFourBits, FCVTPU_wd = FCVTPU | FP64, FCVTPU_xd = FCVTPU | SixtyFourBits | FP64, - FCVTMS = FPIntegerConvertFixed | 0x00100000u, + FCVTMS = FPIntegerConvertFixed | 0x00100000, FCVTMS_wh = FCVTMS | FP16, FCVTMS_xh = FCVTMS | SixtyFourBits | FP16, FCVTMS_ws = FCVTMS, FCVTMS_xs = FCVTMS | SixtyFourBits, FCVTMS_wd = FCVTMS | FP64, FCVTMS_xd = FCVTMS | SixtyFourBits | FP64, - FCVTMU = FPIntegerConvertFixed | 0x00110000u, + FCVTMU = FPIntegerConvertFixed | 0x00110000, FCVTMU_wh = FCVTMU | FP16, FCVTMU_xh = FCVTMU | SixtyFourBits | FP16, FCVTMU_ws = FCVTMU, FCVTMU_xs = FCVTMU | SixtyFourBits, FCVTMU_wd = FCVTMU | FP64, FCVTMU_xd = FCVTMU | SixtyFourBits | FP64, - FCVTZS = FPIntegerConvertFixed | 0x00180000u, + FCVTZS = FPIntegerConvertFixed | 0x00180000, FCVTZS_wh = FCVTZS | FP16, FCVTZS_xh = FCVTZS | SixtyFourBits | FP16, FCVTZS_ws = FCVTZS, FCVTZS_xs = FCVTZS | SixtyFourBits, FCVTZS_wd = FCVTZS | FP64, FCVTZS_xd = FCVTZS | SixtyFourBits | FP64, - FCVTZU = FPIntegerConvertFixed | 0x00190000u, + FCVTZU = FPIntegerConvertFixed | 0x00190000, FCVTZU_wh = FCVTZU | FP16, FCVTZU_xh = FCVTZU | SixtyFourBits | FP16, FCVTZU_ws = FCVTZU, FCVTZU_xs = FCVTZU | SixtyFourBits, FCVTZU_wd = FCVTZU | FP64, FCVTZU_xd = FCVTZU | SixtyFourBits | FP64, - SCVTF = FPIntegerConvertFixed | 0x00020000u, + SCVTF = FPIntegerConvertFixed | 0x00020000, SCVTF_hw = SCVTF | FP16, SCVTF_hx = SCVTF | SixtyFourBits | FP16, SCVTF_sw = SCVTF, SCVTF_sx = SCVTF | SixtyFourBits, SCVTF_dw = SCVTF | FP64, SCVTF_dx = SCVTF | SixtyFourBits | FP64, - UCVTF = FPIntegerConvertFixed | 0x00030000u, + UCVTF = FPIntegerConvertFixed | 0x00030000, UCVTF_hw = UCVTF | FP16, UCVTF_hx = UCVTF | SixtyFourBits | FP16, UCVTF_sw = UCVTF, UCVTF_sx = UCVTF | SixtyFourBits, UCVTF_dw = UCVTF | FP64, UCVTF_dx = UCVTF | SixtyFourBits | FP64, - FCVTAS = FPIntegerConvertFixed | 0x00040000u, + FCVTAS = FPIntegerConvertFixed | 0x00040000, FCVTAS_wh = FCVTAS | FP16, FCVTAS_xh = FCVTAS | SixtyFourBits | FP16, FCVTAS_ws = FCVTAS, FCVTAS_xs = FCVTAS | SixtyFourBits, FCVTAS_wd = FCVTAS | FP64, FCVTAS_xd = FCVTAS | SixtyFourBits | FP64, - FCVTAU = FPIntegerConvertFixed | 0x00050000u, + FCVTAU = FPIntegerConvertFixed | 0x00050000, FCVTAU_wh = FCVTAU | FP16, FCVTAU_xh = FCVTAU | SixtyFourBits | FP16, FCVTAU_ws = FCVTAU, FCVTAU_xs = FCVTAU | SixtyFourBits, FCVTAU_wd = FCVTAU | FP64, FCVTAU_xd = FCVTAU | SixtyFourBits | FP64, - FMOV_wh = FPIntegerConvertFixed | 0x00060000u | FP16, - FMOV_hw = FPIntegerConvertFixed | 0x00070000u | FP16, + FMOV_wh = FPIntegerConvertFixed | 0x00060000 | FP16, + FMOV_hw = FPIntegerConvertFixed | 0x00070000 | FP16, FMOV_xh = FMOV_wh | SixtyFourBits, FMOV_hx = FMOV_hw | SixtyFourBits, - FMOV_ws = FPIntegerConvertFixed | 0x00060000u, - FMOV_sw = FPIntegerConvertFixed | 0x00070000u, + FMOV_ws = FPIntegerConvertFixed | 0x00060000, + FMOV_sw = FPIntegerConvertFixed | 0x00070000, FMOV_xd = FMOV_ws | SixtyFourBits | FP64, FMOV_dx = FMOV_sw | SixtyFourBits | FP64, - FMOV_d1_x = FPIntegerConvertFixed | SixtyFourBits | 0x008F0000u, - FMOV_x_d1 = FPIntegerConvertFixed | SixtyFourBits | 0x008E0000u, + FMOV_d1_x = FPIntegerConvertFixed | SixtyFourBits | 0x008F0000, + FMOV_x_d1 = FPIntegerConvertFixed | SixtyFourBits | 0x008E0000, FJCVTZS = FPIntegerConvertFixed | FP64 | 0x001E0000 }; // Conversion between fixed point and floating point. enum FPFixedPointConvertOp : uint32_t { - FPFixedPointConvertFixed = 0x1E000000u, - FPFixedPointConvertFMask = 0x5F200000u, - FPFixedPointConvertMask = 0xFFFF0000u, - FCVTZS_fixed = FPFixedPointConvertFixed | 0x00180000u, + FPFixedPointConvertFixed = 0x1E000000, + FPFixedPointConvertFMask = 0x5F200000, + FPFixedPointConvertMask = 0xFFFF0000, + FCVTZS_fixed = FPFixedPointConvertFixed | 0x00180000, FCVTZS_wh_fixed = FCVTZS_fixed | FP16, FCVTZS_xh_fixed = FCVTZS_fixed | SixtyFourBits | FP16, FCVTZS_ws_fixed = FCVTZS_fixed, FCVTZS_xs_fixed = FCVTZS_fixed | SixtyFourBits, FCVTZS_wd_fixed = FCVTZS_fixed | FP64, FCVTZS_xd_fixed = FCVTZS_fixed | SixtyFourBits | FP64, - FCVTZU_fixed = FPFixedPointConvertFixed | 0x00190000u, + FCVTZU_fixed = FPFixedPointConvertFixed | 0x00190000, FCVTZU_wh_fixed = FCVTZU_fixed | FP16, FCVTZU_xh_fixed = FCVTZU_fixed | SixtyFourBits | FP16, FCVTZU_ws_fixed = FCVTZU_fixed, FCVTZU_xs_fixed = FCVTZU_fixed | SixtyFourBits, FCVTZU_wd_fixed = FCVTZU_fixed | FP64, FCVTZU_xd_fixed = FCVTZU_fixed | SixtyFourBits | FP64, - SCVTF_fixed = FPFixedPointConvertFixed | 0x00020000u, + SCVTF_fixed = FPFixedPointConvertFixed | 0x00020000, SCVTF_hw_fixed = SCVTF_fixed | FP16, SCVTF_hx_fixed = SCVTF_fixed | SixtyFourBits | FP16, SCVTF_sw_fixed = SCVTF_fixed, SCVTF_sx_fixed = SCVTF_fixed | SixtyFourBits, SCVTF_dw_fixed = SCVTF_fixed | FP64, SCVTF_dx_fixed = SCVTF_fixed | SixtyFourBits | FP64, - UCVTF_fixed = FPFixedPointConvertFixed | 0x00030000u, + UCVTF_fixed = FPFixedPointConvertFixed | 0x00030000, UCVTF_hw_fixed = UCVTF_fixed | FP16, UCVTF_hx_fixed = UCVTF_fixed | SixtyFourBits | FP16, UCVTF_sw_fixed = UCVTF_fixed, @@ -1840,57 +1849,57 @@ enum FPFixedPointConvertOp : uint32_t { // Crypto - two register SHA. enum Crypto2RegSHAOp : uint32_t { - Crypto2RegSHAFixed = 0x5E280800u, - Crypto2RegSHAFMask = 0xFF3E0C00u + Crypto2RegSHAFixed = 0x5E280800, + Crypto2RegSHAFMask = 0xFF3E0C00 }; // Crypto - three register SHA. enum Crypto3RegSHAOp : uint32_t { - Crypto3RegSHAFixed = 0x5E000000u, - Crypto3RegSHAFMask = 0xFF208C00u + Crypto3RegSHAFixed = 0x5E000000, + Crypto3RegSHAFMask = 0xFF208C00 }; // Crypto - AES. enum CryptoAESOp : uint32_t { - CryptoAESFixed = 0x4E280800u, - CryptoAESFMask = 0xFF3E0C00u + CryptoAESFixed = 0x4E280800, + CryptoAESFMask = 0xFF3E0C00 }; // NEON instructions with two register operands. enum NEON2RegMiscOp : uint32_t { - NEON2RegMiscFixed = 0x0E200800u, - NEON2RegMiscFMask = 0x9F3E0C00u, - NEON2RegMiscMask = 0xBF3FFC00u, - NEON2RegMiscUBit = 0x20000000u, - NEON_REV64 = NEON2RegMiscFixed | 0x00000000u, - NEON_REV32 = NEON2RegMiscFixed | 0x20000000u, - NEON_REV16 = NEON2RegMiscFixed | 0x00001000u, - NEON_SADDLP = NEON2RegMiscFixed | 0x00002000u, + NEON2RegMiscFixed = 0x0E200800, + NEON2RegMiscFMask = 0x9F3E0C00, + NEON2RegMiscMask = 0xBF3FFC00, + NEON2RegMiscUBit = 0x20000000, + NEON_REV64 = NEON2RegMiscFixed | 0x00000000, + NEON_REV32 = NEON2RegMiscFixed | 0x20000000, + NEON_REV16 = NEON2RegMiscFixed | 0x00001000, + NEON_SADDLP = NEON2RegMiscFixed | 0x00002000, NEON_UADDLP = NEON_SADDLP | NEON2RegMiscUBit, - NEON_SUQADD = NEON2RegMiscFixed | 0x00003000u, + NEON_SUQADD = NEON2RegMiscFixed | 0x00003000, NEON_USQADD = NEON_SUQADD | NEON2RegMiscUBit, - NEON_CLS = NEON2RegMiscFixed | 0x00004000u, - NEON_CLZ = NEON2RegMiscFixed | 0x20004000u, - NEON_CNT = NEON2RegMiscFixed | 0x00005000u, - NEON_RBIT_NOT = NEON2RegMiscFixed | 0x20005000u, - NEON_SADALP = NEON2RegMiscFixed | 0x00006000u, + NEON_CLS = NEON2RegMiscFixed | 0x00004000, + NEON_CLZ = NEON2RegMiscFixed | 0x20004000, + NEON_CNT = NEON2RegMiscFixed | 0x00005000, + NEON_RBIT_NOT = NEON2RegMiscFixed | 0x20005000, + NEON_SADALP = NEON2RegMiscFixed | 0x00006000, NEON_UADALP = NEON_SADALP | NEON2RegMiscUBit, - NEON_SQABS = NEON2RegMiscFixed | 0x00007000u, - NEON_SQNEG = NEON2RegMiscFixed | 0x20007000u, - NEON_CMGT_zero = NEON2RegMiscFixed | 0x00008000u, - NEON_CMGE_zero = NEON2RegMiscFixed | 0x20008000u, - NEON_CMEQ_zero = NEON2RegMiscFixed | 0x00009000u, - NEON_CMLE_zero = NEON2RegMiscFixed | 0x20009000u, - NEON_CMLT_zero = NEON2RegMiscFixed | 0x0000A000u, - NEON_ABS = NEON2RegMiscFixed | 0x0000B000u, - NEON_NEG = NEON2RegMiscFixed | 0x2000B000u, - NEON_XTN = NEON2RegMiscFixed | 0x00012000u, - NEON_SQXTUN = NEON2RegMiscFixed | 0x20012000u, - NEON_SHLL = NEON2RegMiscFixed | 0x20013000u, - NEON_SQXTN = NEON2RegMiscFixed | 0x00014000u, + NEON_SQABS = NEON2RegMiscFixed | 0x00007000, + NEON_SQNEG = NEON2RegMiscFixed | 0x20007000, + NEON_CMGT_zero = NEON2RegMiscFixed | 0x00008000, + NEON_CMGE_zero = NEON2RegMiscFixed | 0x20008000, + NEON_CMEQ_zero = NEON2RegMiscFixed | 0x00009000, + NEON_CMLE_zero = NEON2RegMiscFixed | 0x20009000, + NEON_CMLT_zero = NEON2RegMiscFixed | 0x0000A000, + NEON_ABS = NEON2RegMiscFixed | 0x0000B000, + NEON_NEG = NEON2RegMiscFixed | 0x2000B000, + NEON_XTN = NEON2RegMiscFixed | 0x00012000, + NEON_SQXTUN = NEON2RegMiscFixed | 0x20012000, + NEON_SHLL = NEON2RegMiscFixed | 0x20013000, + NEON_SQXTN = NEON2RegMiscFixed | 0x00014000, NEON_UQXTN = NEON_SQXTN | NEON2RegMiscUBit, - NEON2RegMiscOpcode = 0x0001F000u, + NEON2RegMiscOpcode = 0x0001F000, NEON_RBIT_NOT_opcode = NEON_RBIT_NOT & NEON2RegMiscOpcode, NEON_NEG_opcode = NEON_NEG & NEON2RegMiscOpcode, NEON_XTN_opcode = NEON_XTN & NEON2RegMiscOpcode, @@ -1898,45 +1907,45 @@ enum NEON2RegMiscOp : uint32_t { // These instructions use only one bit of the size field. The other bit is // used to distinguish between instructions. - NEON2RegMiscFPMask = NEON2RegMiscMask | 0x00800000u, - NEON_FABS = NEON2RegMiscFixed | 0x0080F000u, - NEON_FNEG = NEON2RegMiscFixed | 0x2080F000u, - NEON_FCVTN = NEON2RegMiscFixed | 0x00016000u, - NEON_FCVTXN = NEON2RegMiscFixed | 0x20016000u, - NEON_FCVTL = NEON2RegMiscFixed | 0x00017000u, - NEON_FRINT32X = NEON2RegMiscFixed | 0x2001E000u, - NEON_FRINT32Z = NEON2RegMiscFixed | 0x0001E000u, - NEON_FRINT64X = NEON2RegMiscFixed | 0x2001F000u, - NEON_FRINT64Z = NEON2RegMiscFixed | 0x0001F000u, - NEON_FRINTN = NEON2RegMiscFixed | 0x00018000u, - NEON_FRINTA = NEON2RegMiscFixed | 0x20018000u, - NEON_FRINTP = NEON2RegMiscFixed | 0x00818000u, - NEON_FRINTM = NEON2RegMiscFixed | 0x00019000u, - NEON_FRINTX = NEON2RegMiscFixed | 0x20019000u, - NEON_FRINTZ = NEON2RegMiscFixed | 0x00819000u, - NEON_FRINTI = NEON2RegMiscFixed | 0x20819000u, - NEON_FCVTNS = NEON2RegMiscFixed | 0x0001A000u, + NEON2RegMiscFPMask = NEON2RegMiscMask | 0x00800000, + NEON_FABS = NEON2RegMiscFixed | 0x0080F000, + NEON_FNEG = NEON2RegMiscFixed | 0x2080F000, + NEON_FCVTN = NEON2RegMiscFixed | 0x00016000, + NEON_FCVTXN = NEON2RegMiscFixed | 0x20016000, + NEON_FCVTL = NEON2RegMiscFixed | 0x00017000, + NEON_FRINT32X = NEON2RegMiscFixed | 0x2001E000, + NEON_FRINT32Z = NEON2RegMiscFixed | 0x0001E000, + NEON_FRINT64X = NEON2RegMiscFixed | 0x2001F000, + NEON_FRINT64Z = NEON2RegMiscFixed | 0x0001F000, + NEON_FRINTN = NEON2RegMiscFixed | 0x00018000, + NEON_FRINTA = NEON2RegMiscFixed | 0x20018000, + NEON_FRINTP = NEON2RegMiscFixed | 0x00818000, + NEON_FRINTM = NEON2RegMiscFixed | 0x00019000, + NEON_FRINTX = NEON2RegMiscFixed | 0x20019000, + NEON_FRINTZ = NEON2RegMiscFixed | 0x00819000, + NEON_FRINTI = NEON2RegMiscFixed | 0x20819000, + NEON_FCVTNS = NEON2RegMiscFixed | 0x0001A000, NEON_FCVTNU = NEON_FCVTNS | NEON2RegMiscUBit, - NEON_FCVTPS = NEON2RegMiscFixed | 0x0081A000u, + NEON_FCVTPS = NEON2RegMiscFixed | 0x0081A000, NEON_FCVTPU = NEON_FCVTPS | NEON2RegMiscUBit, - NEON_FCVTMS = NEON2RegMiscFixed | 0x0001B000u, + NEON_FCVTMS = NEON2RegMiscFixed | 0x0001B000, NEON_FCVTMU = NEON_FCVTMS | NEON2RegMiscUBit, - NEON_FCVTZS = NEON2RegMiscFixed | 0x0081B000u, + NEON_FCVTZS = NEON2RegMiscFixed | 0x0081B000, NEON_FCVTZU = NEON_FCVTZS | NEON2RegMiscUBit, - NEON_FCVTAS = NEON2RegMiscFixed | 0x0001C000u, + NEON_FCVTAS = NEON2RegMiscFixed | 0x0001C000, NEON_FCVTAU = NEON_FCVTAS | NEON2RegMiscUBit, - NEON_FSQRT = NEON2RegMiscFixed | 0x2081F000u, - NEON_SCVTF = NEON2RegMiscFixed | 0x0001D000u, + NEON_FSQRT = NEON2RegMiscFixed | 0x2081F000, + NEON_SCVTF = NEON2RegMiscFixed | 0x0001D000, NEON_UCVTF = NEON_SCVTF | NEON2RegMiscUBit, - NEON_URSQRTE = NEON2RegMiscFixed | 0x2081C000u, - NEON_URECPE = NEON2RegMiscFixed | 0x0081C000u, - NEON_FRSQRTE = NEON2RegMiscFixed | 0x2081D000u, - NEON_FRECPE = NEON2RegMiscFixed | 0x0081D000u, - NEON_FCMGT_zero = NEON2RegMiscFixed | 0x0080C000u, - NEON_FCMGE_zero = NEON2RegMiscFixed | 0x2080C000u, - NEON_FCMEQ_zero = NEON2RegMiscFixed | 0x0080D000u, - NEON_FCMLE_zero = NEON2RegMiscFixed | 0x2080D000u, - NEON_FCMLT_zero = NEON2RegMiscFixed | 0x0080E000u, + NEON_URSQRTE = NEON2RegMiscFixed | 0x2081C000, + NEON_URECPE = NEON2RegMiscFixed | 0x0081C000, + NEON_FRSQRTE = NEON2RegMiscFixed | 0x2081D000, + NEON_FRECPE = NEON2RegMiscFixed | 0x0081D000, + NEON_FCMGT_zero = NEON2RegMiscFixed | 0x0080C000, + NEON_FCMGE_zero = NEON2RegMiscFixed | 0x2080C000, + NEON_FCMEQ_zero = NEON2RegMiscFixed | 0x0080D000, + NEON_FCMLE_zero = NEON2RegMiscFixed | 0x2080D000, + NEON_FCMLT_zero = NEON2RegMiscFixed | 0x0080E000, NEON_FCVTL_opcode = NEON_FCVTL & NEON2RegMiscOpcode, NEON_FCVTN_opcode = NEON_FCVTN & NEON2RegMiscOpcode @@ -1944,76 +1953,76 @@ enum NEON2RegMiscOp : uint32_t { // NEON instructions with two register operands (FP16). enum NEON2RegMiscFP16Op : uint32_t { - NEON2RegMiscFP16Fixed = 0x0E780800u, - NEON2RegMiscFP16FMask = 0x9F7E0C00u, - NEON2RegMiscFP16Mask = 0xBFFFFC00u, - NEON_FRINTN_H = NEON2RegMiscFP16Fixed | 0x00018000u, - NEON_FRINTM_H = NEON2RegMiscFP16Fixed | 0x00019000u, - NEON_FCVTNS_H = NEON2RegMiscFP16Fixed | 0x0001A000u, - NEON_FCVTMS_H = NEON2RegMiscFP16Fixed | 0x0001B000u, - NEON_FCVTAS_H = NEON2RegMiscFP16Fixed | 0x0001C000u, - NEON_SCVTF_H = NEON2RegMiscFP16Fixed | 0x0001D000u, - NEON_FCMGT_H_zero = NEON2RegMiscFP16Fixed | 0x0080C000u, - NEON_FCMEQ_H_zero = NEON2RegMiscFP16Fixed | 0x0080D000u, - NEON_FCMLT_H_zero = NEON2RegMiscFP16Fixed | 0x0080E000u, - NEON_FABS_H = NEON2RegMiscFP16Fixed | 0x0080F000u, - NEON_FRINTP_H = NEON2RegMiscFP16Fixed | 0x00818000u, - NEON_FRINTZ_H = NEON2RegMiscFP16Fixed | 0x00819000u, - NEON_FCVTPS_H = NEON2RegMiscFP16Fixed | 0x0081A000u, - NEON_FCVTZS_H = NEON2RegMiscFP16Fixed | 0x0081B000u, - NEON_FRECPE_H = NEON2RegMiscFP16Fixed | 0x0081D000u, - NEON_FRINTA_H = NEON2RegMiscFP16Fixed | 0x20018000u, - NEON_FRINTX_H = NEON2RegMiscFP16Fixed | 0x20019000u, - NEON_FCVTNU_H = NEON2RegMiscFP16Fixed | 0x2001A000u, - NEON_FCVTMU_H = NEON2RegMiscFP16Fixed | 0x2001B000u, - NEON_FCVTAU_H = NEON2RegMiscFP16Fixed | 0x2001C000u, - NEON_UCVTF_H = NEON2RegMiscFP16Fixed | 0x2001D000u, - NEON_FCMGE_H_zero = NEON2RegMiscFP16Fixed | 0x2080C000u, - NEON_FCMLE_H_zero = NEON2RegMiscFP16Fixed | 0x2080D000u, - NEON_FNEG_H = NEON2RegMiscFP16Fixed | 0x2080F000u, - NEON_FRINTI_H = NEON2RegMiscFP16Fixed | 0x20819000u, - NEON_FCVTPU_H = NEON2RegMiscFP16Fixed | 0x2081A000u, - NEON_FCVTZU_H = NEON2RegMiscFP16Fixed | 0x2081B000u, - NEON_FRSQRTE_H = NEON2RegMiscFP16Fixed | 0x2081D000u, - NEON_FSQRT_H = NEON2RegMiscFP16Fixed | 0x2081F000u + NEON2RegMiscFP16Fixed = 0x0E780800, + NEON2RegMiscFP16FMask = 0x9F7E0C00, + NEON2RegMiscFP16Mask = 0xBFFFFC00, + NEON_FRINTN_H = NEON2RegMiscFP16Fixed | 0x00018000, + NEON_FRINTM_H = NEON2RegMiscFP16Fixed | 0x00019000, + NEON_FCVTNS_H = NEON2RegMiscFP16Fixed | 0x0001A000, + NEON_FCVTMS_H = NEON2RegMiscFP16Fixed | 0x0001B000, + NEON_FCVTAS_H = NEON2RegMiscFP16Fixed | 0x0001C000, + NEON_SCVTF_H = NEON2RegMiscFP16Fixed | 0x0001D000, + NEON_FCMGT_H_zero = NEON2RegMiscFP16Fixed | 0x0080C000, + NEON_FCMEQ_H_zero = NEON2RegMiscFP16Fixed | 0x0080D000, + NEON_FCMLT_H_zero = NEON2RegMiscFP16Fixed | 0x0080E000, + NEON_FABS_H = NEON2RegMiscFP16Fixed | 0x0080F000, + NEON_FRINTP_H = NEON2RegMiscFP16Fixed | 0x00818000, + NEON_FRINTZ_H = NEON2RegMiscFP16Fixed | 0x00819000, + NEON_FCVTPS_H = NEON2RegMiscFP16Fixed | 0x0081A000, + NEON_FCVTZS_H = NEON2RegMiscFP16Fixed | 0x0081B000, + NEON_FRECPE_H = NEON2RegMiscFP16Fixed | 0x0081D000, + NEON_FRINTA_H = NEON2RegMiscFP16Fixed | 0x20018000, + NEON_FRINTX_H = NEON2RegMiscFP16Fixed | 0x20019000, + NEON_FCVTNU_H = NEON2RegMiscFP16Fixed | 0x2001A000, + NEON_FCVTMU_H = NEON2RegMiscFP16Fixed | 0x2001B000, + NEON_FCVTAU_H = NEON2RegMiscFP16Fixed | 0x2001C000, + NEON_UCVTF_H = NEON2RegMiscFP16Fixed | 0x2001D000, + NEON_FCMGE_H_zero = NEON2RegMiscFP16Fixed | 0x2080C000, + NEON_FCMLE_H_zero = NEON2RegMiscFP16Fixed | 0x2080D000, + NEON_FNEG_H = NEON2RegMiscFP16Fixed | 0x2080F000, + NEON_FRINTI_H = NEON2RegMiscFP16Fixed | 0x20819000, + NEON_FCVTPU_H = NEON2RegMiscFP16Fixed | 0x2081A000, + NEON_FCVTZU_H = NEON2RegMiscFP16Fixed | 0x2081B000, + NEON_FRSQRTE_H = NEON2RegMiscFP16Fixed | 0x2081D000, + NEON_FSQRT_H = NEON2RegMiscFP16Fixed | 0x2081F000 }; // NEON instructions with three same-type operands. enum NEON3SameOp : uint32_t { - NEON3SameFixed = 0x0E200400u, - NEON3SameFMask = 0x9F200400u, - NEON3SameMask = 0xBF20FC00u, - NEON3SameUBit = 0x20000000u, - NEON_ADD = NEON3SameFixed | 0x00008000u, - NEON_ADDP = NEON3SameFixed | 0x0000B800u, - NEON_SHADD = NEON3SameFixed | 0x00000000u, - NEON_SHSUB = NEON3SameFixed | 0x00002000u, - NEON_SRHADD = NEON3SameFixed | 0x00001000u, - NEON_CMEQ = NEON3SameFixed | NEON3SameUBit | 0x00008800u, - NEON_CMGE = NEON3SameFixed | 0x00003800u, - NEON_CMGT = NEON3SameFixed | 0x00003000u, + NEON3SameFixed = 0x0E200400, + NEON3SameFMask = 0x9F200400, + NEON3SameMask = 0xBF20FC00, + NEON3SameUBit = 0x20000000, + NEON_ADD = NEON3SameFixed | 0x00008000, + NEON_ADDP = NEON3SameFixed | 0x0000B800, + NEON_SHADD = NEON3SameFixed | 0x00000000, + NEON_SHSUB = NEON3SameFixed | 0x00002000, + NEON_SRHADD = NEON3SameFixed | 0x00001000, + NEON_CMEQ = NEON3SameFixed | NEON3SameUBit | 0x00008800, + NEON_CMGE = NEON3SameFixed | 0x00003800, + NEON_CMGT = NEON3SameFixed | 0x00003000, NEON_CMHI = NEON3SameFixed | NEON3SameUBit | NEON_CMGT, NEON_CMHS = NEON3SameFixed | NEON3SameUBit | NEON_CMGE, - NEON_CMTST = NEON3SameFixed | 0x00008800u, - NEON_MLA = NEON3SameFixed | 0x00009000u, - NEON_MLS = NEON3SameFixed | 0x20009000u, - NEON_MUL = NEON3SameFixed | 0x00009800u, - NEON_PMUL = NEON3SameFixed | 0x20009800u, - NEON_SRSHL = NEON3SameFixed | 0x00005000u, - NEON_SQSHL = NEON3SameFixed | 0x00004800u, - NEON_SQRSHL = NEON3SameFixed | 0x00005800u, - NEON_SSHL = NEON3SameFixed | 0x00004000u, - NEON_SMAX = NEON3SameFixed | 0x00006000u, - NEON_SMAXP = NEON3SameFixed | 0x0000A000u, - NEON_SMIN = NEON3SameFixed | 0x00006800u, - NEON_SMINP = NEON3SameFixed | 0x0000A800u, - NEON_SABD = NEON3SameFixed | 0x00007000u, - NEON_SABA = NEON3SameFixed | 0x00007800u, + NEON_CMTST = NEON3SameFixed | 0x00008800, + NEON_MLA = NEON3SameFixed | 0x00009000, + NEON_MLS = NEON3SameFixed | 0x20009000, + NEON_MUL = NEON3SameFixed | 0x00009800, + NEON_PMUL = NEON3SameFixed | 0x20009800, + NEON_SRSHL = NEON3SameFixed | 0x00005000, + NEON_SQSHL = NEON3SameFixed | 0x00004800, + NEON_SQRSHL = NEON3SameFixed | 0x00005800, + NEON_SSHL = NEON3SameFixed | 0x00004000, + NEON_SMAX = NEON3SameFixed | 0x00006000, + NEON_SMAXP = NEON3SameFixed | 0x0000A000, + NEON_SMIN = NEON3SameFixed | 0x00006800, + NEON_SMINP = NEON3SameFixed | 0x0000A800, + NEON_SABD = NEON3SameFixed | 0x00007000, + NEON_SABA = NEON3SameFixed | 0x00007800, NEON_UABD = NEON3SameFixed | NEON3SameUBit | NEON_SABD, NEON_UABA = NEON3SameFixed | NEON3SameUBit | NEON_SABA, - NEON_SQADD = NEON3SameFixed | 0x00000800u, - NEON_SQSUB = NEON3SameFixed | 0x00002800u, - NEON_SUB = NEON3SameFixed | NEON3SameUBit | 0x00008000u, + NEON_SQADD = NEON3SameFixed | 0x00000800, + NEON_SQSUB = NEON3SameFixed | 0x00002800, + NEON_SUB = NEON3SameFixed | NEON3SameUBit | 0x00008000, NEON_UHADD = NEON3SameFixed | NEON3SameUBit | NEON_SHADD, NEON_UHSUB = NEON3SameFixed | NEON3SameUBit | NEON_SHSUB, NEON_URHADD = NEON3SameFixed | NEON3SameUBit | NEON_SRHADD, @@ -2027,153 +2036,153 @@ enum NEON3SameOp : uint32_t { NEON_UQSHL = NEON3SameFixed | NEON3SameUBit | NEON_SQSHL, NEON_UQSUB = NEON3SameFixed | NEON3SameUBit | NEON_SQSUB, NEON_USHL = NEON3SameFixed | NEON3SameUBit | NEON_SSHL, - NEON_SQDMULH = NEON3SameFixed | 0x0000B000u, - NEON_SQRDMULH = NEON3SameFixed | 0x2000B000u, + NEON_SQDMULH = NEON3SameFixed | 0x0000B000, + NEON_SQRDMULH = NEON3SameFixed | 0x2000B000, // NEON floating point instructions with three same-type operands. - NEON3SameFPFixed = NEON3SameFixed | 0x0000C000u, - NEON3SameFPFMask = NEON3SameFMask | 0x0000C000u, - NEON3SameFPMask = NEON3SameMask | 0x00800000u, - NEON_FADD = NEON3SameFixed | 0x0000D000u, - NEON_FSUB = NEON3SameFixed | 0x0080D000u, - NEON_FMUL = NEON3SameFixed | 0x2000D800u, - NEON_FDIV = NEON3SameFixed | 0x2000F800u, - NEON_FMAX = NEON3SameFixed | 0x0000F000u, - NEON_FMAXNM = NEON3SameFixed | 0x0000C000u, - NEON_FMAXP = NEON3SameFixed | 0x2000F000u, - NEON_FMAXNMP = NEON3SameFixed | 0x2000C000u, - NEON_FMIN = NEON3SameFixed | 0x0080F000u, - NEON_FMINNM = NEON3SameFixed | 0x0080C000u, - NEON_FMINP = NEON3SameFixed | 0x2080F000u, - NEON_FMINNMP = NEON3SameFixed | 0x2080C000u, - NEON_FMLA = NEON3SameFixed | 0x0000C800u, - NEON_FMLS = NEON3SameFixed | 0x0080C800u, - NEON_FMULX = NEON3SameFixed | 0x0000D800u, - NEON_FRECPS = NEON3SameFixed | 0x0000F800u, - NEON_FRSQRTS = NEON3SameFixed | 0x0080F800u, - NEON_FABD = NEON3SameFixed | 0x2080D000u, - NEON_FADDP = NEON3SameFixed | 0x2000D000u, - NEON_FCMEQ = NEON3SameFixed | 0x0000E000u, - NEON_FCMGE = NEON3SameFixed | 0x2000E000u, - NEON_FCMGT = NEON3SameFixed | 0x2080E000u, - NEON_FACGE = NEON3SameFixed | 0x2000E800u, - NEON_FACGT = NEON3SameFixed | 0x2080E800u, + NEON3SameFPFixed = NEON3SameFixed | 0x0000C000, + NEON3SameFPFMask = NEON3SameFMask | 0x0000C000, + NEON3SameFPMask = NEON3SameMask | 0x00800000, + NEON_FADD = NEON3SameFixed | 0x0000D000, + NEON_FSUB = NEON3SameFixed | 0x0080D000, + NEON_FMUL = NEON3SameFixed | 0x2000D800, + NEON_FDIV = NEON3SameFixed | 0x2000F800, + NEON_FMAX = NEON3SameFixed | 0x0000F000, + NEON_FMAXNM = NEON3SameFixed | 0x0000C000, + NEON_FMAXP = NEON3SameFixed | 0x2000F000, + NEON_FMAXNMP = NEON3SameFixed | 0x2000C000, + NEON_FMIN = NEON3SameFixed | 0x0080F000, + NEON_FMINNM = NEON3SameFixed | 0x0080C000, + NEON_FMINP = NEON3SameFixed | 0x2080F000, + NEON_FMINNMP = NEON3SameFixed | 0x2080C000, + NEON_FMLA = NEON3SameFixed | 0x0000C800, + NEON_FMLS = NEON3SameFixed | 0x0080C800, + NEON_FMULX = NEON3SameFixed | 0x0000D800, + NEON_FRECPS = NEON3SameFixed | 0x0000F800, + NEON_FRSQRTS = NEON3SameFixed | 0x0080F800, + NEON_FABD = NEON3SameFixed | 0x2080D000, + NEON_FADDP = NEON3SameFixed | 0x2000D000, + NEON_FCMEQ = NEON3SameFixed | 0x0000E000, + NEON_FCMGE = NEON3SameFixed | 0x2000E000, + NEON_FCMGT = NEON3SameFixed | 0x2080E000, + NEON_FACGE = NEON3SameFixed | 0x2000E800, + NEON_FACGT = NEON3SameFixed | 0x2080E800, // NEON logical instructions with three same-type operands. - NEON3SameLogicalFixed = NEON3SameFixed | 0x00001800u, - NEON3SameLogicalFMask = NEON3SameFMask | 0x0000F800u, - NEON3SameLogicalMask = 0xBFE0FC00u, + NEON3SameLogicalFixed = NEON3SameFixed | 0x00001800, + NEON3SameLogicalFMask = NEON3SameFMask | 0x0000F800, + NEON3SameLogicalMask = 0xBFE0FC00, NEON3SameLogicalFormatMask = NEON_Q, - NEON_AND = NEON3SameLogicalFixed | 0x00000000u, - NEON_ORR = NEON3SameLogicalFixed | 0x00A00000u, - NEON_ORN = NEON3SameLogicalFixed | 0x00C00000u, - NEON_EOR = NEON3SameLogicalFixed | 0x20000000u, - NEON_BIC = NEON3SameLogicalFixed | 0x00400000u, - NEON_BIF = NEON3SameLogicalFixed | 0x20C00000u, - NEON_BIT = NEON3SameLogicalFixed | 0x20800000u, - NEON_BSL = NEON3SameLogicalFixed | 0x20400000u, + NEON_AND = NEON3SameLogicalFixed | 0x00000000, + NEON_ORR = NEON3SameLogicalFixed | 0x00A00000, + NEON_ORN = NEON3SameLogicalFixed | 0x00C00000, + NEON_EOR = NEON3SameLogicalFixed | 0x20000000, + NEON_BIC = NEON3SameLogicalFixed | 0x00400000, + NEON_BIF = NEON3SameLogicalFixed | 0x20C00000, + NEON_BIT = NEON3SameLogicalFixed | 0x20800000, + NEON_BSL = NEON3SameLogicalFixed | 0x20400000, // FHM (FMLAL-like) instructions have an oddball encoding scheme under 3Same. - NEON3SameFHMMask = 0xBFE0FC00u, // U size opcode - NEON_FMLAL = NEON3SameFixed | 0x0000E800u, // 0 00 11101 - NEON_FMLAL2 = NEON3SameFixed | 0x2000C800u, // 1 00 11001 - NEON_FMLSL = NEON3SameFixed | 0x0080E800u, // 0 10 11101 - NEON_FMLSL2 = NEON3SameFixed | 0x2080C800u // 1 10 11001 + NEON3SameFHMMask = 0xBFE0FC00, // U size opcode + NEON_FMLAL = NEON3SameFixed | 0x0000E800, // 0 00 11101 + NEON_FMLAL2 = NEON3SameFixed | 0x2000C800, // 1 00 11001 + NEON_FMLSL = NEON3SameFixed | 0x0080E800, // 0 10 11101 + NEON_FMLSL2 = NEON3SameFixed | 0x2080C800 // 1 10 11001 }; enum NEON3SameFP16 : uint32_t { - NEON3SameFP16Fixed = 0x0E400400u, - NEON3SameFP16FMask = 0x9F60C400u, - NEON3SameFP16Mask = 0xBFE0FC00u, - NEON_FMAXNM_H = NEON3SameFP16Fixed | 0x00000000u, - NEON_FMLA_H = NEON3SameFP16Fixed | 0x00000800u, - NEON_FADD_H = NEON3SameFP16Fixed | 0x00001000u, - NEON_FMULX_H = NEON3SameFP16Fixed | 0x00001800u, - NEON_FCMEQ_H = NEON3SameFP16Fixed | 0x00002000u, - NEON_FMAX_H = NEON3SameFP16Fixed | 0x00003000u, - NEON_FRECPS_H = NEON3SameFP16Fixed | 0x00003800u, - NEON_FMINNM_H = NEON3SameFP16Fixed | 0x00800000u, - NEON_FMLS_H = NEON3SameFP16Fixed | 0x00800800u, - NEON_FSUB_H = NEON3SameFP16Fixed | 0x00801000u, - NEON_FMIN_H = NEON3SameFP16Fixed | 0x00803000u, - NEON_FRSQRTS_H = NEON3SameFP16Fixed | 0x00803800u, - NEON_FMAXNMP_H = NEON3SameFP16Fixed | 0x20000000u, - NEON_FADDP_H = NEON3SameFP16Fixed | 0x20001000u, - NEON_FMUL_H = NEON3SameFP16Fixed | 0x20001800u, - NEON_FCMGE_H = NEON3SameFP16Fixed | 0x20002000u, - NEON_FACGE_H = NEON3SameFP16Fixed | 0x20002800u, - NEON_FMAXP_H = NEON3SameFP16Fixed | 0x20003000u, - NEON_FDIV_H = NEON3SameFP16Fixed | 0x20003800u, - NEON_FMINNMP_H = NEON3SameFP16Fixed | 0x20800000u, - NEON_FABD_H = NEON3SameFP16Fixed | 0x20801000u, - NEON_FCMGT_H = NEON3SameFP16Fixed | 0x20802000u, - NEON_FACGT_H = NEON3SameFP16Fixed | 0x20802800u, - NEON_FMINP_H = NEON3SameFP16Fixed | 0x20803000u + NEON3SameFP16Fixed = 0x0E400400, + NEON3SameFP16FMask = 0x9F60C400, + NEON3SameFP16Mask = 0xBFE0FC00, + NEON_FMAXNM_H = NEON3SameFP16Fixed | 0x00000000, + NEON_FMLA_H = NEON3SameFP16Fixed | 0x00000800, + NEON_FADD_H = NEON3SameFP16Fixed | 0x00001000, + NEON_FMULX_H = NEON3SameFP16Fixed | 0x00001800, + NEON_FCMEQ_H = NEON3SameFP16Fixed | 0x00002000, + NEON_FMAX_H = NEON3SameFP16Fixed | 0x00003000, + NEON_FRECPS_H = NEON3SameFP16Fixed | 0x00003800, + NEON_FMINNM_H = NEON3SameFP16Fixed | 0x00800000, + NEON_FMLS_H = NEON3SameFP16Fixed | 0x00800800, + NEON_FSUB_H = NEON3SameFP16Fixed | 0x00801000, + NEON_FMIN_H = NEON3SameFP16Fixed | 0x00803000, + NEON_FRSQRTS_H = NEON3SameFP16Fixed | 0x00803800, + NEON_FMAXNMP_H = NEON3SameFP16Fixed | 0x20000000, + NEON_FADDP_H = NEON3SameFP16Fixed | 0x20001000, + NEON_FMUL_H = NEON3SameFP16Fixed | 0x20001800, + NEON_FCMGE_H = NEON3SameFP16Fixed | 0x20002000, + NEON_FACGE_H = NEON3SameFP16Fixed | 0x20002800, + NEON_FMAXP_H = NEON3SameFP16Fixed | 0x20003000, + NEON_FDIV_H = NEON3SameFP16Fixed | 0x20003800, + NEON_FMINNMP_H = NEON3SameFP16Fixed | 0x20800000, + NEON_FABD_H = NEON3SameFP16Fixed | 0x20801000, + NEON_FCMGT_H = NEON3SameFP16Fixed | 0x20802000, + NEON_FACGT_H = NEON3SameFP16Fixed | 0x20802800, + NEON_FMINP_H = NEON3SameFP16Fixed | 0x20803000 }; // 'Extra' NEON instructions with three same-type operands. enum NEON3SameExtraOp : uint32_t { - NEON3SameExtraFixed = 0x0E008400u, - NEON3SameExtraUBit = 0x20000000u, - NEON3SameExtraFMask = 0x9E208400u, - NEON3SameExtraMask = 0xBE20FC00u, + NEON3SameExtraFixed = 0x0E008400, + NEON3SameExtraUBit = 0x20000000, + NEON3SameExtraFMask = 0x9E208400, + NEON3SameExtraMask = 0xBE20FC00, NEON_SQRDMLAH = NEON3SameExtraFixed | NEON3SameExtraUBit, - NEON_SQRDMLSH = NEON3SameExtraFixed | NEON3SameExtraUBit | 0x00000800u, - NEON_SDOT = NEON3SameExtraFixed | 0x00001000u, - NEON_UDOT = NEON3SameExtraFixed | NEON3SameExtraUBit | 0x00001000u, + NEON_SQRDMLSH = NEON3SameExtraFixed | NEON3SameExtraUBit | 0x00000800, + NEON_SDOT = NEON3SameExtraFixed | 0x00001000, + NEON_UDOT = NEON3SameExtraFixed | NEON3SameExtraUBit | 0x00001000, /* v8.3 Complex Numbers */ - NEON3SameExtraFCFixed = 0x2E00C400u, - NEON3SameExtraFCFMask = 0xBF20C400u, + NEON3SameExtraFCFixed = 0x2E00C400, + NEON3SameExtraFCFMask = 0xBF20C400, // FCMLA fixes opcode<3:2>, and uses opcode<1:0> to encode . - NEON3SameExtraFCMLAMask = NEON3SameExtraFCFMask | 0x00006000u, + NEON3SameExtraFCMLAMask = NEON3SameExtraFCFMask | 0x00006000, NEON_FCMLA = NEON3SameExtraFCFixed, // FCADD fixes opcode<3:2, 0>, and uses opcode<1> to encode . - NEON3SameExtraFCADDMask = NEON3SameExtraFCFMask | 0x00006800u, - NEON_FCADD = NEON3SameExtraFCFixed | 0x00002000u + NEON3SameExtraFCADDMask = NEON3SameExtraFCFMask | 0x00006800, + NEON_FCADD = NEON3SameExtraFCFixed | 0x00002000 // Other encodings under NEON3SameExtraFCFMask are UNALLOCATED. }; // NEON instructions with three different-type operands. enum NEON3DifferentOp : uint32_t { - NEON3DifferentFixed = 0x0E200000u, - NEON3DifferentFMask = 0x9F200C00u, - NEON3DifferentMask = 0xFF20FC00u, - NEON_ADDHN = NEON3DifferentFixed | 0x00004000u, + NEON3DifferentFixed = 0x0E200000, + NEON3DifferentFMask = 0x9F200C00, + NEON3DifferentMask = 0xFF20FC00, + NEON_ADDHN = NEON3DifferentFixed | 0x00004000, NEON_ADDHN2 = NEON_ADDHN | NEON_Q, - NEON_PMULL = NEON3DifferentFixed | 0x0000E000u, + NEON_PMULL = NEON3DifferentFixed | 0x0000E000, NEON_PMULL2 = NEON_PMULL | NEON_Q, - NEON_RADDHN = NEON3DifferentFixed | 0x20004000u, + NEON_RADDHN = NEON3DifferentFixed | 0x20004000, NEON_RADDHN2 = NEON_RADDHN | NEON_Q, - NEON_RSUBHN = NEON3DifferentFixed | 0x20006000u, + NEON_RSUBHN = NEON3DifferentFixed | 0x20006000, NEON_RSUBHN2 = NEON_RSUBHN | NEON_Q, - NEON_SABAL = NEON3DifferentFixed | 0x00005000u, + NEON_SABAL = NEON3DifferentFixed | 0x00005000, NEON_SABAL2 = NEON_SABAL | NEON_Q, - NEON_SABDL = NEON3DifferentFixed | 0x00007000u, + NEON_SABDL = NEON3DifferentFixed | 0x00007000, NEON_SABDL2 = NEON_SABDL | NEON_Q, - NEON_SADDL = NEON3DifferentFixed | 0x00000000u, + NEON_SADDL = NEON3DifferentFixed | 0x00000000, NEON_SADDL2 = NEON_SADDL | NEON_Q, - NEON_SADDW = NEON3DifferentFixed | 0x00001000u, + NEON_SADDW = NEON3DifferentFixed | 0x00001000, NEON_SADDW2 = NEON_SADDW | NEON_Q, - NEON_SMLAL = NEON3DifferentFixed | 0x00008000u, + NEON_SMLAL = NEON3DifferentFixed | 0x00008000, NEON_SMLAL2 = NEON_SMLAL | NEON_Q, - NEON_SMLSL = NEON3DifferentFixed | 0x0000A000u, + NEON_SMLSL = NEON3DifferentFixed | 0x0000A000, NEON_SMLSL2 = NEON_SMLSL | NEON_Q, - NEON_SMULL = NEON3DifferentFixed | 0x0000C000u, + NEON_SMULL = NEON3DifferentFixed | 0x0000C000, NEON_SMULL2 = NEON_SMULL | NEON_Q, - NEON_SSUBL = NEON3DifferentFixed | 0x00002000u, + NEON_SSUBL = NEON3DifferentFixed | 0x00002000, NEON_SSUBL2 = NEON_SSUBL | NEON_Q, - NEON_SSUBW = NEON3DifferentFixed | 0x00003000u, + NEON_SSUBW = NEON3DifferentFixed | 0x00003000, NEON_SSUBW2 = NEON_SSUBW | NEON_Q, - NEON_SQDMLAL = NEON3DifferentFixed | 0x00009000u, + NEON_SQDMLAL = NEON3DifferentFixed | 0x00009000, NEON_SQDMLAL2 = NEON_SQDMLAL | NEON_Q, - NEON_SQDMLSL = NEON3DifferentFixed | 0x0000B000u, + NEON_SQDMLSL = NEON3DifferentFixed | 0x0000B000, NEON_SQDMLSL2 = NEON_SQDMLSL | NEON_Q, - NEON_SQDMULL = NEON3DifferentFixed | 0x0000D000u, + NEON_SQDMULL = NEON3DifferentFixed | 0x0000D000, NEON_SQDMULL2 = NEON_SQDMULL | NEON_Q, - NEON_SUBHN = NEON3DifferentFixed | 0x00006000u, + NEON_SUBHN = NEON3DifferentFixed | 0x00006000, NEON_SUBHN2 = NEON_SUBHN | NEON_Q, NEON_UABAL = NEON_SABAL | NEON3SameUBit, NEON_UABAL2 = NEON_UABAL | NEON_Q, @@ -2197,133 +2206,133 @@ enum NEON3DifferentOp : uint32_t { // NEON instructions operating across vectors. enum NEONAcrossLanesOp : uint32_t { - NEONAcrossLanesFixed = 0x0E300800u, - NEONAcrossLanesFMask = 0x9F3E0C00u, - NEONAcrossLanesMask = 0xBF3FFC00u, - NEON_ADDV = NEONAcrossLanesFixed | 0x0001B000u, - NEON_SADDLV = NEONAcrossLanesFixed | 0x00003000u, - NEON_UADDLV = NEONAcrossLanesFixed | 0x20003000u, - NEON_SMAXV = NEONAcrossLanesFixed | 0x0000A000u, - NEON_SMINV = NEONAcrossLanesFixed | 0x0001A000u, - NEON_UMAXV = NEONAcrossLanesFixed | 0x2000A000u, - NEON_UMINV = NEONAcrossLanesFixed | 0x2001A000u, + NEONAcrossLanesFixed = 0x0E300800, + NEONAcrossLanesFMask = 0x9F3E0C00, + NEONAcrossLanesMask = 0xBF3FFC00, + NEON_ADDV = NEONAcrossLanesFixed | 0x0001B000, + NEON_SADDLV = NEONAcrossLanesFixed | 0x00003000, + NEON_UADDLV = NEONAcrossLanesFixed | 0x20003000, + NEON_SMAXV = NEONAcrossLanesFixed | 0x0000A000, + NEON_SMINV = NEONAcrossLanesFixed | 0x0001A000, + NEON_UMAXV = NEONAcrossLanesFixed | 0x2000A000, + NEON_UMINV = NEONAcrossLanesFixed | 0x2001A000, - NEONAcrossLanesFP16Fixed = NEONAcrossLanesFixed | 0x0000C000u, - NEONAcrossLanesFP16FMask = NEONAcrossLanesFMask | 0x2000C000u, - NEONAcrossLanesFP16Mask = NEONAcrossLanesMask | 0x20800000u, - NEON_FMAXNMV_H = NEONAcrossLanesFP16Fixed | 0x00000000u, - NEON_FMAXV_H = NEONAcrossLanesFP16Fixed | 0x00003000u, - NEON_FMINNMV_H = NEONAcrossLanesFP16Fixed | 0x00800000u, - NEON_FMINV_H = NEONAcrossLanesFP16Fixed | 0x00803000u, + NEONAcrossLanesFP16Fixed = NEONAcrossLanesFixed | 0x0000C000, + NEONAcrossLanesFP16FMask = NEONAcrossLanesFMask | 0x2000C000, + NEONAcrossLanesFP16Mask = NEONAcrossLanesMask | 0x20800000, + NEON_FMAXNMV_H = NEONAcrossLanesFP16Fixed | 0x00000000, + NEON_FMAXV_H = NEONAcrossLanesFP16Fixed | 0x00003000, + NEON_FMINNMV_H = NEONAcrossLanesFP16Fixed | 0x00800000, + NEON_FMINV_H = NEONAcrossLanesFP16Fixed | 0x00803000, // NEON floating point across instructions. - NEONAcrossLanesFPFixed = NEONAcrossLanesFixed | 0x2000C000u, - NEONAcrossLanesFPFMask = NEONAcrossLanesFMask | 0x2000C000u, - NEONAcrossLanesFPMask = NEONAcrossLanesMask | 0x20800000u, + NEONAcrossLanesFPFixed = NEONAcrossLanesFixed | 0x2000C000, + NEONAcrossLanesFPFMask = NEONAcrossLanesFMask | 0x2000C000, + NEONAcrossLanesFPMask = NEONAcrossLanesMask | 0x20800000, - NEON_FMAXV = NEONAcrossLanesFPFixed | 0x2000F000u, - NEON_FMINV = NEONAcrossLanesFPFixed | 0x2080F000u, - NEON_FMAXNMV = NEONAcrossLanesFPFixed | 0x2000C000u, - NEON_FMINNMV = NEONAcrossLanesFPFixed | 0x2080C000u + NEON_FMAXV = NEONAcrossLanesFPFixed | 0x2000F000, + NEON_FMINV = NEONAcrossLanesFPFixed | 0x2080F000, + NEON_FMAXNMV = NEONAcrossLanesFPFixed | 0x2000C000, + NEON_FMINNMV = NEONAcrossLanesFPFixed | 0x2080C000 }; // NEON instructions with indexed element operand. enum NEONByIndexedElementOp : uint32_t { - NEONByIndexedElementFixed = 0x0F000000u, - NEONByIndexedElementFMask = 0x9F000400u, - NEONByIndexedElementMask = 0xBF00F400u, - NEON_MUL_byelement = NEONByIndexedElementFixed | 0x00008000u, - NEON_MLA_byelement = NEONByIndexedElementFixed | 0x20000000u, - NEON_MLS_byelement = NEONByIndexedElementFixed | 0x20004000u, - NEON_SMULL_byelement = NEONByIndexedElementFixed | 0x0000A000u, - NEON_SMLAL_byelement = NEONByIndexedElementFixed | 0x00002000u, - NEON_SMLSL_byelement = NEONByIndexedElementFixed | 0x00006000u, - NEON_UMULL_byelement = NEONByIndexedElementFixed | 0x2000A000u, - NEON_UMLAL_byelement = NEONByIndexedElementFixed | 0x20002000u, - NEON_UMLSL_byelement = NEONByIndexedElementFixed | 0x20006000u, - NEON_SQDMULL_byelement = NEONByIndexedElementFixed | 0x0000B000u, - NEON_SQDMLAL_byelement = NEONByIndexedElementFixed | 0x00003000u, - NEON_SQDMLSL_byelement = NEONByIndexedElementFixed | 0x00007000u, - NEON_SQDMULH_byelement = NEONByIndexedElementFixed | 0x0000C000u, - NEON_SQRDMULH_byelement = NEONByIndexedElementFixed | 0x0000D000u, - NEON_SDOT_byelement = NEONByIndexedElementFixed | 0x0000E000u, - NEON_SQRDMLAH_byelement = NEONByIndexedElementFixed | 0x2000D000u, - NEON_UDOT_byelement = NEONByIndexedElementFixed | 0x2000E000u, - NEON_SQRDMLSH_byelement = NEONByIndexedElementFixed | 0x2000F000u, + NEONByIndexedElementFixed = 0x0F000000, + NEONByIndexedElementFMask = 0x9F000400, + NEONByIndexedElementMask = 0xBF00F400, + NEON_MUL_byelement = NEONByIndexedElementFixed | 0x00008000, + NEON_MLA_byelement = NEONByIndexedElementFixed | 0x20000000, + NEON_MLS_byelement = NEONByIndexedElementFixed | 0x20004000, + NEON_SMULL_byelement = NEONByIndexedElementFixed | 0x0000A000, + NEON_SMLAL_byelement = NEONByIndexedElementFixed | 0x00002000, + NEON_SMLSL_byelement = NEONByIndexedElementFixed | 0x00006000, + NEON_UMULL_byelement = NEONByIndexedElementFixed | 0x2000A000, + NEON_UMLAL_byelement = NEONByIndexedElementFixed | 0x20002000, + NEON_UMLSL_byelement = NEONByIndexedElementFixed | 0x20006000, + NEON_SQDMULL_byelement = NEONByIndexedElementFixed | 0x0000B000, + NEON_SQDMLAL_byelement = NEONByIndexedElementFixed | 0x00003000, + NEON_SQDMLSL_byelement = NEONByIndexedElementFixed | 0x00007000, + NEON_SQDMULH_byelement = NEONByIndexedElementFixed | 0x0000C000, + NEON_SQRDMULH_byelement = NEONByIndexedElementFixed | 0x0000D000, + NEON_SDOT_byelement = NEONByIndexedElementFixed | 0x0000E000, + NEON_SQRDMLAH_byelement = NEONByIndexedElementFixed | 0x2000D000, + NEON_UDOT_byelement = NEONByIndexedElementFixed | 0x2000E000, + NEON_SQRDMLSH_byelement = NEONByIndexedElementFixed | 0x2000F000, - NEON_FMLA_H_byelement = NEONByIndexedElementFixed | 0x00001000u, - NEON_FMLS_H_byelement = NEONByIndexedElementFixed | 0x00005000u, - NEON_FMUL_H_byelement = NEONByIndexedElementFixed | 0x00009000u, - NEON_FMULX_H_byelement = NEONByIndexedElementFixed | 0x20009000u, + NEON_FMLA_H_byelement = NEONByIndexedElementFixed | 0x00001000, + NEON_FMLS_H_byelement = NEONByIndexedElementFixed | 0x00005000, + NEON_FMUL_H_byelement = NEONByIndexedElementFixed | 0x00009000, + NEON_FMULX_H_byelement = NEONByIndexedElementFixed | 0x20009000, // Floating point instructions. - NEONByIndexedElementFPFixed = NEONByIndexedElementFixed | 0x00800000u, - NEONByIndexedElementFPMask = NEONByIndexedElementMask | 0x00800000u, - NEON_FMLA_byelement = NEONByIndexedElementFPFixed | 0x00001000u, - NEON_FMLS_byelement = NEONByIndexedElementFPFixed | 0x00005000u, - NEON_FMUL_byelement = NEONByIndexedElementFPFixed | 0x00009000u, - NEON_FMULX_byelement = NEONByIndexedElementFPFixed | 0x20009000u, + NEONByIndexedElementFPFixed = NEONByIndexedElementFixed | 0x00800000, + NEONByIndexedElementFPMask = NEONByIndexedElementMask | 0x00800000, + NEON_FMLA_byelement = NEONByIndexedElementFPFixed | 0x00001000, + NEON_FMLS_byelement = NEONByIndexedElementFPFixed | 0x00005000, + NEON_FMUL_byelement = NEONByIndexedElementFPFixed | 0x00009000, + NEON_FMULX_byelement = NEONByIndexedElementFPFixed | 0x20009000, // FMLAL-like instructions. // For all cases: U = x, size = 10, opcode = xx00 - NEONByIndexedElementFPLongFixed = NEONByIndexedElementFixed | 0x00800000u, - NEONByIndexedElementFPLongFMask = NEONByIndexedElementFMask | 0x00C03000u, - NEONByIndexedElementFPLongMask = 0xBFC0F400u, - NEON_FMLAL_H_byelement = NEONByIndexedElementFixed | 0x00800000u, - NEON_FMLAL2_H_byelement = NEONByIndexedElementFixed | 0x20808000u, - NEON_FMLSL_H_byelement = NEONByIndexedElementFixed | 0x00804000u, - NEON_FMLSL2_H_byelement = NEONByIndexedElementFixed | 0x2080C000u, + NEONByIndexedElementFPLongFixed = NEONByIndexedElementFixed | 0x00800000, + NEONByIndexedElementFPLongFMask = NEONByIndexedElementFMask | 0x00C03000, + NEONByIndexedElementFPLongMask = 0xBFC0F400, + NEON_FMLAL_H_byelement = NEONByIndexedElementFixed | 0x00800000, + NEON_FMLAL2_H_byelement = NEONByIndexedElementFixed | 0x20808000, + NEON_FMLSL_H_byelement = NEONByIndexedElementFixed | 0x00804000, + NEON_FMLSL2_H_byelement = NEONByIndexedElementFixed | 0x2080C000, // Complex instruction(s). // This is necessary because the 'rot' encoding moves into the // NEONByIndex..Mask space. - NEONByIndexedElementFPComplexMask = 0xBF009400u, - NEON_FCMLA_byelement = NEONByIndexedElementFixed | 0x20001000u + NEONByIndexedElementFPComplexMask = 0xBF009400, + NEON_FCMLA_byelement = NEONByIndexedElementFixed | 0x20001000 }; // NEON register copy. enum NEONCopyOp : uint32_t { - NEONCopyFixed = 0x0E000400u, - NEONCopyFMask = 0x9FE08400u, - NEONCopyMask = 0x3FE08400u, - NEONCopyInsElementMask = NEONCopyMask | 0x40000000u, - NEONCopyInsGeneralMask = NEONCopyMask | 0x40007800u, - NEONCopyDupElementMask = NEONCopyMask | 0x20007800u, + NEONCopyFixed = 0x0E000400, + NEONCopyFMask = 0x9FE08400, + NEONCopyMask = 0x3FE08400, + NEONCopyInsElementMask = NEONCopyMask | 0x40000000, + NEONCopyInsGeneralMask = NEONCopyMask | 0x40007800, + NEONCopyDupElementMask = NEONCopyMask | 0x20007800, NEONCopyDupGeneralMask = NEONCopyDupElementMask, - NEONCopyUmovMask = NEONCopyMask | 0x20007800u, - NEONCopySmovMask = NEONCopyMask | 0x20007800u, - NEON_INS_ELEMENT = NEONCopyFixed | 0x60000000u, - NEON_INS_GENERAL = NEONCopyFixed | 0x40001800u, - NEON_DUP_ELEMENT = NEONCopyFixed | 0x00000000u, - NEON_DUP_GENERAL = NEONCopyFixed | 0x00000800u, - NEON_SMOV = NEONCopyFixed | 0x00002800u, - NEON_UMOV = NEONCopyFixed | 0x00003800u + NEONCopyUmovMask = NEONCopyMask | 0x20007800, + NEONCopySmovMask = NEONCopyMask | 0x20007800, + NEON_INS_ELEMENT = NEONCopyFixed | 0x60000000, + NEON_INS_GENERAL = NEONCopyFixed | 0x40001800, + NEON_DUP_ELEMENT = NEONCopyFixed | 0x00000000, + NEON_DUP_GENERAL = NEONCopyFixed | 0x00000800, + NEON_SMOV = NEONCopyFixed | 0x00002800, + NEON_UMOV = NEONCopyFixed | 0x00003800 }; // NEON extract. enum NEONExtractOp : uint32_t { - NEONExtractFixed = 0x2E000000u, - NEONExtractFMask = 0xBF208400u, - NEONExtractMask = 0xBFE08400u, - NEON_EXT = NEONExtractFixed | 0x00000000u + NEONExtractFixed = 0x2E000000, + NEONExtractFMask = 0xBF208400, + NEONExtractMask = 0xBFE08400, + NEON_EXT = NEONExtractFixed | 0x00000000 }; enum NEONLoadStoreMultiOp : uint32_t { - NEONLoadStoreMultiL = 0x00400000u, - NEONLoadStoreMulti1_1v = 0x00007000u, - NEONLoadStoreMulti1_2v = 0x0000A000u, - NEONLoadStoreMulti1_3v = 0x00006000u, - NEONLoadStoreMulti1_4v = 0x00002000u, - NEONLoadStoreMulti2 = 0x00008000u, - NEONLoadStoreMulti3 = 0x00004000u, - NEONLoadStoreMulti4 = 0x00000000u + NEONLoadStoreMultiL = 0x00400000, + NEONLoadStoreMulti1_1v = 0x00007000, + NEONLoadStoreMulti1_2v = 0x0000A000, + NEONLoadStoreMulti1_3v = 0x00006000, + NEONLoadStoreMulti1_4v = 0x00002000, + NEONLoadStoreMulti2 = 0x00008000, + NEONLoadStoreMulti3 = 0x00004000, + NEONLoadStoreMulti4 = 0x00000000 }; // NEON load/store multiple structures. enum NEONLoadStoreMultiStructOp : uint32_t { - NEONLoadStoreMultiStructFixed = 0x0C000000u, - NEONLoadStoreMultiStructFMask = 0xBFBF0000u, - NEONLoadStoreMultiStructMask = 0xBFFFF000u, + NEONLoadStoreMultiStructFixed = 0x0C000000, + NEONLoadStoreMultiStructFMask = 0xBFBF0000, + NEONLoadStoreMultiStructMask = 0xBFFFF000, NEONLoadStoreMultiStructStore = NEONLoadStoreMultiStructFixed, NEONLoadStoreMultiStructLoad = NEONLoadStoreMultiStructFixed | NEONLoadStoreMultiL, @@ -2345,10 +2354,10 @@ enum NEONLoadStoreMultiStructOp : uint32_t { // NEON load/store multiple structures with post-index addressing. enum NEONLoadStoreMultiStructPostIndexOp : uint32_t { - NEONLoadStoreMultiStructPostIndexFixed = 0x0C800000u, - NEONLoadStoreMultiStructPostIndexFMask = 0xBFA00000u, - NEONLoadStoreMultiStructPostIndexMask = 0xBFE0F000u, - NEONLoadStoreMultiStructPostIndex = 0x00800000u, + NEONLoadStoreMultiStructPostIndexFixed = 0x0C800000, + NEONLoadStoreMultiStructPostIndexFMask = 0xBFA00000, + NEONLoadStoreMultiStructPostIndexMask = 0xBFE0F000, + NEONLoadStoreMultiStructPostIndex = 0x00800000, NEON_LD1_1v_post = NEON_LD1_1v | NEONLoadStoreMultiStructPostIndex, NEON_LD1_2v_post = NEON_LD1_2v | NEONLoadStoreMultiStructPostIndex, NEON_LD1_3v_post = NEON_LD1_3v | NEONLoadStoreMultiStructPostIndex, @@ -2366,24 +2375,24 @@ enum NEONLoadStoreMultiStructPostIndexOp : uint32_t { }; enum NEONLoadStoreSingleOp : uint32_t { - NEONLoadStoreSingle1 = 0x00000000u, - NEONLoadStoreSingle2 = 0x00200000u, - NEONLoadStoreSingle3 = 0x00002000u, - NEONLoadStoreSingle4 = 0x00202000u, - NEONLoadStoreSingleL = 0x00400000u, - NEONLoadStoreSingle_b = 0x00000000u, - NEONLoadStoreSingle_h = 0x00004000u, - NEONLoadStoreSingle_s = 0x00008000u, - NEONLoadStoreSingle_d = 0x00008400u, - NEONLoadStoreSingleAllLanes = 0x0000C000u, - NEONLoadStoreSingleLenMask = 0x00202000u + NEONLoadStoreSingle1 = 0x00000000, + NEONLoadStoreSingle2 = 0x00200000, + NEONLoadStoreSingle3 = 0x00002000, + NEONLoadStoreSingle4 = 0x00202000, + NEONLoadStoreSingleL = 0x00400000, + NEONLoadStoreSingle_b = 0x00000000, + NEONLoadStoreSingle_h = 0x00004000, + NEONLoadStoreSingle_s = 0x00008000, + NEONLoadStoreSingle_d = 0x00008400, + NEONLoadStoreSingleAllLanes = 0x0000C000, + NEONLoadStoreSingleLenMask = 0x00202000 }; // NEON load/store single structure. enum NEONLoadStoreSingleStructOp : uint32_t { - NEONLoadStoreSingleStructFixed = 0x0D000000u, - NEONLoadStoreSingleStructFMask = 0xBF9F0000u, - NEONLoadStoreSingleStructMask = 0xBFFFE000u, + NEONLoadStoreSingleStructFixed = 0x0D000000, + NEONLoadStoreSingleStructFMask = 0xBF9F0000, + NEONLoadStoreSingleStructMask = 0xBFFFE000, NEONLoadStoreSingleStructStore = NEONLoadStoreSingleStructFixed, NEONLoadStoreSingleStructLoad = NEONLoadStoreSingleStructFixed | NEONLoadStoreSingleL, @@ -2446,10 +2455,10 @@ enum NEONLoadStoreSingleStructOp : uint32_t { // NEON load/store single structure with post-index addressing. enum NEONLoadStoreSingleStructPostIndexOp : uint32_t { - NEONLoadStoreSingleStructPostIndexFixed = 0x0D800000u, - NEONLoadStoreSingleStructPostIndexFMask = 0xBF800000u, - NEONLoadStoreSingleStructPostIndexMask = 0xBFE0E000u, - NEONLoadStoreSingleStructPostIndex = 0x00800000u, + NEONLoadStoreSingleStructPostIndexFixed = 0x0D800000, + NEONLoadStoreSingleStructPostIndexFMask = 0xBF800000, + NEONLoadStoreSingleStructPostIndexMask = 0xBFE0E000, + NEONLoadStoreSingleStructPostIndex = 0x00800000, NEON_LD1_b_post = NEON_LD1_b | NEONLoadStoreSingleStructPostIndex, NEON_LD1_h_post = NEON_LD1_h | NEONLoadStoreSingleStructPostIndex, NEON_LD1_s_post = NEON_LD1_s | NEONLoadStoreSingleStructPostIndex, @@ -2493,62 +2502,62 @@ enum NEONLoadStoreSingleStructPostIndexOp : uint32_t { // NEON modified immediate. enum NEONModifiedImmediateOp : uint32_t { - NEONModifiedImmediateFixed = 0x0F000400u, - NEONModifiedImmediateFMask = 0x9FF80400u, - NEONModifiedImmediateOpBit = 0x20000000u, - NEONModifiedImmediate_FMOV = NEONModifiedImmediateFixed | 0x00000800u, - NEONModifiedImmediate_MOVI = NEONModifiedImmediateFixed | 0x00000000u, - NEONModifiedImmediate_MVNI = NEONModifiedImmediateFixed | 0x20000000u, - NEONModifiedImmediate_ORR = NEONModifiedImmediateFixed | 0x00001000u, - NEONModifiedImmediate_BIC = NEONModifiedImmediateFixed | 0x20001000u + NEONModifiedImmediateFixed = 0x0F000400, + NEONModifiedImmediateFMask = 0x9FF80400, + NEONModifiedImmediateOpBit = 0x20000000, + NEONModifiedImmediate_FMOV = NEONModifiedImmediateFixed | 0x00000800, + NEONModifiedImmediate_MOVI = NEONModifiedImmediateFixed | 0x00000000, + NEONModifiedImmediate_MVNI = NEONModifiedImmediateFixed | 0x20000000, + NEONModifiedImmediate_ORR = NEONModifiedImmediateFixed | 0x00001000, + NEONModifiedImmediate_BIC = NEONModifiedImmediateFixed | 0x20001000 }; // NEON shift immediate. enum NEONShiftImmediateOp : uint32_t { - NEONShiftImmediateFixed = 0x0F000400u, - NEONShiftImmediateFMask = 0x9F800400u, - NEONShiftImmediateMask = 0xBF80FC00u, - NEONShiftImmediateUBit = 0x20000000u, - NEON_SHL = NEONShiftImmediateFixed | 0x00005000u, - NEON_SSHLL = NEONShiftImmediateFixed | 0x0000A000u, - NEON_USHLL = NEONShiftImmediateFixed | 0x2000A000u, - NEON_SLI = NEONShiftImmediateFixed | 0x20005000u, - NEON_SRI = NEONShiftImmediateFixed | 0x20004000u, - NEON_SHRN = NEONShiftImmediateFixed | 0x00008000u, - NEON_RSHRN = NEONShiftImmediateFixed | 0x00008800u, - NEON_UQSHRN = NEONShiftImmediateFixed | 0x20009000u, - NEON_UQRSHRN = NEONShiftImmediateFixed | 0x20009800u, - NEON_SQSHRN = NEONShiftImmediateFixed | 0x00009000u, - NEON_SQRSHRN = NEONShiftImmediateFixed | 0x00009800u, - NEON_SQSHRUN = NEONShiftImmediateFixed | 0x20008000u, - NEON_SQRSHRUN = NEONShiftImmediateFixed | 0x20008800u, - NEON_SSHR = NEONShiftImmediateFixed | 0x00000000u, - NEON_SRSHR = NEONShiftImmediateFixed | 0x00002000u, - NEON_USHR = NEONShiftImmediateFixed | 0x20000000u, - NEON_URSHR = NEONShiftImmediateFixed | 0x20002000u, - NEON_SSRA = NEONShiftImmediateFixed | 0x00001000u, - NEON_SRSRA = NEONShiftImmediateFixed | 0x00003000u, - NEON_USRA = NEONShiftImmediateFixed | 0x20001000u, - NEON_URSRA = NEONShiftImmediateFixed | 0x20003000u, - NEON_SQSHLU = NEONShiftImmediateFixed | 0x20006000u, - NEON_SCVTF_imm = NEONShiftImmediateFixed | 0x0000E000u, - NEON_UCVTF_imm = NEONShiftImmediateFixed | 0x2000E000u, - NEON_FCVTZS_imm = NEONShiftImmediateFixed | 0x0000F800u, - NEON_FCVTZU_imm = NEONShiftImmediateFixed | 0x2000F800u, - NEON_SQSHL_imm = NEONShiftImmediateFixed | 0x00007000u, - NEON_UQSHL_imm = NEONShiftImmediateFixed | 0x20007000u + NEONShiftImmediateFixed = 0x0F000400, + NEONShiftImmediateFMask = 0x9F800400, + NEONShiftImmediateMask = 0xBF80FC00, + NEONShiftImmediateUBit = 0x20000000, + NEON_SHL = NEONShiftImmediateFixed | 0x00005000, + NEON_SSHLL = NEONShiftImmediateFixed | 0x0000A000, + NEON_USHLL = NEONShiftImmediateFixed | 0x2000A000, + NEON_SLI = NEONShiftImmediateFixed | 0x20005000, + NEON_SRI = NEONShiftImmediateFixed | 0x20004000, + NEON_SHRN = NEONShiftImmediateFixed | 0x00008000, + NEON_RSHRN = NEONShiftImmediateFixed | 0x00008800, + NEON_UQSHRN = NEONShiftImmediateFixed | 0x20009000, + NEON_UQRSHRN = NEONShiftImmediateFixed | 0x20009800, + NEON_SQSHRN = NEONShiftImmediateFixed | 0x00009000, + NEON_SQRSHRN = NEONShiftImmediateFixed | 0x00009800, + NEON_SQSHRUN = NEONShiftImmediateFixed | 0x20008000, + NEON_SQRSHRUN = NEONShiftImmediateFixed | 0x20008800, + NEON_SSHR = NEONShiftImmediateFixed | 0x00000000, + NEON_SRSHR = NEONShiftImmediateFixed | 0x00002000, + NEON_USHR = NEONShiftImmediateFixed | 0x20000000, + NEON_URSHR = NEONShiftImmediateFixed | 0x20002000, + NEON_SSRA = NEONShiftImmediateFixed | 0x00001000, + NEON_SRSRA = NEONShiftImmediateFixed | 0x00003000, + NEON_USRA = NEONShiftImmediateFixed | 0x20001000, + NEON_URSRA = NEONShiftImmediateFixed | 0x20003000, + NEON_SQSHLU = NEONShiftImmediateFixed | 0x20006000, + NEON_SCVTF_imm = NEONShiftImmediateFixed | 0x0000E000, + NEON_UCVTF_imm = NEONShiftImmediateFixed | 0x2000E000, + NEON_FCVTZS_imm = NEONShiftImmediateFixed | 0x0000F800, + NEON_FCVTZU_imm = NEONShiftImmediateFixed | 0x2000F800, + NEON_SQSHL_imm = NEONShiftImmediateFixed | 0x00007000, + NEON_UQSHL_imm = NEONShiftImmediateFixed | 0x20007000 }; // NEON table. enum NEONTableOp : uint32_t { - NEONTableFixed = 0x0E000000u, - NEONTableFMask = 0xBF208C00u, - NEONTableExt = 0x00001000u, - NEONTableMask = 0xBF20FC00u, - NEON_TBL_1v = NEONTableFixed | 0x00000000u, - NEON_TBL_2v = NEONTableFixed | 0x00002000u, - NEON_TBL_3v = NEONTableFixed | 0x00004000u, - NEON_TBL_4v = NEONTableFixed | 0x00006000u, + NEONTableFixed = 0x0E000000, + NEONTableFMask = 0xBF208C00, + NEONTableExt = 0x00001000, + NEONTableMask = 0xBF20FC00, + NEON_TBL_1v = NEONTableFixed | 0x00000000, + NEON_TBL_2v = NEONTableFixed | 0x00002000, + NEON_TBL_3v = NEONTableFixed | 0x00004000, + NEON_TBL_4v = NEONTableFixed | 0x00006000, NEON_TBX_1v = NEON_TBL_1v | NEONTableExt, NEON_TBX_2v = NEON_TBL_2v | NEONTableExt, NEON_TBX_3v = NEON_TBL_3v | NEONTableExt, @@ -2557,21 +2566,21 @@ enum NEONTableOp : uint32_t { // NEON perm. enum NEONPermOp : uint32_t { - NEONPermFixed = 0x0E000800u, - NEONPermFMask = 0xBF208C00u, - NEONPermMask = 0x3F20FC00u, - NEON_UZP1 = NEONPermFixed | 0x00001000u, - NEON_TRN1 = NEONPermFixed | 0x00002000u, - NEON_ZIP1 = NEONPermFixed | 0x00003000u, - NEON_UZP2 = NEONPermFixed | 0x00005000u, - NEON_TRN2 = NEONPermFixed | 0x00006000u, - NEON_ZIP2 = NEONPermFixed | 0x00007000u + NEONPermFixed = 0x0E000800, + NEONPermFMask = 0xBF208C00, + NEONPermMask = 0x3F20FC00, + NEON_UZP1 = NEONPermFixed | 0x00001000, + NEON_TRN1 = NEONPermFixed | 0x00002000, + NEON_ZIP1 = NEONPermFixed | 0x00003000, + NEON_UZP2 = NEONPermFixed | 0x00005000, + NEON_TRN2 = NEONPermFixed | 0x00006000, + NEON_ZIP2 = NEONPermFixed | 0x00007000 }; // NEON scalar instructions with two register operands. enum NEONScalar2RegMiscOp : uint32_t { - NEONScalar2RegMiscFixed = 0x5E200800u, - NEONScalar2RegMiscFMask = 0xDF3E0C00u, + NEONScalar2RegMiscFixed = 0x5E200800, + NEONScalar2RegMiscFMask = 0xDF3E0C00, NEONScalar2RegMiscMask = NEON_Q | NEONScalar | NEON2RegMiscMask, NEON_CMGT_zero_scalar = NEON_Q | NEONScalar | NEON_CMGT_zero, NEON_CMEQ_zero_scalar = NEON_Q | NEONScalar | NEON_CMEQ_zero, @@ -2591,7 +2600,7 @@ enum NEONScalar2RegMiscOp : uint32_t { NEONScalar2RegMiscOpcode = NEON2RegMiscOpcode, NEON_NEG_scalar_opcode = NEON_NEG_scalar & NEONScalar2RegMiscOpcode, - NEONScalar2RegMiscFPMask = NEONScalar2RegMiscMask | 0x00800000u, + NEONScalar2RegMiscFPMask = NEONScalar2RegMiscMask | 0x00800000, NEON_FRSQRTE_scalar = NEON_Q | NEONScalar | NEON_FRSQRTE, NEON_FRECPE_scalar = NEON_Q | NEONScalar | NEON_FRECPE, NEON_SCVTF_scalar = NEON_Q | NEONScalar | NEON_SCVTF, @@ -2601,7 +2610,7 @@ enum NEONScalar2RegMiscOp : uint32_t { NEON_FCMLT_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLT_zero, NEON_FCMGE_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGE_zero, NEON_FCMLE_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLE_zero, - NEON_FRECPX_scalar = NEONScalar2RegMiscFixed | 0x0081F000u, + NEON_FRECPX_scalar = NEONScalar2RegMiscFixed | 0x0081F000, NEON_FCVTNS_scalar = NEON_Q | NEONScalar | NEON_FCVTNS, NEON_FCVTNU_scalar = NEON_Q | NEONScalar | NEON_FCVTNU, NEON_FCVTPS_scalar = NEON_Q | NEONScalar | NEON_FCVTPS, @@ -2617,9 +2626,9 @@ enum NEONScalar2RegMiscOp : uint32_t { // NEON instructions with two register operands (FP16). enum NEONScalar2RegMiscFP16Op : uint32_t { - NEONScalar2RegMiscFP16Fixed = 0x5E780800u, - NEONScalar2RegMiscFP16FMask = 0xDF7E0C00u, - NEONScalar2RegMiscFP16Mask = 0xFFFFFC00u, + NEONScalar2RegMiscFP16Fixed = 0x5E780800, + NEONScalar2RegMiscFP16FMask = 0xDF7E0C00, + NEONScalar2RegMiscFP16Mask = 0xFFFFFC00, NEON_FCVTNS_H_scalar = NEON_Q | NEONScalar | NEON_FCVTNS_H, NEON_FCVTMS_H_scalar = NEON_Q | NEONScalar | NEON_FCVTMS_H, NEON_FCVTAS_H_scalar = NEON_Q | NEONScalar | NEON_FCVTAS_H, @@ -2630,7 +2639,7 @@ enum NEONScalar2RegMiscFP16Op : uint32_t { NEON_FCVTPS_H_scalar = NEON_Q | NEONScalar | NEON_FCVTPS_H, NEON_FCVTZS_H_scalar = NEON_Q | NEONScalar | NEON_FCVTZS_H, NEON_FRECPE_H_scalar = NEON_Q | NEONScalar | NEON_FRECPE_H, - NEON_FRECPX_H_scalar = NEONScalar2RegMiscFP16Fixed | 0x0081F000u, + NEON_FRECPX_H_scalar = NEONScalar2RegMiscFP16Fixed | 0x0081F000, NEON_FCVTNU_H_scalar = NEON_Q | NEONScalar | NEON_FCVTNU_H, NEON_FCVTMU_H_scalar = NEON_Q | NEONScalar | NEON_FCVTMU_H, NEON_FCVTAU_H_scalar = NEON_Q | NEONScalar | NEON_FCVTAU_H, @@ -2644,9 +2653,9 @@ enum NEONScalar2RegMiscFP16Op : uint32_t { // NEON scalar instructions with three same-type operands. enum NEONScalar3SameOp : uint32_t { - NEONScalar3SameFixed = 0x5E200400u, - NEONScalar3SameFMask = 0xDF200400u, - NEONScalar3SameMask = 0xFF20FC00u, + NEONScalar3SameFixed = 0x5E200400, + NEONScalar3SameFMask = 0xDF200400, + NEONScalar3SameMask = 0xFF20FC00, NEON_ADD_scalar = NEON_Q | NEONScalar | NEON_ADD, NEON_CMEQ_scalar = NEON_Q | NEONScalar | NEON_CMEQ, NEON_CMGE_scalar = NEON_Q | NEONScalar | NEON_CMGE, @@ -2671,9 +2680,9 @@ enum NEONScalar3SameOp : uint32_t { NEON_SQRDMULH_scalar = NEON_Q | NEONScalar | NEON_SQRDMULH, // NEON floating point scalar instructions with three same-type operands. - NEONScalar3SameFPFixed = NEONScalar3SameFixed | 0x0000C000u, - NEONScalar3SameFPFMask = NEONScalar3SameFMask | 0x0000C000u, - NEONScalar3SameFPMask = NEONScalar3SameMask | 0x00800000u, + NEONScalar3SameFPFixed = NEONScalar3SameFixed | 0x0000C000, + NEONScalar3SameFPFMask = NEONScalar3SameFMask | 0x0000C000, + NEONScalar3SameFPMask = NEONScalar3SameMask | 0x00800000, NEON_FACGE_scalar = NEON_Q | NEONScalar | NEON_FACGE, NEON_FACGT_scalar = NEON_Q | NEONScalar | NEON_FACGT, NEON_FCMEQ_scalar = NEON_Q | NEONScalar | NEON_FCMEQ, @@ -2687,9 +2696,9 @@ enum NEONScalar3SameOp : uint32_t { // NEON scalar FP16 instructions with three same-type operands. enum NEONScalar3SameFP16Op : uint32_t { - NEONScalar3SameFP16Fixed = 0x5E400400u, - NEONScalar3SameFP16FMask = 0xDF60C400u, - NEONScalar3SameFP16Mask = 0xFFE0FC00u, + NEONScalar3SameFP16Fixed = 0x5E400400, + NEONScalar3SameFP16FMask = 0xDF60C400, + NEONScalar3SameFP16Mask = 0xFFE0FC00, NEON_FABD_H_scalar = NEON_Q | NEONScalar | NEON_FABD_H, NEON_FMULX_H_scalar = NEON_Q | NEONScalar | NEON_FMULX_H, NEON_FCMEQ_H_scalar = NEON_Q | NEONScalar | NEON_FCMEQ_H, @@ -2703,17 +2712,17 @@ enum NEONScalar3SameFP16Op : uint32_t { // 'Extra' NEON scalar instructions with three same-type operands. enum NEONScalar3SameExtraOp : uint32_t { - NEONScalar3SameExtraFixed = 0x5E008400u, - NEONScalar3SameExtraFMask = 0xDF208400u, - NEONScalar3SameExtraMask = 0xFF20FC00u, + NEONScalar3SameExtraFixed = 0x5E008400, + NEONScalar3SameExtraFMask = 0xDF208400, + NEONScalar3SameExtraMask = 0xFF20FC00, NEON_SQRDMLAH_scalar = NEON_Q | NEONScalar | NEON_SQRDMLAH, NEON_SQRDMLSH_scalar = NEON_Q | NEONScalar | NEON_SQRDMLSH }; // NEON scalar instructions with three different-type operands. enum NEONScalar3DiffOp : uint32_t { - NEONScalar3DiffFixed = 0x5E200000u, - NEONScalar3DiffFMask = 0xDF200C00u, + NEONScalar3DiffFixed = 0x5E200000, + NEONScalar3DiffFMask = 0xDF200C00, NEONScalar3DiffMask = NEON_Q | NEONScalar | NEON3DifferentMask, NEON_SQDMLAL_scalar = NEON_Q | NEONScalar | NEON_SQDMLAL, NEON_SQDMLSL_scalar = NEON_Q | NEONScalar | NEON_SQDMLSL, @@ -2722,9 +2731,9 @@ enum NEONScalar3DiffOp : uint32_t { // NEON scalar instructions with indexed element operand. enum NEONScalarByIndexedElementOp : uint32_t { - NEONScalarByIndexedElementFixed = 0x5F000000u, - NEONScalarByIndexedElementFMask = 0xDF000400u, - NEONScalarByIndexedElementMask = 0xFF00F400u, + NEONScalarByIndexedElementFixed = 0x5F000000, + NEONScalarByIndexedElementFMask = 0xDF000400, + NEONScalarByIndexedElementMask = 0xFF00F400, NEON_SQDMLAL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMLAL_byelement, NEON_SQDMLSL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMLSL_byelement, NEON_SQDMULL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMULL_byelement, @@ -2742,9 +2751,9 @@ enum NEONScalarByIndexedElementOp : uint32_t { // Floating point instructions. NEONScalarByIndexedElementFPFixed - = NEONScalarByIndexedElementFixed | 0x00800000u, + = NEONScalarByIndexedElementFixed | 0x00800000, NEONScalarByIndexedElementFPMask - = NEONScalarByIndexedElementMask | 0x00800000u, + = NEONScalarByIndexedElementMask | 0x00800000, NEON_FMLA_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLA_byelement, NEON_FMLS_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLS_byelement, NEON_FMUL_byelement_scalar = NEON_Q | NEONScalar | NEON_FMUL_byelement, @@ -2753,35 +2762,35 @@ enum NEONScalarByIndexedElementOp : uint32_t { // NEON scalar register copy. enum NEONScalarCopyOp : uint32_t { - NEONScalarCopyFixed = 0x5E000400u, - NEONScalarCopyFMask = 0xDFE08400u, - NEONScalarCopyMask = 0xFFE0FC00u, + NEONScalarCopyFixed = 0x5E000400, + NEONScalarCopyFMask = 0xDFE08400, + NEONScalarCopyMask = 0xFFE0FC00, NEON_DUP_ELEMENT_scalar = NEON_Q | NEONScalar | NEON_DUP_ELEMENT }; // NEON scalar pairwise instructions. enum NEONScalarPairwiseOp : uint32_t { - NEONScalarPairwiseFixed = 0x5E300800u, - NEONScalarPairwiseFMask = 0xDF3E0C00u, - NEONScalarPairwiseMask = 0xFFB1F800u, - NEON_ADDP_scalar = NEONScalarPairwiseFixed | 0x0081B000u, - NEON_FMAXNMP_h_scalar = NEONScalarPairwiseFixed | 0x0000C000u, - NEON_FADDP_h_scalar = NEONScalarPairwiseFixed | 0x0000D000u, - NEON_FMAXP_h_scalar = NEONScalarPairwiseFixed | 0x0000F000u, - NEON_FMINNMP_h_scalar = NEONScalarPairwiseFixed | 0x0080C000u, - NEON_FMINP_h_scalar = NEONScalarPairwiseFixed | 0x0080F000u, - NEON_FMAXNMP_scalar = NEONScalarPairwiseFixed | 0x2000C000u, - NEON_FMINNMP_scalar = NEONScalarPairwiseFixed | 0x2080C000u, - NEON_FADDP_scalar = NEONScalarPairwiseFixed | 0x2000D000u, - NEON_FMAXP_scalar = NEONScalarPairwiseFixed | 0x2000F000u, - NEON_FMINP_scalar = NEONScalarPairwiseFixed | 0x2080F000u + NEONScalarPairwiseFixed = 0x5E300800, + NEONScalarPairwiseFMask = 0xDF3E0C00, + NEONScalarPairwiseMask = 0xFFB1F800, + NEON_ADDP_scalar = NEONScalarPairwiseFixed | 0x0081B000, + NEON_FMAXNMP_h_scalar = NEONScalarPairwiseFixed | 0x0000C000, + NEON_FADDP_h_scalar = NEONScalarPairwiseFixed | 0x0000D000, + NEON_FMAXP_h_scalar = NEONScalarPairwiseFixed | 0x0000F000, + NEON_FMINNMP_h_scalar = NEONScalarPairwiseFixed | 0x0080C000, + NEON_FMINP_h_scalar = NEONScalarPairwiseFixed | 0x0080F000, + NEON_FMAXNMP_scalar = NEONScalarPairwiseFixed | 0x2000C000, + NEON_FMINNMP_scalar = NEONScalarPairwiseFixed | 0x2080C000, + NEON_FADDP_scalar = NEONScalarPairwiseFixed | 0x2000D000, + NEON_FMAXP_scalar = NEONScalarPairwiseFixed | 0x2000F000, + NEON_FMINP_scalar = NEONScalarPairwiseFixed | 0x2080F000 }; // NEON scalar shift immediate. enum NEONScalarShiftImmediateOp : uint32_t { - NEONScalarShiftImmediateFixed = 0x5F000400u, - NEONScalarShiftImmediateFMask = 0xDF800400u, - NEONScalarShiftImmediateMask = 0xFF80FC00u, + NEONScalarShiftImmediateFixed = 0x5F000400, + NEONScalarShiftImmediateFMask = 0xDF800400, + NEONScalarShiftImmediateMask = 0xFF80FC00, NEON_SHL_scalar = NEON_Q | NEONScalar | NEON_SHL, NEON_SLI_scalar = NEON_Q | NEONScalar | NEON_SLI, NEON_SRI_scalar = NEON_Q | NEONScalar | NEON_SRI, @@ -2809,1638 +2818,1638 @@ enum NEONScalarShiftImmediateOp : uint32_t { }; enum SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsOp : uint32_t { - SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFixed = 0x84A00000u, - SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFMask = 0xFFA08000u, - SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsMask = 0xFFA0E000u, + SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFixed = 0x84A00000, + SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFMask = 0xFFA08000, + SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsMask = 0xFFA0E000, LD1SH_z_p_bz_s_x32_scaled = SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFixed, - LDFF1SH_z_p_bz_s_x32_scaled = SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFixed | 0x00002000u, - LD1H_z_p_bz_s_x32_scaled = SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFixed | 0x00004000u, - LDFF1H_z_p_bz_s_x32_scaled = SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFixed | 0x00006000u + LDFF1SH_z_p_bz_s_x32_scaled = SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFixed | 0x00002000, + LD1H_z_p_bz_s_x32_scaled = SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFixed | 0x00004000, + LDFF1H_z_p_bz_s_x32_scaled = SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFixed | 0x00006000 }; enum SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsOp : uint32_t { - SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsFixed = 0x85200000u, - SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsFMask = 0xFFA08000u, - SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsMask = 0xFFA0E000u, - LD1W_z_p_bz_s_x32_scaled = SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsFixed | 0x00004000u, - LDFF1W_z_p_bz_s_x32_scaled = SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsFixed | 0x00006000u + SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsFixed = 0x85200000, + SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsFMask = 0xFFA08000, + SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsMask = 0xFFA0E000, + LD1W_z_p_bz_s_x32_scaled = SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsFixed | 0x00004000, + LDFF1W_z_p_bz_s_x32_scaled = SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsFixed | 0x00006000 }; enum SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsOp : uint32_t { - SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed = 0x84000000u, - SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFMask = 0xFE208000u, - SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsMask = 0xFFA0E000u, + SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed = 0x84000000, + SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFMask = 0xFE208000, + SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsMask = 0xFFA0E000, LD1SB_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed, - LDFF1SB_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00002000u, - LD1B_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00004000u, - LDFF1B_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00006000u, - LD1SH_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00800000u, - LDFF1SH_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00802000u, - LD1H_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00804000u, - LDFF1H_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00806000u, - LD1W_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x01004000u, - LDFF1W_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x01006000u + LDFF1SB_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00002000, + LD1B_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00004000, + LDFF1B_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00006000, + LD1SH_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00800000, + LDFF1SH_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00802000, + LD1H_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00804000, + LDFF1H_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00806000, + LD1W_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x01004000, + LDFF1W_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x01006000 }; enum SVE32BitGatherLoad_VectorPlusImmOp : uint32_t { - SVE32BitGatherLoad_VectorPlusImmFixed = 0x84208000u, - SVE32BitGatherLoad_VectorPlusImmFMask = 0xFE608000u, - SVE32BitGatherLoad_VectorPlusImmMask = 0xFFE0E000u, + SVE32BitGatherLoad_VectorPlusImmFixed = 0x84208000, + SVE32BitGatherLoad_VectorPlusImmFMask = 0xFE608000, + SVE32BitGatherLoad_VectorPlusImmMask = 0xFFE0E000, LD1SB_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed, - LDFF1SB_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00002000u, - LD1B_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00004000u, - LDFF1B_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00006000u, - LD1SH_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00800000u, - LDFF1SH_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00802000u, - LD1H_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00804000u, - LDFF1H_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00806000u, - LD1W_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x01004000u, - LDFF1W_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x01006000u + LDFF1SB_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00002000, + LD1B_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00004000, + LDFF1B_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00006000, + LD1SH_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00800000, + LDFF1SH_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00802000, + LD1H_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00804000, + LDFF1H_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00806000, + LD1W_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x01004000, + LDFF1W_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x01006000 }; enum SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsOp : uint32_t { - SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFixed = 0x84200000u, - SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFMask = 0xFFA08010u, - SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsMask = 0xFFA0E010u, + SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFixed = 0x84200000, + SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFMask = 0xFFA08010, + SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsMask = 0xFFA0E010, PRFB_i_p_bz_s_x32_scaled = SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFixed, - PRFH_i_p_bz_s_x32_scaled = SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFixed | 0x00002000u, - PRFW_i_p_bz_s_x32_scaled = SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFixed | 0x00004000u, - PRFD_i_p_bz_s_x32_scaled = SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFixed | 0x00006000u + PRFH_i_p_bz_s_x32_scaled = SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFixed | 0x00002000, + PRFW_i_p_bz_s_x32_scaled = SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFixed | 0x00004000, + PRFD_i_p_bz_s_x32_scaled = SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFixed | 0x00006000 }; enum SVE32BitGatherPrefetch_VectorPlusImmOp : uint32_t { - SVE32BitGatherPrefetch_VectorPlusImmFixed = 0x8400E000u, - SVE32BitGatherPrefetch_VectorPlusImmFMask = 0xFE60E010u, - SVE32BitGatherPrefetch_VectorPlusImmMask = 0xFFE0E010u, + SVE32BitGatherPrefetch_VectorPlusImmFixed = 0x8400E000, + SVE32BitGatherPrefetch_VectorPlusImmFMask = 0xFE60E010, + SVE32BitGatherPrefetch_VectorPlusImmMask = 0xFFE0E010, PRFB_i_p_ai_s = SVE32BitGatherPrefetch_VectorPlusImmFixed, - PRFH_i_p_ai_s = SVE32BitGatherPrefetch_VectorPlusImmFixed | 0x00800000u, - PRFW_i_p_ai_s = SVE32BitGatherPrefetch_VectorPlusImmFixed | 0x01000000u, - PRFD_i_p_ai_s = SVE32BitGatherPrefetch_VectorPlusImmFixed | 0x01800000u + PRFH_i_p_ai_s = SVE32BitGatherPrefetch_VectorPlusImmFixed | 0x00800000, + PRFW_i_p_ai_s = SVE32BitGatherPrefetch_VectorPlusImmFixed | 0x01000000, + PRFD_i_p_ai_s = SVE32BitGatherPrefetch_VectorPlusImmFixed | 0x01800000 }; enum SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsOp : uint32_t { - SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsFixed = 0xE4608000u, - SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsFMask = 0xFE60A000u, - SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsMask = 0xFFE0A000u, - ST1H_z_p_bz_s_x32_scaled = SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsFixed | 0x00800000u, - ST1W_z_p_bz_s_x32_scaled = SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsFixed | 0x01000000u + SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsFixed = 0xE4608000, + SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsFMask = 0xFE60A000, + SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsMask = 0xFFE0A000, + ST1H_z_p_bz_s_x32_scaled = SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsFixed | 0x00800000, + ST1W_z_p_bz_s_x32_scaled = SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsFixed | 0x01000000 }; enum SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsOp : uint32_t { - SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsFixed = 0xE4408000u, - SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsFMask = 0xFE60A000u, - SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsMask = 0xFFE0A000u, + SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsFixed = 0xE4408000, + SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsFMask = 0xFE60A000, + SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsMask = 0xFFE0A000, ST1B_z_p_bz_s_x32_unscaled = SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsFixed, - ST1H_z_p_bz_s_x32_unscaled = SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsFixed | 0x00800000u, - ST1W_z_p_bz_s_x32_unscaled = SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsFixed | 0x01000000u + ST1H_z_p_bz_s_x32_unscaled = SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsFixed | 0x00800000, + ST1W_z_p_bz_s_x32_unscaled = SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsFixed | 0x01000000 }; enum SVE32BitScatterStore_VectorPlusImmOp : uint32_t { - SVE32BitScatterStore_VectorPlusImmFixed = 0xE460A000u, - SVE32BitScatterStore_VectorPlusImmFMask = 0xFE60E000u, - SVE32BitScatterStore_VectorPlusImmMask = 0xFFE0E000u, + SVE32BitScatterStore_VectorPlusImmFixed = 0xE460A000, + SVE32BitScatterStore_VectorPlusImmFMask = 0xFE60E000, + SVE32BitScatterStore_VectorPlusImmMask = 0xFFE0E000, ST1B_z_p_ai_s = SVE32BitScatterStore_VectorPlusImmFixed, - ST1H_z_p_ai_s = SVE32BitScatterStore_VectorPlusImmFixed | 0x00800000u, - ST1W_z_p_ai_s = SVE32BitScatterStore_VectorPlusImmFixed | 0x01000000u + ST1H_z_p_ai_s = SVE32BitScatterStore_VectorPlusImmFixed | 0x00800000, + ST1W_z_p_ai_s = SVE32BitScatterStore_VectorPlusImmFixed | 0x01000000 }; enum SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsOp : uint32_t { - SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed = 0xC4200000u, - SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFMask = 0xFE208000u, - SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsMask = 0xFFA0E000u, - LD1SH_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x00800000u, - LDFF1SH_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x00802000u, - LD1H_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x00804000u, - LDFF1H_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x00806000u, - LD1SW_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01000000u, - LDFF1SW_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01002000u, - LD1W_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01004000u, - LDFF1W_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01006000u, - LD1D_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01804000u, - LDFF1D_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01806000u + SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed = 0xC4200000, + SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFMask = 0xFE208000, + SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsMask = 0xFFA0E000, + LD1SH_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x00800000, + LDFF1SH_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x00802000, + LD1H_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x00804000, + LDFF1H_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x00806000, + LD1SW_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01000000, + LDFF1SW_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01002000, + LD1W_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01004000, + LDFF1W_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01006000, + LD1D_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01804000, + LDFF1D_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01806000 }; enum SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsOp : uint32_t { - SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed = 0xC4608000u, - SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFMask = 0xFE608000u, - SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsMask = 0xFFE0E000u, - LD1SH_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x00800000u, - LDFF1SH_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x00802000u, - LD1H_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x00804000u, - LDFF1H_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x00806000u, - LD1SW_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01000000u, - LDFF1SW_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01002000u, - LD1W_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01004000u, - LDFF1W_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01006000u, - LD1D_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01804000u, - LDFF1D_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01806000u + SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed = 0xC4608000, + SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFMask = 0xFE608000, + SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsMask = 0xFFE0E000, + LD1SH_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x00800000, + LDFF1SH_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x00802000, + LD1H_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x00804000, + LDFF1H_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x00806000, + LD1SW_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01000000, + LDFF1SW_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01002000, + LD1W_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01004000, + LDFF1W_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01006000, + LD1D_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01804000, + LDFF1D_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01806000 }; enum SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsOp : uint32_t { - SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed = 0xC4408000u, - SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFMask = 0xFE608000u, - SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsMask = 0xFFE0E000u, + SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed = 0xC4408000, + SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFMask = 0xFE608000, + SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsMask = 0xFFE0E000, LD1SB_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed, - LDFF1SB_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00002000u, - LD1B_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00004000u, - LDFF1B_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00006000u, - LD1SH_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00800000u, - LDFF1SH_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00802000u, - LD1H_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00804000u, - LDFF1H_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00806000u, - LD1SW_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01000000u, - LDFF1SW_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01002000u, - LD1W_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01004000u, - LDFF1W_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01006000u, - LD1D_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01804000u, - LDFF1D_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01806000u + LDFF1SB_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00002000, + LD1B_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00004000, + LDFF1B_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00006000, + LD1SH_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00800000, + LDFF1SH_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00802000, + LD1H_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00804000, + LDFF1H_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00806000, + LD1SW_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01000000, + LDFF1SW_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01002000, + LD1W_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01004000, + LDFF1W_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01006000, + LD1D_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01804000, + LDFF1D_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01806000 }; enum SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsOp : uint32_t { - SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed = 0xC4000000u, - SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFMask = 0xFE208000u, - SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsMask = 0xFFA0E000u, + SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed = 0xC4000000, + SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFMask = 0xFE208000, + SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsMask = 0xFFA0E000, LD1SB_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed, - LDFF1SB_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00002000u, - LD1B_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00004000u, - LDFF1B_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00006000u, - LD1SH_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00800000u, - LDFF1SH_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00802000u, - LD1H_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00804000u, - LDFF1H_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00806000u, - LD1SW_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01000000u, - LDFF1SW_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01002000u, - LD1W_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01004000u, - LDFF1W_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01006000u, - LD1D_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01804000u, - LDFF1D_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01806000u + LDFF1SB_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00002000, + LD1B_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00004000, + LDFF1B_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00006000, + LD1SH_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00800000, + LDFF1SH_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00802000, + LD1H_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00804000, + LDFF1H_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00806000, + LD1SW_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01000000, + LDFF1SW_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01002000, + LD1W_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01004000, + LDFF1W_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01006000, + LD1D_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01804000, + LDFF1D_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01806000 }; enum SVE64BitGatherLoad_VectorPlusImmOp : uint32_t { - SVE64BitGatherLoad_VectorPlusImmFixed = 0xC4208000u, - SVE64BitGatherLoad_VectorPlusImmFMask = 0xFE608000u, - SVE64BitGatherLoad_VectorPlusImmMask = 0xFFE0E000u, + SVE64BitGatherLoad_VectorPlusImmFixed = 0xC4208000, + SVE64BitGatherLoad_VectorPlusImmFMask = 0xFE608000, + SVE64BitGatherLoad_VectorPlusImmMask = 0xFFE0E000, LD1SB_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed, - LDFF1SB_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00002000u, - LD1B_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00004000u, - LDFF1B_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00006000u, - LD1SH_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00800000u, - LDFF1SH_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00802000u, - LD1H_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00804000u, - LDFF1H_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00806000u, - LD1SW_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01000000u, - LDFF1SW_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01002000u, - LD1W_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01004000u, - LDFF1W_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01006000u, - LD1D_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01804000u, - LDFF1D_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01806000u + LDFF1SB_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00002000, + LD1B_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00004000, + LDFF1B_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00006000, + LD1SH_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00800000, + LDFF1SH_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00802000, + LD1H_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00804000, + LDFF1H_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00806000, + LD1SW_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01000000, + LDFF1SW_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01002000, + LD1W_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01004000, + LDFF1W_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01006000, + LD1D_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01804000, + LDFF1D_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01806000 }; enum SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsOp : uint32_t { - SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFixed = 0xC4608000u, - SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFMask = 0xFFE08010u, - SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsMask = 0xFFE0E010u, + SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFixed = 0xC4608000, + SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFMask = 0xFFE08010, + SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsMask = 0xFFE0E010, PRFB_i_p_bz_d_64_scaled = SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFixed, - PRFH_i_p_bz_d_64_scaled = SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFixed | 0x00002000u, - PRFW_i_p_bz_d_64_scaled = SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFixed | 0x00004000u, - PRFD_i_p_bz_d_64_scaled = SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFixed | 0x00006000u + PRFH_i_p_bz_d_64_scaled = SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFixed | 0x00002000, + PRFW_i_p_bz_d_64_scaled = SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFixed | 0x00004000, + PRFD_i_p_bz_d_64_scaled = SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFixed | 0x00006000 }; enum SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsOp : uint32_t { - SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFixed = 0xC4200000u, - SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFMask = 0xFFA08010u, - SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsMask = 0xFFA0E010u, + SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFixed = 0xC4200000, + SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFMask = 0xFFA08010, + SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsMask = 0xFFA0E010, PRFB_i_p_bz_d_x32_scaled = SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFixed, - PRFH_i_p_bz_d_x32_scaled = SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x00002000u, - PRFW_i_p_bz_d_x32_scaled = SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x00004000u, - PRFD_i_p_bz_d_x32_scaled = SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x00006000u + PRFH_i_p_bz_d_x32_scaled = SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x00002000, + PRFW_i_p_bz_d_x32_scaled = SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x00004000, + PRFD_i_p_bz_d_x32_scaled = SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x00006000 }; enum SVE64BitGatherPrefetch_VectorPlusImmOp : uint32_t { - SVE64BitGatherPrefetch_VectorPlusImmFixed = 0xC400E000u, - SVE64BitGatherPrefetch_VectorPlusImmFMask = 0xFE60E010u, - SVE64BitGatherPrefetch_VectorPlusImmMask = 0xFFE0E010u, + SVE64BitGatherPrefetch_VectorPlusImmFixed = 0xC400E000, + SVE64BitGatherPrefetch_VectorPlusImmFMask = 0xFE60E010, + SVE64BitGatherPrefetch_VectorPlusImmMask = 0xFFE0E010, PRFB_i_p_ai_d = SVE64BitGatherPrefetch_VectorPlusImmFixed, - PRFH_i_p_ai_d = SVE64BitGatherPrefetch_VectorPlusImmFixed | 0x00800000u, - PRFW_i_p_ai_d = SVE64BitGatherPrefetch_VectorPlusImmFixed | 0x01000000u, - PRFD_i_p_ai_d = SVE64BitGatherPrefetch_VectorPlusImmFixed | 0x01800000u + PRFH_i_p_ai_d = SVE64BitGatherPrefetch_VectorPlusImmFixed | 0x00800000, + PRFW_i_p_ai_d = SVE64BitGatherPrefetch_VectorPlusImmFixed | 0x01000000, + PRFD_i_p_ai_d = SVE64BitGatherPrefetch_VectorPlusImmFixed | 0x01800000 }; enum SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsOp : uint32_t { - SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsFixed = 0xE420A000u, - SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsFMask = 0xFE60E000u, - SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsMask = 0xFFE0E000u, - ST1H_z_p_bz_d_64_scaled = SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsFixed | 0x00800000u, - ST1W_z_p_bz_d_64_scaled = SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsFixed | 0x01000000u, - ST1D_z_p_bz_d_64_scaled = SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsFixed | 0x01800000u + SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsFixed = 0xE420A000, + SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsFMask = 0xFE60E000, + SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsMask = 0xFFE0E000, + ST1H_z_p_bz_d_64_scaled = SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsFixed | 0x00800000, + ST1W_z_p_bz_d_64_scaled = SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsFixed | 0x01000000, + ST1D_z_p_bz_d_64_scaled = SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsFixed | 0x01800000 }; enum SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsOp : uint32_t { - SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFixed = 0xE400A000u, - SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFMask = 0xFE60E000u, - SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsMask = 0xFFE0E000u, + SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFixed = 0xE400A000, + SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFMask = 0xFE60E000, + SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsMask = 0xFFE0E000, ST1B_z_p_bz_d_64_unscaled = SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFixed, - ST1H_z_p_bz_d_64_unscaled = SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFixed | 0x00800000u, - ST1W_z_p_bz_d_64_unscaled = SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFixed | 0x01000000u, - ST1D_z_p_bz_d_64_unscaled = SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFixed | 0x01800000u + ST1H_z_p_bz_d_64_unscaled = SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFixed | 0x00800000, + ST1W_z_p_bz_d_64_unscaled = SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFixed | 0x01000000, + ST1D_z_p_bz_d_64_unscaled = SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFixed | 0x01800000 }; enum SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsOp : uint32_t { - SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsFixed = 0xE4208000u, - SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsFMask = 0xFE60A000u, - SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsMask = 0xFFE0A000u, - ST1H_z_p_bz_d_x32_scaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x00800000u, - ST1W_z_p_bz_d_x32_scaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x01000000u, - ST1D_z_p_bz_d_x32_scaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x01800000u + SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsFixed = 0xE4208000, + SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsFMask = 0xFE60A000, + SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsMask = 0xFFE0A000, + ST1H_z_p_bz_d_x32_scaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x00800000, + ST1W_z_p_bz_d_x32_scaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x01000000, + ST1D_z_p_bz_d_x32_scaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x01800000 }; enum SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsOp : uint32_t { - SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFixed = 0xE4008000u, - SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFMask = 0xFE60A000u, - SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsMask = 0xFFE0A000u, + SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFixed = 0xE4008000, + SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFMask = 0xFE60A000, + SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsMask = 0xFFE0A000, ST1B_z_p_bz_d_x32_unscaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFixed, - ST1H_z_p_bz_d_x32_unscaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00800000u, - ST1W_z_p_bz_d_x32_unscaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01000000u, - ST1D_z_p_bz_d_x32_unscaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01800000u + ST1H_z_p_bz_d_x32_unscaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00800000, + ST1W_z_p_bz_d_x32_unscaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01000000, + ST1D_z_p_bz_d_x32_unscaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01800000 }; enum SVE64BitScatterStore_VectorPlusImmOp : uint32_t { - SVE64BitScatterStore_VectorPlusImmFixed = 0xE440A000u, - SVE64BitScatterStore_VectorPlusImmFMask = 0xFE60E000u, - SVE64BitScatterStore_VectorPlusImmMask = 0xFFE0E000u, + SVE64BitScatterStore_VectorPlusImmFixed = 0xE440A000, + SVE64BitScatterStore_VectorPlusImmFMask = 0xFE60E000, + SVE64BitScatterStore_VectorPlusImmMask = 0xFFE0E000, ST1B_z_p_ai_d = SVE64BitScatterStore_VectorPlusImmFixed, - ST1H_z_p_ai_d = SVE64BitScatterStore_VectorPlusImmFixed | 0x00800000u, - ST1W_z_p_ai_d = SVE64BitScatterStore_VectorPlusImmFixed | 0x01000000u, - ST1D_z_p_ai_d = SVE64BitScatterStore_VectorPlusImmFixed | 0x01800000u + ST1H_z_p_ai_d = SVE64BitScatterStore_VectorPlusImmFixed | 0x00800000, + ST1W_z_p_ai_d = SVE64BitScatterStore_VectorPlusImmFixed | 0x01000000, + ST1D_z_p_ai_d = SVE64BitScatterStore_VectorPlusImmFixed | 0x01800000 }; enum SVEAddressGenerationOp : uint32_t { - SVEAddressGenerationFixed = 0x0420A000u, - SVEAddressGenerationFMask = 0xFF20F000u, - SVEAddressGenerationMask = 0xFFE0F000u, + SVEAddressGenerationFixed = 0x0420A000, + SVEAddressGenerationFMask = 0xFF20F000, + SVEAddressGenerationMask = 0xFFE0F000, ADR_z_az_d_s32_scaled = SVEAddressGenerationFixed, - ADR_z_az_d_u32_scaled = SVEAddressGenerationFixed | 0x00400000u, - ADR_z_az_s_same_scaled = SVEAddressGenerationFixed | 0x00800000u, - ADR_z_az_d_same_scaled = SVEAddressGenerationFixed | 0x00C00000u + ADR_z_az_d_u32_scaled = SVEAddressGenerationFixed | 0x00400000, + ADR_z_az_s_same_scaled = SVEAddressGenerationFixed | 0x00800000, + ADR_z_az_d_same_scaled = SVEAddressGenerationFixed | 0x00C00000 }; enum SVEBitwiseLogicalUnpredicatedOp : uint32_t { - SVEBitwiseLogicalUnpredicatedFixed = 0x04202000u, - SVEBitwiseLogicalUnpredicatedFMask = 0xFF20E000u, - SVEBitwiseLogicalUnpredicatedMask = 0xFFE0FC00u, - AND_z_zz = SVEBitwiseLogicalUnpredicatedFixed | 0x00001000u, - ORR_z_zz = SVEBitwiseLogicalUnpredicatedFixed | 0x00401000u, - EOR_z_zz = SVEBitwiseLogicalUnpredicatedFixed | 0x00801000u, - BIC_z_zz = SVEBitwiseLogicalUnpredicatedFixed | 0x00C01000u + SVEBitwiseLogicalUnpredicatedFixed = 0x04202000, + SVEBitwiseLogicalUnpredicatedFMask = 0xFF20E000, + SVEBitwiseLogicalUnpredicatedMask = 0xFFE0FC00, + AND_z_zz = SVEBitwiseLogicalUnpredicatedFixed | 0x00001000, + ORR_z_zz = SVEBitwiseLogicalUnpredicatedFixed | 0x00401000, + EOR_z_zz = SVEBitwiseLogicalUnpredicatedFixed | 0x00801000, + BIC_z_zz = SVEBitwiseLogicalUnpredicatedFixed | 0x00C01000 }; enum SVEBitwiseLogicalWithImm_UnpredicatedOp : uint32_t { - SVEBitwiseLogicalWithImm_UnpredicatedFixed = 0x05000000u, - SVEBitwiseLogicalWithImm_UnpredicatedFMask = 0xFF3C0000u, - SVEBitwiseLogicalWithImm_UnpredicatedMask = 0xFFFC0000u, + SVEBitwiseLogicalWithImm_UnpredicatedFixed = 0x05000000, + SVEBitwiseLogicalWithImm_UnpredicatedFMask = 0xFF3C0000, + SVEBitwiseLogicalWithImm_UnpredicatedMask = 0xFFFC0000, ORR_z_zi = SVEBitwiseLogicalWithImm_UnpredicatedFixed, - EOR_z_zi = SVEBitwiseLogicalWithImm_UnpredicatedFixed | 0x00400000u, - AND_z_zi = SVEBitwiseLogicalWithImm_UnpredicatedFixed | 0x00800000u + EOR_z_zi = SVEBitwiseLogicalWithImm_UnpredicatedFixed | 0x00400000, + AND_z_zi = SVEBitwiseLogicalWithImm_UnpredicatedFixed | 0x00800000 }; enum SVEBitwiseLogical_PredicatedOp : uint32_t { - SVEBitwiseLogical_PredicatedFixed = 0x04180000u, - SVEBitwiseLogical_PredicatedFMask = 0xFF38E000u, - SVEBitwiseLogical_PredicatedMask = 0xFF3FE000u, + SVEBitwiseLogical_PredicatedFixed = 0x04180000, + SVEBitwiseLogical_PredicatedFMask = 0xFF38E000, + SVEBitwiseLogical_PredicatedMask = 0xFF3FE000, ORR_z_p_zz = SVEBitwiseLogical_PredicatedFixed, - EOR_z_p_zz = SVEBitwiseLogical_PredicatedFixed | 0x00010000u, - AND_z_p_zz = SVEBitwiseLogical_PredicatedFixed | 0x00020000u, - BIC_z_p_zz = SVEBitwiseLogical_PredicatedFixed | 0x00030000u + EOR_z_p_zz = SVEBitwiseLogical_PredicatedFixed | 0x00010000, + AND_z_p_zz = SVEBitwiseLogical_PredicatedFixed | 0x00020000, + BIC_z_p_zz = SVEBitwiseLogical_PredicatedFixed | 0x00030000 }; enum SVEBitwiseShiftByImm_PredicatedOp : uint32_t { - SVEBitwiseShiftByImm_PredicatedFixed = 0x04008000u, - SVEBitwiseShiftByImm_PredicatedFMask = 0xFF30E000u, - SVEBitwiseShiftByImm_PredicatedMask = 0xFF3FE000u, + SVEBitwiseShiftByImm_PredicatedFixed = 0x04008000, + SVEBitwiseShiftByImm_PredicatedFMask = 0xFF30E000, + SVEBitwiseShiftByImm_PredicatedMask = 0xFF3FE000, ASR_z_p_zi = SVEBitwiseShiftByImm_PredicatedFixed, - LSR_z_p_zi = SVEBitwiseShiftByImm_PredicatedFixed | 0x00010000u, - LSL_z_p_zi = SVEBitwiseShiftByImm_PredicatedFixed | 0x00030000u, - ASRD_z_p_zi = SVEBitwiseShiftByImm_PredicatedFixed | 0x00040000u + LSR_z_p_zi = SVEBitwiseShiftByImm_PredicatedFixed | 0x00010000, + LSL_z_p_zi = SVEBitwiseShiftByImm_PredicatedFixed | 0x00030000, + ASRD_z_p_zi = SVEBitwiseShiftByImm_PredicatedFixed | 0x00040000 }; enum SVEBitwiseShiftByVector_PredicatedOp : uint32_t { - SVEBitwiseShiftByVector_PredicatedFixed = 0x04108000u, - SVEBitwiseShiftByVector_PredicatedFMask = 0xFF38E000u, - SVEBitwiseShiftByVector_PredicatedMask = 0xFF3FE000u, + SVEBitwiseShiftByVector_PredicatedFixed = 0x04108000, + SVEBitwiseShiftByVector_PredicatedFMask = 0xFF38E000, + SVEBitwiseShiftByVector_PredicatedMask = 0xFF3FE000, ASR_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed, - LSR_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed | 0x00010000u, - LSL_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed | 0x00030000u, - ASRR_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed | 0x00040000u, - LSRR_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed | 0x00050000u, - LSLR_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed | 0x00070000u + LSR_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed | 0x00010000, + LSL_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed | 0x00030000, + ASRR_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed | 0x00040000, + LSRR_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed | 0x00050000, + LSLR_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed | 0x00070000 }; enum SVEBitwiseShiftByWideElements_PredicatedOp : uint32_t { - SVEBitwiseShiftByWideElements_PredicatedFixed = 0x04188000u, - SVEBitwiseShiftByWideElements_PredicatedFMask = 0xFF38E000u, - SVEBitwiseShiftByWideElements_PredicatedMask = 0xFF3FE000u, + SVEBitwiseShiftByWideElements_PredicatedFixed = 0x04188000, + SVEBitwiseShiftByWideElements_PredicatedFMask = 0xFF38E000, + SVEBitwiseShiftByWideElements_PredicatedMask = 0xFF3FE000, ASR_z_p_zw = SVEBitwiseShiftByWideElements_PredicatedFixed, - LSR_z_p_zw = SVEBitwiseShiftByWideElements_PredicatedFixed | 0x00010000u, - LSL_z_p_zw = SVEBitwiseShiftByWideElements_PredicatedFixed | 0x00030000u + LSR_z_p_zw = SVEBitwiseShiftByWideElements_PredicatedFixed | 0x00010000, + LSL_z_p_zw = SVEBitwiseShiftByWideElements_PredicatedFixed | 0x00030000 }; enum SVEBitwiseShiftUnpredicatedOp : uint32_t { - SVEBitwiseShiftUnpredicatedFixed = 0x04208000u, - SVEBitwiseShiftUnpredicatedFMask = 0xFF20E000u, - SVEBitwiseShiftUnpredicatedMask = 0xFF20FC00u, + SVEBitwiseShiftUnpredicatedFixed = 0x04208000, + SVEBitwiseShiftUnpredicatedFMask = 0xFF20E000, + SVEBitwiseShiftUnpredicatedMask = 0xFF20FC00, ASR_z_zw = SVEBitwiseShiftUnpredicatedFixed, - LSR_z_zw = SVEBitwiseShiftUnpredicatedFixed | 0x00000400u, - LSL_z_zw = SVEBitwiseShiftUnpredicatedFixed | 0x00000C00u, - ASR_z_zi = SVEBitwiseShiftUnpredicatedFixed | 0x00001000u, - LSR_z_zi = SVEBitwiseShiftUnpredicatedFixed | 0x00001400u, - LSL_z_zi = SVEBitwiseShiftUnpredicatedFixed | 0x00001C00u + LSR_z_zw = SVEBitwiseShiftUnpredicatedFixed | 0x00000400, + LSL_z_zw = SVEBitwiseShiftUnpredicatedFixed | 0x00000C00, + ASR_z_zi = SVEBitwiseShiftUnpredicatedFixed | 0x00001000, + LSR_z_zi = SVEBitwiseShiftUnpredicatedFixed | 0x00001400, + LSL_z_zi = SVEBitwiseShiftUnpredicatedFixed | 0x00001C00 }; enum SVEBroadcastBitmaskImmOp : uint32_t { - SVEBroadcastBitmaskImmFixed = 0x05C00000u, - SVEBroadcastBitmaskImmFMask = 0xFFFC0000u, - SVEBroadcastBitmaskImmMask = 0xFFFC0000u, + SVEBroadcastBitmaskImmFixed = 0x05C00000, + SVEBroadcastBitmaskImmFMask = 0xFFFC0000, + SVEBroadcastBitmaskImmMask = 0xFFFC0000, DUPM_z_i = SVEBroadcastBitmaskImmFixed }; enum SVEBroadcastFPImm_UnpredicatedOp : uint32_t { - SVEBroadcastFPImm_UnpredicatedFixed = 0x2539C000u, - SVEBroadcastFPImm_UnpredicatedFMask = 0xFF39C000u, - SVEBroadcastFPImm_UnpredicatedMask = 0xFF3FE000u, + SVEBroadcastFPImm_UnpredicatedFixed = 0x2539C000, + SVEBroadcastFPImm_UnpredicatedFMask = 0xFF39C000, + SVEBroadcastFPImm_UnpredicatedMask = 0xFF3FE000, FDUP_z_i = SVEBroadcastFPImm_UnpredicatedFixed }; enum SVEBroadcastGeneralRegisterOp : uint32_t { - SVEBroadcastGeneralRegisterFixed = 0x05203800u, - SVEBroadcastGeneralRegisterFMask = 0xFF3FFC00u, - SVEBroadcastGeneralRegisterMask = 0xFF3FFC00u, + SVEBroadcastGeneralRegisterFixed = 0x05203800, + SVEBroadcastGeneralRegisterFMask = 0xFF3FFC00, + SVEBroadcastGeneralRegisterMask = 0xFF3FFC00, DUP_z_r = SVEBroadcastGeneralRegisterFixed }; enum SVEBroadcastIndexElementOp : uint32_t { - SVEBroadcastIndexElementFixed = 0x05202000u, - SVEBroadcastIndexElementFMask = 0xFF20FC00u, - SVEBroadcastIndexElementMask = 0xFF20FC00u, + SVEBroadcastIndexElementFixed = 0x05202000, + SVEBroadcastIndexElementFMask = 0xFF20FC00, + SVEBroadcastIndexElementMask = 0xFF20FC00, DUP_z_zi = SVEBroadcastIndexElementFixed }; enum SVEBroadcastIntImm_UnpredicatedOp : uint32_t { - SVEBroadcastIntImm_UnpredicatedFixed = 0x2538C000u, - SVEBroadcastIntImm_UnpredicatedFMask = 0xFF39C000u, - SVEBroadcastIntImm_UnpredicatedMask = 0xFF3FC000u, + SVEBroadcastIntImm_UnpredicatedFixed = 0x2538C000, + SVEBroadcastIntImm_UnpredicatedFMask = 0xFF39C000, + SVEBroadcastIntImm_UnpredicatedMask = 0xFF3FC000, DUP_z_i = SVEBroadcastIntImm_UnpredicatedFixed }; enum SVECompressActiveElementsOp : uint32_t { - SVECompressActiveElementsFixed = 0x05A18000u, - SVECompressActiveElementsFMask = 0xFFBFE000u, - SVECompressActiveElementsMask = 0xFFBFE000u, + SVECompressActiveElementsFixed = 0x05A18000, + SVECompressActiveElementsFMask = 0xFFBFE000, + SVECompressActiveElementsMask = 0xFFBFE000, COMPACT_z_p_z = SVECompressActiveElementsFixed }; enum SVEConditionallyBroadcastElementToVectorOp : uint32_t { - SVEConditionallyBroadcastElementToVectorFixed = 0x05288000u, - SVEConditionallyBroadcastElementToVectorFMask = 0xFF3EE000u, - SVEConditionallyBroadcastElementToVectorMask = 0xFF3FE000u, + SVEConditionallyBroadcastElementToVectorFixed = 0x05288000, + SVEConditionallyBroadcastElementToVectorFMask = 0xFF3EE000, + SVEConditionallyBroadcastElementToVectorMask = 0xFF3FE000, CLASTA_z_p_zz = SVEConditionallyBroadcastElementToVectorFixed, - CLASTB_z_p_zz = SVEConditionallyBroadcastElementToVectorFixed | 0x00010000u + CLASTB_z_p_zz = SVEConditionallyBroadcastElementToVectorFixed | 0x00010000 }; enum SVEConditionallyExtractElementToGeneralRegisterOp : uint32_t { - SVEConditionallyExtractElementToGeneralRegisterFixed = 0x0530A000u, - SVEConditionallyExtractElementToGeneralRegisterFMask = 0xFF3EE000u, - SVEConditionallyExtractElementToGeneralRegisterMask = 0xFF3FE000u, + SVEConditionallyExtractElementToGeneralRegisterFixed = 0x0530A000, + SVEConditionallyExtractElementToGeneralRegisterFMask = 0xFF3EE000, + SVEConditionallyExtractElementToGeneralRegisterMask = 0xFF3FE000, CLASTA_r_p_z = SVEConditionallyExtractElementToGeneralRegisterFixed, - CLASTB_r_p_z = SVEConditionallyExtractElementToGeneralRegisterFixed | 0x00010000u + CLASTB_r_p_z = SVEConditionallyExtractElementToGeneralRegisterFixed | 0x00010000 }; enum SVEConditionallyExtractElementToSIMDFPScalarOp : uint32_t { - SVEConditionallyExtractElementToSIMDFPScalarFixed = 0x052A8000u, - SVEConditionallyExtractElementToSIMDFPScalarFMask = 0xFF3EE000u, - SVEConditionallyExtractElementToSIMDFPScalarMask = 0xFF3FE000u, + SVEConditionallyExtractElementToSIMDFPScalarFixed = 0x052A8000, + SVEConditionallyExtractElementToSIMDFPScalarFMask = 0xFF3EE000, + SVEConditionallyExtractElementToSIMDFPScalarMask = 0xFF3FE000, CLASTA_v_p_z = SVEConditionallyExtractElementToSIMDFPScalarFixed, - CLASTB_v_p_z = SVEConditionallyExtractElementToSIMDFPScalarFixed | 0x00010000u + CLASTB_v_p_z = SVEConditionallyExtractElementToSIMDFPScalarFixed | 0x00010000 }; enum SVEConditionallyTerminateScalarsOp : uint32_t { - SVEConditionallyTerminateScalarsFixed = 0x25202000u, - SVEConditionallyTerminateScalarsFMask = 0xFF20FC0Fu, - SVEConditionallyTerminateScalarsMask = 0xFFA0FC1Fu, - CTERMEQ_rr = SVEConditionallyTerminateScalarsFixed | 0x00800000u, - CTERMNE_rr = SVEConditionallyTerminateScalarsFixed | 0x00800010u + SVEConditionallyTerminateScalarsFixed = 0x25202000, + SVEConditionallyTerminateScalarsFMask = 0xFF20FC0F, + SVEConditionallyTerminateScalarsMask = 0xFFA0FC1F, + CTERMEQ_rr = SVEConditionallyTerminateScalarsFixed | 0x00800000, + CTERMNE_rr = SVEConditionallyTerminateScalarsFixed | 0x00800010 }; enum SVEConstructivePrefix_UnpredicatedOp : uint32_t { - SVEConstructivePrefix_UnpredicatedFixed = 0x0420BC00u, - SVEConstructivePrefix_UnpredicatedFMask = 0xFF20FC00u, - SVEConstructivePrefix_UnpredicatedMask = 0xFFFFFC00u, + SVEConstructivePrefix_UnpredicatedFixed = 0x0420BC00, + SVEConstructivePrefix_UnpredicatedFMask = 0xFF20FC00, + SVEConstructivePrefix_UnpredicatedMask = 0xFFFFFC00, MOVPRFX_z_z = SVEConstructivePrefix_UnpredicatedFixed }; enum SVEContiguousFirstFaultLoad_ScalarPlusScalarOp : uint32_t { - SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed = 0xA4006000u, - SVEContiguousFirstFaultLoad_ScalarPlusScalarFMask = 0xFE00E000u, - SVEContiguousFirstFaultLoad_ScalarPlusScalarMask = 0xFFE0E000u, + SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed = 0xA4006000, + SVEContiguousFirstFaultLoad_ScalarPlusScalarFMask = 0xFE00E000, + SVEContiguousFirstFaultLoad_ScalarPlusScalarMask = 0xFFE0E000, LDFF1B_z_p_br_u8 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed, - LDFF1B_z_p_br_u16 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00200000u, - LDFF1B_z_p_br_u32 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00400000u, - LDFF1B_z_p_br_u64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00600000u, - LDFF1SW_z_p_br_s64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00800000u, - LDFF1H_z_p_br_u16 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00A00000u, - LDFF1H_z_p_br_u32 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00C00000u, - LDFF1H_z_p_br_u64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00E00000u, - LDFF1SH_z_p_br_s64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01000000u, - LDFF1SH_z_p_br_s32 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01200000u, - LDFF1W_z_p_br_u32 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01400000u, - LDFF1W_z_p_br_u64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01600000u, - LDFF1SB_z_p_br_s64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01800000u, - LDFF1SB_z_p_br_s32 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01A00000u, - LDFF1SB_z_p_br_s16 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01C00000u, - LDFF1D_z_p_br_u64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01E00000u + LDFF1B_z_p_br_u16 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00200000, + LDFF1B_z_p_br_u32 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00400000, + LDFF1B_z_p_br_u64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00600000, + LDFF1SW_z_p_br_s64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00800000, + LDFF1H_z_p_br_u16 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00A00000, + LDFF1H_z_p_br_u32 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00C00000, + LDFF1H_z_p_br_u64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00E00000, + LDFF1SH_z_p_br_s64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01000000, + LDFF1SH_z_p_br_s32 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01200000, + LDFF1W_z_p_br_u32 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01400000, + LDFF1W_z_p_br_u64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01600000, + LDFF1SB_z_p_br_s64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01800000, + LDFF1SB_z_p_br_s32 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01A00000, + LDFF1SB_z_p_br_s16 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01C00000, + LDFF1D_z_p_br_u64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01E00000 }; enum SVEContiguousLoad_ScalarPlusImmOp : uint32_t { - SVEContiguousLoad_ScalarPlusImmFixed = 0xA400A000u, - SVEContiguousLoad_ScalarPlusImmFMask = 0xFE10E000u, - SVEContiguousLoad_ScalarPlusImmMask = 0xFFF0E000u, + SVEContiguousLoad_ScalarPlusImmFixed = 0xA400A000, + SVEContiguousLoad_ScalarPlusImmFMask = 0xFE10E000, + SVEContiguousLoad_ScalarPlusImmMask = 0xFFF0E000, LD1B_z_p_bi_u8 = SVEContiguousLoad_ScalarPlusImmFixed, - LD1B_z_p_bi_u16 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00200000u, - LD1B_z_p_bi_u32 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00400000u, - LD1B_z_p_bi_u64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00600000u, - LD1SW_z_p_bi_s64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00800000u, - LD1H_z_p_bi_u16 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00A00000u, - LD1H_z_p_bi_u32 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00C00000u, - LD1H_z_p_bi_u64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00E00000u, - LD1SH_z_p_bi_s64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01000000u, - LD1SH_z_p_bi_s32 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01200000u, - LD1W_z_p_bi_u32 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01400000u, - LD1W_z_p_bi_u64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01600000u, - LD1SB_z_p_bi_s64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01800000u, - LD1SB_z_p_bi_s32 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01A00000u, - LD1SB_z_p_bi_s16 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01C00000u, - LD1D_z_p_bi_u64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01E00000u + LD1B_z_p_bi_u16 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00200000, + LD1B_z_p_bi_u32 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00400000, + LD1B_z_p_bi_u64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00600000, + LD1SW_z_p_bi_s64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00800000, + LD1H_z_p_bi_u16 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00A00000, + LD1H_z_p_bi_u32 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00C00000, + LD1H_z_p_bi_u64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00E00000, + LD1SH_z_p_bi_s64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01000000, + LD1SH_z_p_bi_s32 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01200000, + LD1W_z_p_bi_u32 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01400000, + LD1W_z_p_bi_u64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01600000, + LD1SB_z_p_bi_s64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01800000, + LD1SB_z_p_bi_s32 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01A00000, + LD1SB_z_p_bi_s16 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01C00000, + LD1D_z_p_bi_u64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01E00000 }; enum SVEContiguousLoad_ScalarPlusScalarOp : uint32_t { - SVEContiguousLoad_ScalarPlusScalarFixed = 0xA4004000u, - SVEContiguousLoad_ScalarPlusScalarFMask = 0xFE00E000u, - SVEContiguousLoad_ScalarPlusScalarMask = 0xFFE0E000u, + SVEContiguousLoad_ScalarPlusScalarFixed = 0xA4004000, + SVEContiguousLoad_ScalarPlusScalarFMask = 0xFE00E000, + SVEContiguousLoad_ScalarPlusScalarMask = 0xFFE0E000, LD1B_z_p_br_u8 = SVEContiguousLoad_ScalarPlusScalarFixed, - LD1B_z_p_br_u16 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00200000u, - LD1B_z_p_br_u32 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00400000u, - LD1B_z_p_br_u64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00600000u, - LD1SW_z_p_br_s64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00800000u, - LD1H_z_p_br_u16 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00A00000u, - LD1H_z_p_br_u32 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00C00000u, - LD1H_z_p_br_u64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00E00000u, - LD1SH_z_p_br_s64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01000000u, - LD1SH_z_p_br_s32 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01200000u, - LD1W_z_p_br_u32 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01400000u, - LD1W_z_p_br_u64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01600000u, - LD1SB_z_p_br_s64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01800000u, - LD1SB_z_p_br_s32 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01A00000u, - LD1SB_z_p_br_s16 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01C00000u, - LD1D_z_p_br_u64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01E00000u + LD1B_z_p_br_u16 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00200000, + LD1B_z_p_br_u32 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00400000, + LD1B_z_p_br_u64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00600000, + LD1SW_z_p_br_s64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00800000, + LD1H_z_p_br_u16 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00A00000, + LD1H_z_p_br_u32 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00C00000, + LD1H_z_p_br_u64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00E00000, + LD1SH_z_p_br_s64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01000000, + LD1SH_z_p_br_s32 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01200000, + LD1W_z_p_br_u32 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01400000, + LD1W_z_p_br_u64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01600000, + LD1SB_z_p_br_s64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01800000, + LD1SB_z_p_br_s32 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01A00000, + LD1SB_z_p_br_s16 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01C00000, + LD1D_z_p_br_u64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01E00000 }; enum SVEContiguousNonFaultLoad_ScalarPlusImmOp : uint32_t { - SVEContiguousNonFaultLoad_ScalarPlusImmFixed = 0xA410A000u, - SVEContiguousNonFaultLoad_ScalarPlusImmFMask = 0xFE10E000u, - SVEContiguousNonFaultLoad_ScalarPlusImmMask = 0xFFF0E000u, + SVEContiguousNonFaultLoad_ScalarPlusImmFixed = 0xA410A000, + SVEContiguousNonFaultLoad_ScalarPlusImmFMask = 0xFE10E000, + SVEContiguousNonFaultLoad_ScalarPlusImmMask = 0xFFF0E000, LDNF1B_z_p_bi_u8 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed, - LDNF1B_z_p_bi_u16 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00200000u, - LDNF1B_z_p_bi_u32 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00400000u, - LDNF1B_z_p_bi_u64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00600000u, - LDNF1SW_z_p_bi_s64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00800000u, - LDNF1H_z_p_bi_u16 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00A00000u, - LDNF1H_z_p_bi_u32 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00C00000u, - LDNF1H_z_p_bi_u64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00E00000u, - LDNF1SH_z_p_bi_s64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01000000u, - LDNF1SH_z_p_bi_s32 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01200000u, - LDNF1W_z_p_bi_u32 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01400000u, - LDNF1W_z_p_bi_u64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01600000u, - LDNF1SB_z_p_bi_s64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01800000u, - LDNF1SB_z_p_bi_s32 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01A00000u, - LDNF1SB_z_p_bi_s16 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01C00000u, - LDNF1D_z_p_bi_u64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01E00000u + LDNF1B_z_p_bi_u16 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00200000, + LDNF1B_z_p_bi_u32 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00400000, + LDNF1B_z_p_bi_u64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00600000, + LDNF1SW_z_p_bi_s64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00800000, + LDNF1H_z_p_bi_u16 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00A00000, + LDNF1H_z_p_bi_u32 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00C00000, + LDNF1H_z_p_bi_u64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00E00000, + LDNF1SH_z_p_bi_s64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01000000, + LDNF1SH_z_p_bi_s32 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01200000, + LDNF1W_z_p_bi_u32 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01400000, + LDNF1W_z_p_bi_u64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01600000, + LDNF1SB_z_p_bi_s64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01800000, + LDNF1SB_z_p_bi_s32 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01A00000, + LDNF1SB_z_p_bi_s16 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01C00000, + LDNF1D_z_p_bi_u64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01E00000 }; enum SVEContiguousNonTemporalLoad_ScalarPlusImmOp : uint32_t { - SVEContiguousNonTemporalLoad_ScalarPlusImmFixed = 0xA400E000u, - SVEContiguousNonTemporalLoad_ScalarPlusImmFMask = 0xFE70E000u, - SVEContiguousNonTemporalLoad_ScalarPlusImmMask = 0xFFF0E000u, + SVEContiguousNonTemporalLoad_ScalarPlusImmFixed = 0xA400E000, + SVEContiguousNonTemporalLoad_ScalarPlusImmFMask = 0xFE70E000, + SVEContiguousNonTemporalLoad_ScalarPlusImmMask = 0xFFF0E000, LDNT1B_z_p_bi_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusImmFixed, - LDNT1H_z_p_bi_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusImmFixed | 0x00800000u, - LDNT1W_z_p_bi_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusImmFixed | 0x01000000u, - LDNT1D_z_p_bi_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusImmFixed | 0x01800000u + LDNT1H_z_p_bi_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusImmFixed | 0x00800000, + LDNT1W_z_p_bi_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusImmFixed | 0x01000000, + LDNT1D_z_p_bi_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusImmFixed | 0x01800000 }; enum SVEContiguousNonTemporalLoad_ScalarPlusScalarOp : uint32_t { - SVEContiguousNonTemporalLoad_ScalarPlusScalarFixed = 0xA400C000u, - SVEContiguousNonTemporalLoad_ScalarPlusScalarFMask = 0xFE60E000u, - SVEContiguousNonTemporalLoad_ScalarPlusScalarMask = 0xFFE0E000u, + SVEContiguousNonTemporalLoad_ScalarPlusScalarFixed = 0xA400C000, + SVEContiguousNonTemporalLoad_ScalarPlusScalarFMask = 0xFE60E000, + SVEContiguousNonTemporalLoad_ScalarPlusScalarMask = 0xFFE0E000, LDNT1B_z_p_br_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusScalarFixed, - LDNT1H_z_p_br_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusScalarFixed | 0x00800000u, - LDNT1W_z_p_br_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusScalarFixed | 0x01000000u, - LDNT1D_z_p_br_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusScalarFixed | 0x01800000u + LDNT1H_z_p_br_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusScalarFixed | 0x00800000, + LDNT1W_z_p_br_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusScalarFixed | 0x01000000, + LDNT1D_z_p_br_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusScalarFixed | 0x01800000 }; enum SVEContiguousNonTemporalStore_ScalarPlusImmOp : uint32_t { - SVEContiguousNonTemporalStore_ScalarPlusImmFixed = 0xE410E000u, - SVEContiguousNonTemporalStore_ScalarPlusImmFMask = 0xFE70E000u, - SVEContiguousNonTemporalStore_ScalarPlusImmMask = 0xFFF0E000u, + SVEContiguousNonTemporalStore_ScalarPlusImmFixed = 0xE410E000, + SVEContiguousNonTemporalStore_ScalarPlusImmFMask = 0xFE70E000, + SVEContiguousNonTemporalStore_ScalarPlusImmMask = 0xFFF0E000, STNT1B_z_p_bi_contiguous = SVEContiguousNonTemporalStore_ScalarPlusImmFixed, - STNT1H_z_p_bi_contiguous = SVEContiguousNonTemporalStore_ScalarPlusImmFixed | 0x00800000u, - STNT1W_z_p_bi_contiguous = SVEContiguousNonTemporalStore_ScalarPlusImmFixed | 0x01000000u, - STNT1D_z_p_bi_contiguous = SVEContiguousNonTemporalStore_ScalarPlusImmFixed | 0x01800000u + STNT1H_z_p_bi_contiguous = SVEContiguousNonTemporalStore_ScalarPlusImmFixed | 0x00800000, + STNT1W_z_p_bi_contiguous = SVEContiguousNonTemporalStore_ScalarPlusImmFixed | 0x01000000, + STNT1D_z_p_bi_contiguous = SVEContiguousNonTemporalStore_ScalarPlusImmFixed | 0x01800000 }; enum SVEContiguousNonTemporalStore_ScalarPlusScalarOp : uint32_t { - SVEContiguousNonTemporalStore_ScalarPlusScalarFixed = 0xE4006000u, - SVEContiguousNonTemporalStore_ScalarPlusScalarFMask = 0xFE60E000u, - SVEContiguousNonTemporalStore_ScalarPlusScalarMask = 0xFFE0E000u, + SVEContiguousNonTemporalStore_ScalarPlusScalarFixed = 0xE4006000, + SVEContiguousNonTemporalStore_ScalarPlusScalarFMask = 0xFE60E000, + SVEContiguousNonTemporalStore_ScalarPlusScalarMask = 0xFFE0E000, STNT1B_z_p_br_contiguous = SVEContiguousNonTemporalStore_ScalarPlusScalarFixed, - STNT1H_z_p_br_contiguous = SVEContiguousNonTemporalStore_ScalarPlusScalarFixed | 0x00800000u, - STNT1W_z_p_br_contiguous = SVEContiguousNonTemporalStore_ScalarPlusScalarFixed | 0x01000000u, - STNT1D_z_p_br_contiguous = SVEContiguousNonTemporalStore_ScalarPlusScalarFixed | 0x01800000u + STNT1H_z_p_br_contiguous = SVEContiguousNonTemporalStore_ScalarPlusScalarFixed | 0x00800000, + STNT1W_z_p_br_contiguous = SVEContiguousNonTemporalStore_ScalarPlusScalarFixed | 0x01000000, + STNT1D_z_p_br_contiguous = SVEContiguousNonTemporalStore_ScalarPlusScalarFixed | 0x01800000 }; enum SVEContiguousPrefetch_ScalarPlusImmOp : uint32_t { - SVEContiguousPrefetch_ScalarPlusImmFixed = 0x85C00000u, - SVEContiguousPrefetch_ScalarPlusImmFMask = 0xFFC08010u, - SVEContiguousPrefetch_ScalarPlusImmMask = 0xFFC0E010u, + SVEContiguousPrefetch_ScalarPlusImmFixed = 0x85C00000, + SVEContiguousPrefetch_ScalarPlusImmFMask = 0xFFC08010, + SVEContiguousPrefetch_ScalarPlusImmMask = 0xFFC0E010, PRFB_i_p_bi_s = SVEContiguousPrefetch_ScalarPlusImmFixed, - PRFH_i_p_bi_s = SVEContiguousPrefetch_ScalarPlusImmFixed | 0x00002000u, - PRFW_i_p_bi_s = SVEContiguousPrefetch_ScalarPlusImmFixed | 0x00004000u, - PRFD_i_p_bi_s = SVEContiguousPrefetch_ScalarPlusImmFixed | 0x00006000u + PRFH_i_p_bi_s = SVEContiguousPrefetch_ScalarPlusImmFixed | 0x00002000, + PRFW_i_p_bi_s = SVEContiguousPrefetch_ScalarPlusImmFixed | 0x00004000, + PRFD_i_p_bi_s = SVEContiguousPrefetch_ScalarPlusImmFixed | 0x00006000 }; enum SVEContiguousPrefetch_ScalarPlusScalarOp : uint32_t { - SVEContiguousPrefetch_ScalarPlusScalarFixed = 0x8400C000u, - SVEContiguousPrefetch_ScalarPlusScalarFMask = 0xFE60E010u, - SVEContiguousPrefetch_ScalarPlusScalarMask = 0xFFE0E010u, + SVEContiguousPrefetch_ScalarPlusScalarFixed = 0x8400C000, + SVEContiguousPrefetch_ScalarPlusScalarFMask = 0xFE60E010, + SVEContiguousPrefetch_ScalarPlusScalarMask = 0xFFE0E010, PRFB_i_p_br_s = SVEContiguousPrefetch_ScalarPlusScalarFixed, - PRFH_i_p_br_s = SVEContiguousPrefetch_ScalarPlusScalarFixed | 0x00800000u, - PRFW_i_p_br_s = SVEContiguousPrefetch_ScalarPlusScalarFixed | 0x01000000u, - PRFD_i_p_br_s = SVEContiguousPrefetch_ScalarPlusScalarFixed | 0x01800000u + PRFH_i_p_br_s = SVEContiguousPrefetch_ScalarPlusScalarFixed | 0x00800000, + PRFW_i_p_br_s = SVEContiguousPrefetch_ScalarPlusScalarFixed | 0x01000000, + PRFD_i_p_br_s = SVEContiguousPrefetch_ScalarPlusScalarFixed | 0x01800000 }; enum SVEContiguousStore_ScalarPlusImmOp : uint32_t { - SVEContiguousStore_ScalarPlusImmFixed = 0xE400E000u, - SVEContiguousStore_ScalarPlusImmFMask = 0xFE10E000u, - SVEContiguousStore_ScalarPlusImmMask = 0xFF90E000u, + SVEContiguousStore_ScalarPlusImmFixed = 0xE400E000, + SVEContiguousStore_ScalarPlusImmFMask = 0xFE10E000, + SVEContiguousStore_ScalarPlusImmMask = 0xFF90E000, ST1B_z_p_bi = SVEContiguousStore_ScalarPlusImmFixed, - ST1H_z_p_bi = SVEContiguousStore_ScalarPlusImmFixed | 0x00800000u, - ST1W_z_p_bi = SVEContiguousStore_ScalarPlusImmFixed | 0x01000000u, - ST1D_z_p_bi = SVEContiguousStore_ScalarPlusImmFixed | 0x01800000u + ST1H_z_p_bi = SVEContiguousStore_ScalarPlusImmFixed | 0x00800000, + ST1W_z_p_bi = SVEContiguousStore_ScalarPlusImmFixed | 0x01000000, + ST1D_z_p_bi = SVEContiguousStore_ScalarPlusImmFixed | 0x01800000 }; enum SVEContiguousStore_ScalarPlusScalarOp : uint32_t { - SVEContiguousStore_ScalarPlusScalarFixed = 0xE4004000u, - SVEContiguousStore_ScalarPlusScalarFMask = 0xFE00E000u, - SVEContiguousStore_ScalarPlusScalarMask = 0xFF80E000u, + SVEContiguousStore_ScalarPlusScalarFixed = 0xE4004000, + SVEContiguousStore_ScalarPlusScalarFMask = 0xFE00E000, + SVEContiguousStore_ScalarPlusScalarMask = 0xFF80E000, ST1B_z_p_br = SVEContiguousStore_ScalarPlusScalarFixed, - ST1H_z_p_br = SVEContiguousStore_ScalarPlusScalarFixed | 0x00800000u, - ST1W_z_p_br = SVEContiguousStore_ScalarPlusScalarFixed | 0x01000000u, - ST1D_z_p_br = SVEContiguousStore_ScalarPlusScalarFixed | 0x01800000u + ST1H_z_p_br = SVEContiguousStore_ScalarPlusScalarFixed | 0x00800000, + ST1W_z_p_br = SVEContiguousStore_ScalarPlusScalarFixed | 0x01000000, + ST1D_z_p_br = SVEContiguousStore_ScalarPlusScalarFixed | 0x01800000 }; enum SVECopyFPImm_PredicatedOp : uint32_t { - SVECopyFPImm_PredicatedFixed = 0x0510C000u, - SVECopyFPImm_PredicatedFMask = 0xFF30E000u, - SVECopyFPImm_PredicatedMask = 0xFF30E000u, + SVECopyFPImm_PredicatedFixed = 0x0510C000, + SVECopyFPImm_PredicatedFMask = 0xFF30E000, + SVECopyFPImm_PredicatedMask = 0xFF30E000, FCPY_z_p_i = SVECopyFPImm_PredicatedFixed }; enum SVECopyGeneralRegisterToVector_PredicatedOp : uint32_t { - SVECopyGeneralRegisterToVector_PredicatedFixed = 0x0528A000u, - SVECopyGeneralRegisterToVector_PredicatedFMask = 0xFF3FE000u, - SVECopyGeneralRegisterToVector_PredicatedMask = 0xFF3FE000u, + SVECopyGeneralRegisterToVector_PredicatedFixed = 0x0528A000, + SVECopyGeneralRegisterToVector_PredicatedFMask = 0xFF3FE000, + SVECopyGeneralRegisterToVector_PredicatedMask = 0xFF3FE000, CPY_z_p_r = SVECopyGeneralRegisterToVector_PredicatedFixed }; enum SVECopyIntImm_PredicatedOp : uint32_t { - SVECopyIntImm_PredicatedFixed = 0x05100000u, - SVECopyIntImm_PredicatedFMask = 0xFF308000u, - SVECopyIntImm_PredicatedMask = 0xFF308000u, + SVECopyIntImm_PredicatedFixed = 0x05100000, + SVECopyIntImm_PredicatedFMask = 0xFF308000, + SVECopyIntImm_PredicatedMask = 0xFF308000, CPY_z_p_i = SVECopyIntImm_PredicatedFixed }; enum SVECopySIMDFPScalarRegisterToVector_PredicatedOp : uint32_t { - SVECopySIMDFPScalarRegisterToVector_PredicatedFixed = 0x05208000u, - SVECopySIMDFPScalarRegisterToVector_PredicatedFMask = 0xFF3FE000u, - SVECopySIMDFPScalarRegisterToVector_PredicatedMask = 0xFF3FE000u, + SVECopySIMDFPScalarRegisterToVector_PredicatedFixed = 0x05208000, + SVECopySIMDFPScalarRegisterToVector_PredicatedFMask = 0xFF3FE000, + SVECopySIMDFPScalarRegisterToVector_PredicatedMask = 0xFF3FE000, CPY_z_p_v = SVECopySIMDFPScalarRegisterToVector_PredicatedFixed }; enum SVEElementCountOp : uint32_t { - SVEElementCountFixed = 0x0420E000u, - SVEElementCountFMask = 0xFF30F800u, - SVEElementCountMask = 0xFFF0FC00u, + SVEElementCountFixed = 0x0420E000, + SVEElementCountFMask = 0xFF30F800, + SVEElementCountMask = 0xFFF0FC00, CNTB_r_s = SVEElementCountFixed, - CNTH_r_s = SVEElementCountFixed | 0x00400000u, - CNTW_r_s = SVEElementCountFixed | 0x00800000u, - CNTD_r_s = SVEElementCountFixed | 0x00C00000u + CNTH_r_s = SVEElementCountFixed | 0x00400000, + CNTW_r_s = SVEElementCountFixed | 0x00800000, + CNTD_r_s = SVEElementCountFixed | 0x00C00000 }; enum SVEExtractElementToGeneralRegisterOp : uint32_t { - SVEExtractElementToGeneralRegisterFixed = 0x0520A000u, - SVEExtractElementToGeneralRegisterFMask = 0xFF3EE000u, - SVEExtractElementToGeneralRegisterMask = 0xFF3FE000u, + SVEExtractElementToGeneralRegisterFixed = 0x0520A000, + SVEExtractElementToGeneralRegisterFMask = 0xFF3EE000, + SVEExtractElementToGeneralRegisterMask = 0xFF3FE000, LASTA_r_p_z = SVEExtractElementToGeneralRegisterFixed, - LASTB_r_p_z = SVEExtractElementToGeneralRegisterFixed | 0x00010000u + LASTB_r_p_z = SVEExtractElementToGeneralRegisterFixed | 0x00010000 }; enum SVEExtractElementToSIMDFPScalarRegisterOp : uint32_t { - SVEExtractElementToSIMDFPScalarRegisterFixed = 0x05228000u, - SVEExtractElementToSIMDFPScalarRegisterFMask = 0xFF3EE000u, - SVEExtractElementToSIMDFPScalarRegisterMask = 0xFF3FE000u, + SVEExtractElementToSIMDFPScalarRegisterFixed = 0x05228000, + SVEExtractElementToSIMDFPScalarRegisterFMask = 0xFF3EE000, + SVEExtractElementToSIMDFPScalarRegisterMask = 0xFF3FE000, LASTA_v_p_z = SVEExtractElementToSIMDFPScalarRegisterFixed, - LASTB_v_p_z = SVEExtractElementToSIMDFPScalarRegisterFixed | 0x00010000u + LASTB_v_p_z = SVEExtractElementToSIMDFPScalarRegisterFixed | 0x00010000 }; enum SVEFFRInitialiseOp : uint32_t { - SVEFFRInitialiseFixed = 0x252C9000u, - SVEFFRInitialiseFMask = 0xFF3FFFFFu, - SVEFFRInitialiseMask = 0xFFFFFFFFu, + SVEFFRInitialiseFixed = 0x252C9000, + SVEFFRInitialiseFMask = 0xFF3FFFFF, + SVEFFRInitialiseMask = 0xFFFFFFFF, SETFFR_f = SVEFFRInitialiseFixed }; enum SVEFFRWriteFromPredicateOp : uint32_t { - SVEFFRWriteFromPredicateFixed = 0x25289000u, - SVEFFRWriteFromPredicateFMask = 0xFF3FFE1Fu, - SVEFFRWriteFromPredicateMask = 0xFFFFFE1Fu, + SVEFFRWriteFromPredicateFixed = 0x25289000, + SVEFFRWriteFromPredicateFMask = 0xFF3FFE1F, + SVEFFRWriteFromPredicateMask = 0xFFFFFE1F, WRFFR_f_p = SVEFFRWriteFromPredicateFixed }; enum SVEFPAccumulatingReductionOp : uint32_t { - SVEFPAccumulatingReductionFixed = 0x65182000u, - SVEFPAccumulatingReductionFMask = 0xFF38E000u, - SVEFPAccumulatingReductionMask = 0xFF3FE000u, + SVEFPAccumulatingReductionFixed = 0x65182000, + SVEFPAccumulatingReductionFMask = 0xFF38E000, + SVEFPAccumulatingReductionMask = 0xFF3FE000, FADDA_v_p_z = SVEFPAccumulatingReductionFixed }; enum SVEFPArithmeticUnpredicatedOp : uint32_t { - SVEFPArithmeticUnpredicatedFixed = 0x65000000u, - SVEFPArithmeticUnpredicatedFMask = 0xFF20E000u, - SVEFPArithmeticUnpredicatedMask = 0xFF20FC00u, + SVEFPArithmeticUnpredicatedFixed = 0x65000000, + SVEFPArithmeticUnpredicatedFMask = 0xFF20E000, + SVEFPArithmeticUnpredicatedMask = 0xFF20FC00, FADD_z_zz = SVEFPArithmeticUnpredicatedFixed, - FSUB_z_zz = SVEFPArithmeticUnpredicatedFixed | 0x00000400u, - FMUL_z_zz = SVEFPArithmeticUnpredicatedFixed | 0x00000800u, - FTSMUL_z_zz = SVEFPArithmeticUnpredicatedFixed | 0x00000C00u, - FRECPS_z_zz = SVEFPArithmeticUnpredicatedFixed | 0x00001800u, - FRSQRTS_z_zz = SVEFPArithmeticUnpredicatedFixed | 0x00001C00u + FSUB_z_zz = SVEFPArithmeticUnpredicatedFixed | 0x00000400, + FMUL_z_zz = SVEFPArithmeticUnpredicatedFixed | 0x00000800, + FTSMUL_z_zz = SVEFPArithmeticUnpredicatedFixed | 0x00000C00, + FRECPS_z_zz = SVEFPArithmeticUnpredicatedFixed | 0x00001800, + FRSQRTS_z_zz = SVEFPArithmeticUnpredicatedFixed | 0x00001C00 }; enum SVEFPArithmeticWithImm_PredicatedOp : uint32_t { - SVEFPArithmeticWithImm_PredicatedFixed = 0x65188000u, - SVEFPArithmeticWithImm_PredicatedFMask = 0xFF38E3C0u, - SVEFPArithmeticWithImm_PredicatedMask = 0xFF3FE3C0u, + SVEFPArithmeticWithImm_PredicatedFixed = 0x65188000, + SVEFPArithmeticWithImm_PredicatedFMask = 0xFF38E3C0, + SVEFPArithmeticWithImm_PredicatedMask = 0xFF3FE3C0, FADD_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed, - FSUB_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00010000u, - FMUL_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00020000u, - FSUBR_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00030000u, - FMAXNM_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00040000u, - FMINNM_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00050000u, - FMAX_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00060000u, - FMIN_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00070000u + FSUB_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00010000, + FMUL_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00020000, + FSUBR_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00030000, + FMAXNM_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00040000, + FMINNM_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00050000, + FMAX_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00060000, + FMIN_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00070000 }; enum SVEFPArithmetic_PredicatedOp : uint32_t { - SVEFPArithmetic_PredicatedFixed = 0x65008000u, - SVEFPArithmetic_PredicatedFMask = 0xFF30E000u, - SVEFPArithmetic_PredicatedMask = 0xFF3FE000u, + SVEFPArithmetic_PredicatedFixed = 0x65008000, + SVEFPArithmetic_PredicatedFMask = 0xFF30E000, + SVEFPArithmetic_PredicatedMask = 0xFF3FE000, FADD_z_p_zz = SVEFPArithmetic_PredicatedFixed, - FSUB_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00010000u, - FMUL_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00020000u, - FSUBR_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00030000u, - FMAXNM_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00040000u, - FMINNM_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00050000u, - FMAX_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00060000u, - FMIN_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00070000u, - FABD_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00080000u, - FSCALE_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00090000u, - FMULX_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x000A0000u, - FDIVR_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x000C0000u, - FDIV_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x000D0000u + FSUB_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00010000, + FMUL_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00020000, + FSUBR_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00030000, + FMAXNM_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00040000, + FMINNM_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00050000, + FMAX_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00060000, + FMIN_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00070000, + FABD_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00080000, + FSCALE_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00090000, + FMULX_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x000A0000, + FDIVR_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x000C0000, + FDIV_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x000D0000 }; enum SVEFPCompareVectorsOp : uint32_t { - SVEFPCompareVectorsFixed = 0x65004000u, - SVEFPCompareVectorsFMask = 0xFF204000u, - SVEFPCompareVectorsMask = 0xFF20E010u, + SVEFPCompareVectorsFixed = 0x65004000, + SVEFPCompareVectorsFMask = 0xFF204000, + SVEFPCompareVectorsMask = 0xFF20E010, FCMGE_p_p_zz = SVEFPCompareVectorsFixed, - FCMGT_p_p_zz = SVEFPCompareVectorsFixed | 0x00000010u, - FCMEQ_p_p_zz = SVEFPCompareVectorsFixed | 0x00002000u, - FCMNE_p_p_zz = SVEFPCompareVectorsFixed | 0x00002010u, - FCMUO_p_p_zz = SVEFPCompareVectorsFixed | 0x00008000u, - FACGE_p_p_zz = SVEFPCompareVectorsFixed | 0x00008010u, - FACGT_p_p_zz = SVEFPCompareVectorsFixed | 0x0000A010u + FCMGT_p_p_zz = SVEFPCompareVectorsFixed | 0x00000010, + FCMEQ_p_p_zz = SVEFPCompareVectorsFixed | 0x00002000, + FCMNE_p_p_zz = SVEFPCompareVectorsFixed | 0x00002010, + FCMUO_p_p_zz = SVEFPCompareVectorsFixed | 0x00008000, + FACGE_p_p_zz = SVEFPCompareVectorsFixed | 0x00008010, + FACGT_p_p_zz = SVEFPCompareVectorsFixed | 0x0000A010 }; enum SVEFPCompareWithZeroOp : uint32_t { - SVEFPCompareWithZeroFixed = 0x65102000u, - SVEFPCompareWithZeroFMask = 0xFF38E000u, - SVEFPCompareWithZeroMask = 0xFF3FE010u, + SVEFPCompareWithZeroFixed = 0x65102000, + SVEFPCompareWithZeroFMask = 0xFF38E000, + SVEFPCompareWithZeroMask = 0xFF3FE010, FCMGE_p_p_z0 = SVEFPCompareWithZeroFixed, - FCMGT_p_p_z0 = SVEFPCompareWithZeroFixed | 0x00000010u, - FCMLT_p_p_z0 = SVEFPCompareWithZeroFixed | 0x00010000u, - FCMLE_p_p_z0 = SVEFPCompareWithZeroFixed | 0x00010010u, - FCMEQ_p_p_z0 = SVEFPCompareWithZeroFixed | 0x00020000u, - FCMNE_p_p_z0 = SVEFPCompareWithZeroFixed | 0x00030000u + FCMGT_p_p_z0 = SVEFPCompareWithZeroFixed | 0x00000010, + FCMLT_p_p_z0 = SVEFPCompareWithZeroFixed | 0x00010000, + FCMLE_p_p_z0 = SVEFPCompareWithZeroFixed | 0x00010010, + FCMEQ_p_p_z0 = SVEFPCompareWithZeroFixed | 0x00020000, + FCMNE_p_p_z0 = SVEFPCompareWithZeroFixed | 0x00030000 }; enum SVEFPComplexAdditionOp : uint32_t { - SVEFPComplexAdditionFixed = 0x64008000u, - SVEFPComplexAdditionFMask = 0xFF3EE000u, - SVEFPComplexAdditionMask = 0xFF3EE000u, + SVEFPComplexAdditionFixed = 0x64008000, + SVEFPComplexAdditionFMask = 0xFF3EE000, + SVEFPComplexAdditionMask = 0xFF3EE000, FCADD_z_p_zz = SVEFPComplexAdditionFixed }; enum SVEFPComplexMulAddOp : uint32_t { - SVEFPComplexMulAddFixed = 0x64000000u, - SVEFPComplexMulAddFMask = 0xFF208000u, - SVEFPComplexMulAddMask = 0xFF208000u, + SVEFPComplexMulAddFixed = 0x64000000, + SVEFPComplexMulAddFMask = 0xFF208000, + SVEFPComplexMulAddMask = 0xFF208000, FCMLA_z_p_zzz = SVEFPComplexMulAddFixed }; enum SVEFPComplexMulAddIndexOp : uint32_t { - SVEFPComplexMulAddIndexFixed = 0x64201000u, - SVEFPComplexMulAddIndexFMask = 0xFF20F000u, - SVEFPComplexMulAddIndexMask = 0xFFE0F000u, - FCMLA_z_zzzi_h = SVEFPComplexMulAddIndexFixed | 0x00800000u, - FCMLA_z_zzzi_s = SVEFPComplexMulAddIndexFixed | 0x00C00000u + SVEFPComplexMulAddIndexFixed = 0x64201000, + SVEFPComplexMulAddIndexFMask = 0xFF20F000, + SVEFPComplexMulAddIndexMask = 0xFFE0F000, + FCMLA_z_zzzi_h = SVEFPComplexMulAddIndexFixed | 0x00800000, + FCMLA_z_zzzi_s = SVEFPComplexMulAddIndexFixed | 0x00C00000 }; enum SVEFPConvertPrecisionOp : uint32_t { - SVEFPConvertPrecisionFixed = 0x6508A000u, - SVEFPConvertPrecisionFMask = 0xFF3CE000u, - SVEFPConvertPrecisionMask = 0xFFFFE000u, - FCVT_z_p_z_s2h = SVEFPConvertPrecisionFixed | 0x00800000u, - FCVT_z_p_z_h2s = SVEFPConvertPrecisionFixed | 0x00810000u, - FCVT_z_p_z_d2h = SVEFPConvertPrecisionFixed | 0x00C00000u, - FCVT_z_p_z_h2d = SVEFPConvertPrecisionFixed | 0x00C10000u, - FCVT_z_p_z_d2s = SVEFPConvertPrecisionFixed | 0x00C20000u, - FCVT_z_p_z_s2d = SVEFPConvertPrecisionFixed | 0x00C30000u + SVEFPConvertPrecisionFixed = 0x6508A000, + SVEFPConvertPrecisionFMask = 0xFF3CE000, + SVEFPConvertPrecisionMask = 0xFFFFE000, + FCVT_z_p_z_s2h = SVEFPConvertPrecisionFixed | 0x00800000, + FCVT_z_p_z_h2s = SVEFPConvertPrecisionFixed | 0x00810000, + FCVT_z_p_z_d2h = SVEFPConvertPrecisionFixed | 0x00C00000, + FCVT_z_p_z_h2d = SVEFPConvertPrecisionFixed | 0x00C10000, + FCVT_z_p_z_d2s = SVEFPConvertPrecisionFixed | 0x00C20000, + FCVT_z_p_z_s2d = SVEFPConvertPrecisionFixed | 0x00C30000 }; enum SVEFPConvertToIntOp : uint32_t { - SVEFPConvertToIntFixed = 0x6518A000u, - SVEFPConvertToIntFMask = 0xFF38E000u, - SVEFPConvertToIntMask = 0xFFFFE000u, - FCVTZS_z_p_z_fp162h = SVEFPConvertToIntFixed | 0x00420000u, - FCVTZU_z_p_z_fp162h = SVEFPConvertToIntFixed | 0x00430000u, - FCVTZS_z_p_z_fp162w = SVEFPConvertToIntFixed | 0x00440000u, - FCVTZU_z_p_z_fp162w = SVEFPConvertToIntFixed | 0x00450000u, - FCVTZS_z_p_z_fp162x = SVEFPConvertToIntFixed | 0x00460000u, - FCVTZU_z_p_z_fp162x = SVEFPConvertToIntFixed | 0x00470000u, - FCVTZS_z_p_z_s2w = SVEFPConvertToIntFixed | 0x00840000u, - FCVTZU_z_p_z_s2w = SVEFPConvertToIntFixed | 0x00850000u, - FCVTZS_z_p_z_d2w = SVEFPConvertToIntFixed | 0x00C00000u, - FCVTZU_z_p_z_d2w = SVEFPConvertToIntFixed | 0x00C10000u, - FCVTZS_z_p_z_s2x = SVEFPConvertToIntFixed | 0x00C40000u, - FCVTZU_z_p_z_s2x = SVEFPConvertToIntFixed | 0x00C50000u, - FCVTZS_z_p_z_d2x = SVEFPConvertToIntFixed | 0x00C60000u, - FCVTZU_z_p_z_d2x = SVEFPConvertToIntFixed | 0x00C70000u + SVEFPConvertToIntFixed = 0x6518A000, + SVEFPConvertToIntFMask = 0xFF38E000, + SVEFPConvertToIntMask = 0xFFFFE000, + FCVTZS_z_p_z_fp162h = SVEFPConvertToIntFixed | 0x00420000, + FCVTZU_z_p_z_fp162h = SVEFPConvertToIntFixed | 0x00430000, + FCVTZS_z_p_z_fp162w = SVEFPConvertToIntFixed | 0x00440000, + FCVTZU_z_p_z_fp162w = SVEFPConvertToIntFixed | 0x00450000, + FCVTZS_z_p_z_fp162x = SVEFPConvertToIntFixed | 0x00460000, + FCVTZU_z_p_z_fp162x = SVEFPConvertToIntFixed | 0x00470000, + FCVTZS_z_p_z_s2w = SVEFPConvertToIntFixed | 0x00840000, + FCVTZU_z_p_z_s2w = SVEFPConvertToIntFixed | 0x00850000, + FCVTZS_z_p_z_d2w = SVEFPConvertToIntFixed | 0x00C00000, + FCVTZU_z_p_z_d2w = SVEFPConvertToIntFixed | 0x00C10000, + FCVTZS_z_p_z_s2x = SVEFPConvertToIntFixed | 0x00C40000, + FCVTZU_z_p_z_s2x = SVEFPConvertToIntFixed | 0x00C50000, + FCVTZS_z_p_z_d2x = SVEFPConvertToIntFixed | 0x00C60000, + FCVTZU_z_p_z_d2x = SVEFPConvertToIntFixed | 0x00C70000 }; enum SVEFPExponentialAcceleratorOp : uint32_t { - SVEFPExponentialAcceleratorFixed = 0x0420B800u, - SVEFPExponentialAcceleratorFMask = 0xFF20FC00u, - SVEFPExponentialAcceleratorMask = 0xFF3FFC00u, + SVEFPExponentialAcceleratorFixed = 0x0420B800, + SVEFPExponentialAcceleratorFMask = 0xFF20FC00, + SVEFPExponentialAcceleratorMask = 0xFF3FFC00, FEXPA_z_z = SVEFPExponentialAcceleratorFixed }; enum SVEFPFastReductionOp : uint32_t { - SVEFPFastReductionFixed = 0x65002000u, - SVEFPFastReductionFMask = 0xFF38E000u, - SVEFPFastReductionMask = 0xFF3FE000u, + SVEFPFastReductionFixed = 0x65002000, + SVEFPFastReductionFMask = 0xFF38E000, + SVEFPFastReductionMask = 0xFF3FE000, FADDV_v_p_z = SVEFPFastReductionFixed, - FMAXNMV_v_p_z = SVEFPFastReductionFixed | 0x00040000u, - FMINNMV_v_p_z = SVEFPFastReductionFixed | 0x00050000u, - FMAXV_v_p_z = SVEFPFastReductionFixed | 0x00060000u, - FMINV_v_p_z = SVEFPFastReductionFixed | 0x00070000u + FMAXNMV_v_p_z = SVEFPFastReductionFixed | 0x00040000, + FMINNMV_v_p_z = SVEFPFastReductionFixed | 0x00050000, + FMAXV_v_p_z = SVEFPFastReductionFixed | 0x00060000, + FMINV_v_p_z = SVEFPFastReductionFixed | 0x00070000 }; enum SVEFPMulAddOp : uint32_t { - SVEFPMulAddFixed = 0x65200000u, - SVEFPMulAddFMask = 0xFF200000u, - SVEFPMulAddMask = 0xFF20E000u, + SVEFPMulAddFixed = 0x65200000, + SVEFPMulAddFMask = 0xFF200000, + SVEFPMulAddMask = 0xFF20E000, FMLA_z_p_zzz = SVEFPMulAddFixed, - FMLS_z_p_zzz = SVEFPMulAddFixed | 0x00002000u, - FNMLA_z_p_zzz = SVEFPMulAddFixed | 0x00004000u, - FNMLS_z_p_zzz = SVEFPMulAddFixed | 0x00006000u, - FMAD_z_p_zzz = SVEFPMulAddFixed | 0x00008000u, - FMSB_z_p_zzz = SVEFPMulAddFixed | 0x0000A000u, - FNMAD_z_p_zzz = SVEFPMulAddFixed | 0x0000C000u, - FNMSB_z_p_zzz = SVEFPMulAddFixed | 0x0000E000u + FMLS_z_p_zzz = SVEFPMulAddFixed | 0x00002000, + FNMLA_z_p_zzz = SVEFPMulAddFixed | 0x00004000, + FNMLS_z_p_zzz = SVEFPMulAddFixed | 0x00006000, + FMAD_z_p_zzz = SVEFPMulAddFixed | 0x00008000, + FMSB_z_p_zzz = SVEFPMulAddFixed | 0x0000A000, + FNMAD_z_p_zzz = SVEFPMulAddFixed | 0x0000C000, + FNMSB_z_p_zzz = SVEFPMulAddFixed | 0x0000E000 }; enum SVEFPMulAddIndexOp : uint32_t { - SVEFPMulAddIndexFixed = 0x64200000u, - SVEFPMulAddIndexFMask = 0xFF20F800u, - SVEFPMulAddIndexMask = 0xFFE0FC00u, + SVEFPMulAddIndexFixed = 0x64200000, + SVEFPMulAddIndexFMask = 0xFF20F800, + SVEFPMulAddIndexMask = 0xFFE0FC00, FMLA_z_zzzi_h = SVEFPMulAddIndexFixed, - FMLA_z_zzzi_h_i3h = FMLA_z_zzzi_h | 0x00400000u, - FMLS_z_zzzi_h = SVEFPMulAddIndexFixed | 0x00000400u, - FMLS_z_zzzi_h_i3h = FMLS_z_zzzi_h | 0x00400000u, - FMLA_z_zzzi_s = SVEFPMulAddIndexFixed | 0x00800000u, - FMLS_z_zzzi_s = SVEFPMulAddIndexFixed | 0x00800400u, - FMLA_z_zzzi_d = SVEFPMulAddIndexFixed | 0x00C00000u, - FMLS_z_zzzi_d = SVEFPMulAddIndexFixed | 0x00C00400u + FMLA_z_zzzi_h_i3h = FMLA_z_zzzi_h | 0x00400000, + FMLS_z_zzzi_h = SVEFPMulAddIndexFixed | 0x00000400, + FMLS_z_zzzi_h_i3h = FMLS_z_zzzi_h | 0x00400000, + FMLA_z_zzzi_s = SVEFPMulAddIndexFixed | 0x00800000, + FMLS_z_zzzi_s = SVEFPMulAddIndexFixed | 0x00800400, + FMLA_z_zzzi_d = SVEFPMulAddIndexFixed | 0x00C00000, + FMLS_z_zzzi_d = SVEFPMulAddIndexFixed | 0x00C00400 }; enum SVEFPMulIndexOp : uint32_t { - SVEFPMulIndexFixed = 0x64202000u, - SVEFPMulIndexFMask = 0xFF20FC00u, - SVEFPMulIndexMask = 0xFFE0FC00u, + SVEFPMulIndexFixed = 0x64202000, + SVEFPMulIndexFMask = 0xFF20FC00, + SVEFPMulIndexMask = 0xFFE0FC00, FMUL_z_zzi_h = SVEFPMulIndexFixed, - FMUL_z_zzi_h_i3h = FMUL_z_zzi_h | 0x00400000u, - FMUL_z_zzi_s = SVEFPMulIndexFixed | 0x00800000u, - FMUL_z_zzi_d = SVEFPMulIndexFixed | 0x00C00000u + FMUL_z_zzi_h_i3h = FMUL_z_zzi_h | 0x00400000, + FMUL_z_zzi_s = SVEFPMulIndexFixed | 0x00800000, + FMUL_z_zzi_d = SVEFPMulIndexFixed | 0x00C00000 }; enum SVEFPRoundToIntegralValueOp : uint32_t { - SVEFPRoundToIntegralValueFixed = 0x6500A000u, - SVEFPRoundToIntegralValueFMask = 0xFF38E000u, - SVEFPRoundToIntegralValueMask = 0xFF3FE000u, + SVEFPRoundToIntegralValueFixed = 0x6500A000, + SVEFPRoundToIntegralValueFMask = 0xFF38E000, + SVEFPRoundToIntegralValueMask = 0xFF3FE000, FRINTN_z_p_z = SVEFPRoundToIntegralValueFixed, - FRINTP_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00010000u, - FRINTM_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00020000u, - FRINTZ_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00030000u, - FRINTA_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00040000u, - FRINTX_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00060000u, - FRINTI_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00070000u + FRINTP_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00010000, + FRINTM_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00020000, + FRINTZ_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00030000, + FRINTA_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00040000, + FRINTX_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00060000, + FRINTI_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00070000 }; enum SVEFPTrigMulAddCoefficientOp : uint32_t { - SVEFPTrigMulAddCoefficientFixed = 0x65108000u, - SVEFPTrigMulAddCoefficientFMask = 0xFF38FC00u, - SVEFPTrigMulAddCoefficientMask = 0xFF38FC00u, + SVEFPTrigMulAddCoefficientFixed = 0x65108000, + SVEFPTrigMulAddCoefficientFMask = 0xFF38FC00, + SVEFPTrigMulAddCoefficientMask = 0xFF38FC00, FTMAD_z_zzi = SVEFPTrigMulAddCoefficientFixed }; enum SVEFPTrigSelectCoefficientOp : uint32_t { - SVEFPTrigSelectCoefficientFixed = 0x0420B000u, - SVEFPTrigSelectCoefficientFMask = 0xFF20F800u, - SVEFPTrigSelectCoefficientMask = 0xFF20FC00u, + SVEFPTrigSelectCoefficientFixed = 0x0420B000, + SVEFPTrigSelectCoefficientFMask = 0xFF20F800, + SVEFPTrigSelectCoefficientMask = 0xFF20FC00, FTSSEL_z_zz = SVEFPTrigSelectCoefficientFixed }; enum SVEFPUnaryOpOp : uint32_t { - SVEFPUnaryOpFixed = 0x650CA000u, - SVEFPUnaryOpFMask = 0xFF3CE000u, - SVEFPUnaryOpMask = 0xFF3FE000u, + SVEFPUnaryOpFixed = 0x650CA000, + SVEFPUnaryOpFMask = 0xFF3CE000, + SVEFPUnaryOpMask = 0xFF3FE000, FRECPX_z_p_z = SVEFPUnaryOpFixed, - FSQRT_z_p_z = SVEFPUnaryOpFixed | 0x00010000u + FSQRT_z_p_z = SVEFPUnaryOpFixed | 0x00010000 }; enum SVEFPUnaryOpUnpredicatedOp : uint32_t { - SVEFPUnaryOpUnpredicatedFixed = 0x65083000u, - SVEFPUnaryOpUnpredicatedFMask = 0xFF38F000u, - SVEFPUnaryOpUnpredicatedMask = 0xFF3FFC00u, - FRECPE_z_z = SVEFPUnaryOpUnpredicatedFixed | 0x00060000u, - FRSQRTE_z_z = SVEFPUnaryOpUnpredicatedFixed | 0x00070000u + SVEFPUnaryOpUnpredicatedFixed = 0x65083000, + SVEFPUnaryOpUnpredicatedFMask = 0xFF38F000, + SVEFPUnaryOpUnpredicatedMask = 0xFF3FFC00, + FRECPE_z_z = SVEFPUnaryOpUnpredicatedFixed | 0x00060000, + FRSQRTE_z_z = SVEFPUnaryOpUnpredicatedFixed | 0x00070000 }; enum SVEIncDecByPredicateCountOp : uint32_t { - SVEIncDecByPredicateCountFixed = 0x25288000u, - SVEIncDecByPredicateCountFMask = 0xFF38F000u, - SVEIncDecByPredicateCountMask = 0xFF3FFE00u, + SVEIncDecByPredicateCountFixed = 0x25288000, + SVEIncDecByPredicateCountFMask = 0xFF38F000, + SVEIncDecByPredicateCountMask = 0xFF3FFE00, SQINCP_z_p_z = SVEIncDecByPredicateCountFixed, - SQINCP_r_p_r_sx = SVEIncDecByPredicateCountFixed | 0x00000800u, - SQINCP_r_p_r_x = SVEIncDecByPredicateCountFixed | 0x00000C00u, - UQINCP_z_p_z = SVEIncDecByPredicateCountFixed | 0x00010000u, - UQINCP_r_p_r_uw = SVEIncDecByPredicateCountFixed | 0x00010800u, - UQINCP_r_p_r_x = SVEIncDecByPredicateCountFixed | 0x00010C00u, - SQDECP_z_p_z = SVEIncDecByPredicateCountFixed | 0x00020000u, - SQDECP_r_p_r_sx = SVEIncDecByPredicateCountFixed | 0x00020800u, - SQDECP_r_p_r_x = SVEIncDecByPredicateCountFixed | 0x00020C00u, - UQDECP_z_p_z = SVEIncDecByPredicateCountFixed | 0x00030000u, - UQDECP_r_p_r_uw = SVEIncDecByPredicateCountFixed | 0x00030800u, - UQDECP_r_p_r_x = SVEIncDecByPredicateCountFixed | 0x00030C00u, - INCP_z_p_z = SVEIncDecByPredicateCountFixed | 0x00040000u, - INCP_r_p_r = SVEIncDecByPredicateCountFixed | 0x00040800u, - DECP_z_p_z = SVEIncDecByPredicateCountFixed | 0x00050000u, - DECP_r_p_r = SVEIncDecByPredicateCountFixed | 0x00050800u + SQINCP_r_p_r_sx = SVEIncDecByPredicateCountFixed | 0x00000800, + SQINCP_r_p_r_x = SVEIncDecByPredicateCountFixed | 0x00000C00, + UQINCP_z_p_z = SVEIncDecByPredicateCountFixed | 0x00010000, + UQINCP_r_p_r_uw = SVEIncDecByPredicateCountFixed | 0x00010800, + UQINCP_r_p_r_x = SVEIncDecByPredicateCountFixed | 0x00010C00, + SQDECP_z_p_z = SVEIncDecByPredicateCountFixed | 0x00020000, + SQDECP_r_p_r_sx = SVEIncDecByPredicateCountFixed | 0x00020800, + SQDECP_r_p_r_x = SVEIncDecByPredicateCountFixed | 0x00020C00, + UQDECP_z_p_z = SVEIncDecByPredicateCountFixed | 0x00030000, + UQDECP_r_p_r_uw = SVEIncDecByPredicateCountFixed | 0x00030800, + UQDECP_r_p_r_x = SVEIncDecByPredicateCountFixed | 0x00030C00, + INCP_z_p_z = SVEIncDecByPredicateCountFixed | 0x00040000, + INCP_r_p_r = SVEIncDecByPredicateCountFixed | 0x00040800, + DECP_z_p_z = SVEIncDecByPredicateCountFixed | 0x00050000, + DECP_r_p_r = SVEIncDecByPredicateCountFixed | 0x00050800 }; enum SVEIncDecRegisterByElementCountOp : uint32_t { - SVEIncDecRegisterByElementCountFixed = 0x0430E000u, - SVEIncDecRegisterByElementCountFMask = 0xFF30F800u, - SVEIncDecRegisterByElementCountMask = 0xFFF0FC00u, + SVEIncDecRegisterByElementCountFixed = 0x0430E000, + SVEIncDecRegisterByElementCountFMask = 0xFF30F800, + SVEIncDecRegisterByElementCountMask = 0xFFF0FC00, INCB_r_rs = SVEIncDecRegisterByElementCountFixed, - DECB_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00000400u, - INCH_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00400000u, - DECH_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00400400u, - INCW_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00800000u, - DECW_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00800400u, - INCD_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00C00000u, - DECD_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00C00400u + DECB_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00000400, + INCH_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00400000, + DECH_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00400400, + INCW_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00800000, + DECW_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00800400, + INCD_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00C00000, + DECD_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00C00400 }; enum SVEIncDecVectorByElementCountOp : uint32_t { - SVEIncDecVectorByElementCountFixed = 0x0430C000u, - SVEIncDecVectorByElementCountFMask = 0xFF30F800u, - SVEIncDecVectorByElementCountMask = 0xFFF0FC00u, - INCH_z_zs = SVEIncDecVectorByElementCountFixed | 0x00400000u, - DECH_z_zs = SVEIncDecVectorByElementCountFixed | 0x00400400u, - INCW_z_zs = SVEIncDecVectorByElementCountFixed | 0x00800000u, - DECW_z_zs = SVEIncDecVectorByElementCountFixed | 0x00800400u, - INCD_z_zs = SVEIncDecVectorByElementCountFixed | 0x00C00000u, - DECD_z_zs = SVEIncDecVectorByElementCountFixed | 0x00C00400u + SVEIncDecVectorByElementCountFixed = 0x0430C000, + SVEIncDecVectorByElementCountFMask = 0xFF30F800, + SVEIncDecVectorByElementCountMask = 0xFFF0FC00, + INCH_z_zs = SVEIncDecVectorByElementCountFixed | 0x00400000, + DECH_z_zs = SVEIncDecVectorByElementCountFixed | 0x00400400, + INCW_z_zs = SVEIncDecVectorByElementCountFixed | 0x00800000, + DECW_z_zs = SVEIncDecVectorByElementCountFixed | 0x00800400, + INCD_z_zs = SVEIncDecVectorByElementCountFixed | 0x00C00000, + DECD_z_zs = SVEIncDecVectorByElementCountFixed | 0x00C00400 }; enum SVEIndexGenerationOp : uint32_t { - SVEIndexGenerationFixed = 0x04204000u, - SVEIndexGenerationFMask = 0xFF20F000u, - SVEIndexGenerationMask = 0xFF20FC00u, + SVEIndexGenerationFixed = 0x04204000, + SVEIndexGenerationFMask = 0xFF20F000, + SVEIndexGenerationMask = 0xFF20FC00, INDEX_z_ii = SVEIndexGenerationFixed, - INDEX_z_ri = SVEIndexGenerationFixed | 0x00000400u, - INDEX_z_ir = SVEIndexGenerationFixed | 0x00000800u, - INDEX_z_rr = SVEIndexGenerationFixed | 0x00000C00u + INDEX_z_ri = SVEIndexGenerationFixed | 0x00000400, + INDEX_z_ir = SVEIndexGenerationFixed | 0x00000800, + INDEX_z_rr = SVEIndexGenerationFixed | 0x00000C00 }; enum SVEInsertGeneralRegisterOp : uint32_t { - SVEInsertGeneralRegisterFixed = 0x05243800u, - SVEInsertGeneralRegisterFMask = 0xFF3FFC00u, - SVEInsertGeneralRegisterMask = 0xFF3FFC00u, + SVEInsertGeneralRegisterFixed = 0x05243800, + SVEInsertGeneralRegisterFMask = 0xFF3FFC00, + SVEInsertGeneralRegisterMask = 0xFF3FFC00, INSR_z_r = SVEInsertGeneralRegisterFixed }; enum SVEInsertSIMDFPScalarRegisterOp : uint32_t { - SVEInsertSIMDFPScalarRegisterFixed = 0x05343800u, - SVEInsertSIMDFPScalarRegisterFMask = 0xFF3FFC00u, - SVEInsertSIMDFPScalarRegisterMask = 0xFF3FFC00u, + SVEInsertSIMDFPScalarRegisterFixed = 0x05343800, + SVEInsertSIMDFPScalarRegisterFMask = 0xFF3FFC00, + SVEInsertSIMDFPScalarRegisterMask = 0xFF3FFC00, INSR_z_v = SVEInsertSIMDFPScalarRegisterFixed }; enum SVEIntAddSubtractImm_UnpredicatedOp : uint32_t { - SVEIntAddSubtractImm_UnpredicatedFixed = 0x2520C000u, - SVEIntAddSubtractImm_UnpredicatedFMask = 0xFF38C000u, - SVEIntAddSubtractImm_UnpredicatedMask = 0xFF3FC000u, + SVEIntAddSubtractImm_UnpredicatedFixed = 0x2520C000, + SVEIntAddSubtractImm_UnpredicatedFMask = 0xFF38C000, + SVEIntAddSubtractImm_UnpredicatedMask = 0xFF3FC000, ADD_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed, - SUB_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00010000u, - SUBR_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00030000u, - SQADD_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00040000u, - UQADD_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00050000u, - SQSUB_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00060000u, - UQSUB_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00070000u + SUB_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00010000, + SUBR_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00030000, + SQADD_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00040000, + UQADD_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00050000, + SQSUB_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00060000, + UQSUB_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00070000 }; enum SVEIntAddSubtractVectors_PredicatedOp : uint32_t { - SVEIntAddSubtractVectors_PredicatedFixed = 0x04000000u, - SVEIntAddSubtractVectors_PredicatedFMask = 0xFF38E000u, - SVEIntAddSubtractVectors_PredicatedMask = 0xFF3FE000u, + SVEIntAddSubtractVectors_PredicatedFixed = 0x04000000, + SVEIntAddSubtractVectors_PredicatedFMask = 0xFF38E000, + SVEIntAddSubtractVectors_PredicatedMask = 0xFF3FE000, ADD_z_p_zz = SVEIntAddSubtractVectors_PredicatedFixed, - SUB_z_p_zz = SVEIntAddSubtractVectors_PredicatedFixed | 0x00010000u, - SUBR_z_p_zz = SVEIntAddSubtractVectors_PredicatedFixed | 0x00030000u + SUB_z_p_zz = SVEIntAddSubtractVectors_PredicatedFixed | 0x00010000, + SUBR_z_p_zz = SVEIntAddSubtractVectors_PredicatedFixed | 0x00030000 }; enum SVEIntArithmeticUnpredicatedOp : uint32_t { - SVEIntArithmeticUnpredicatedFixed = 0x04200000u, - SVEIntArithmeticUnpredicatedFMask = 0xFF20E000u, - SVEIntArithmeticUnpredicatedMask = 0xFF20FC00u, + SVEIntArithmeticUnpredicatedFixed = 0x04200000, + SVEIntArithmeticUnpredicatedFMask = 0xFF20E000, + SVEIntArithmeticUnpredicatedMask = 0xFF20FC00, ADD_z_zz = SVEIntArithmeticUnpredicatedFixed, - SUB_z_zz = SVEIntArithmeticUnpredicatedFixed | 0x00000400u, - SQADD_z_zz = SVEIntArithmeticUnpredicatedFixed | 0x00001000u, - UQADD_z_zz = SVEIntArithmeticUnpredicatedFixed | 0x00001400u, - SQSUB_z_zz = SVEIntArithmeticUnpredicatedFixed | 0x00001800u, - UQSUB_z_zz = SVEIntArithmeticUnpredicatedFixed | 0x00001C00u + SUB_z_zz = SVEIntArithmeticUnpredicatedFixed | 0x00000400, + SQADD_z_zz = SVEIntArithmeticUnpredicatedFixed | 0x00001000, + UQADD_z_zz = SVEIntArithmeticUnpredicatedFixed | 0x00001400, + SQSUB_z_zz = SVEIntArithmeticUnpredicatedFixed | 0x00001800, + UQSUB_z_zz = SVEIntArithmeticUnpredicatedFixed | 0x00001C00 }; enum SVEIntCompareScalarCountAndLimitOp : uint32_t { - SVEIntCompareScalarCountAndLimitFixed = 0x25200000u, - SVEIntCompareScalarCountAndLimitFMask = 0xFF20E000u, - SVEIntCompareScalarCountAndLimitMask = 0xFF20EC10u, - WHILELT_p_p_rr = SVEIntCompareScalarCountAndLimitFixed | 0x00000400u, - WHILELE_p_p_rr = SVEIntCompareScalarCountAndLimitFixed | 0x00000410u, - WHILELO_p_p_rr = SVEIntCompareScalarCountAndLimitFixed | 0x00000C00u, - WHILELS_p_p_rr = SVEIntCompareScalarCountAndLimitFixed | 0x00000C10u + SVEIntCompareScalarCountAndLimitFixed = 0x25200000, + SVEIntCompareScalarCountAndLimitFMask = 0xFF20E000, + SVEIntCompareScalarCountAndLimitMask = 0xFF20EC10, + WHILELT_p_p_rr = SVEIntCompareScalarCountAndLimitFixed | 0x00000400, + WHILELE_p_p_rr = SVEIntCompareScalarCountAndLimitFixed | 0x00000410, + WHILELO_p_p_rr = SVEIntCompareScalarCountAndLimitFixed | 0x00000C00, + WHILELS_p_p_rr = SVEIntCompareScalarCountAndLimitFixed | 0x00000C10 }; enum SVEIntCompareSignedImmOp : uint32_t { - SVEIntCompareSignedImmFixed = 0x25000000u, - SVEIntCompareSignedImmFMask = 0xFF204000u, - SVEIntCompareSignedImmMask = 0xFF20E010u, + SVEIntCompareSignedImmFixed = 0x25000000, + SVEIntCompareSignedImmFMask = 0xFF204000, + SVEIntCompareSignedImmMask = 0xFF20E010, CMPGE_p_p_zi = SVEIntCompareSignedImmFixed, - CMPGT_p_p_zi = SVEIntCompareSignedImmFixed | 0x00000010u, - CMPLT_p_p_zi = SVEIntCompareSignedImmFixed | 0x00002000u, - CMPLE_p_p_zi = SVEIntCompareSignedImmFixed | 0x00002010u, - CMPEQ_p_p_zi = SVEIntCompareSignedImmFixed | 0x00008000u, - CMPNE_p_p_zi = SVEIntCompareSignedImmFixed | 0x00008010u + CMPGT_p_p_zi = SVEIntCompareSignedImmFixed | 0x00000010, + CMPLT_p_p_zi = SVEIntCompareSignedImmFixed | 0x00002000, + CMPLE_p_p_zi = SVEIntCompareSignedImmFixed | 0x00002010, + CMPEQ_p_p_zi = SVEIntCompareSignedImmFixed | 0x00008000, + CMPNE_p_p_zi = SVEIntCompareSignedImmFixed | 0x00008010 }; enum SVEIntCompareUnsignedImmOp : uint32_t { - SVEIntCompareUnsignedImmFixed = 0x24200000u, - SVEIntCompareUnsignedImmFMask = 0xFF200000u, - SVEIntCompareUnsignedImmMask = 0xFF202010u, + SVEIntCompareUnsignedImmFixed = 0x24200000, + SVEIntCompareUnsignedImmFMask = 0xFF200000, + SVEIntCompareUnsignedImmMask = 0xFF202010, CMPHS_p_p_zi = SVEIntCompareUnsignedImmFixed, - CMPHI_p_p_zi = SVEIntCompareUnsignedImmFixed | 0x00000010u, - CMPLO_p_p_zi = SVEIntCompareUnsignedImmFixed | 0x00002000u, - CMPLS_p_p_zi = SVEIntCompareUnsignedImmFixed | 0x00002010u + CMPHI_p_p_zi = SVEIntCompareUnsignedImmFixed | 0x00000010, + CMPLO_p_p_zi = SVEIntCompareUnsignedImmFixed | 0x00002000, + CMPLS_p_p_zi = SVEIntCompareUnsignedImmFixed | 0x00002010 }; enum SVEIntCompareVectorsOp : uint32_t { - SVEIntCompareVectorsFixed = 0x24000000u, - SVEIntCompareVectorsFMask = 0xFF200000u, - SVEIntCompareVectorsMask = 0xFF20E010u, + SVEIntCompareVectorsFixed = 0x24000000, + SVEIntCompareVectorsFMask = 0xFF200000, + SVEIntCompareVectorsMask = 0xFF20E010, CMPHS_p_p_zz = SVEIntCompareVectorsFixed, - CMPHI_p_p_zz = SVEIntCompareVectorsFixed | 0x00000010u, - CMPEQ_p_p_zw = SVEIntCompareVectorsFixed | 0x00002000u, - CMPNE_p_p_zw = SVEIntCompareVectorsFixed | 0x00002010u, - CMPGE_p_p_zw = SVEIntCompareVectorsFixed | 0x00004000u, - CMPGT_p_p_zw = SVEIntCompareVectorsFixed | 0x00004010u, - CMPLT_p_p_zw = SVEIntCompareVectorsFixed | 0x00006000u, - CMPLE_p_p_zw = SVEIntCompareVectorsFixed | 0x00006010u, - CMPGE_p_p_zz = SVEIntCompareVectorsFixed | 0x00008000u, - CMPGT_p_p_zz = SVEIntCompareVectorsFixed | 0x00008010u, - CMPEQ_p_p_zz = SVEIntCompareVectorsFixed | 0x0000A000u, - CMPNE_p_p_zz = SVEIntCompareVectorsFixed | 0x0000A010u, - CMPHS_p_p_zw = SVEIntCompareVectorsFixed | 0x0000C000u, - CMPHI_p_p_zw = SVEIntCompareVectorsFixed | 0x0000C010u, - CMPLO_p_p_zw = SVEIntCompareVectorsFixed | 0x0000E000u, - CMPLS_p_p_zw = SVEIntCompareVectorsFixed | 0x0000E010u + CMPHI_p_p_zz = SVEIntCompareVectorsFixed | 0x00000010, + CMPEQ_p_p_zw = SVEIntCompareVectorsFixed | 0x00002000, + CMPNE_p_p_zw = SVEIntCompareVectorsFixed | 0x00002010, + CMPGE_p_p_zw = SVEIntCompareVectorsFixed | 0x00004000, + CMPGT_p_p_zw = SVEIntCompareVectorsFixed | 0x00004010, + CMPLT_p_p_zw = SVEIntCompareVectorsFixed | 0x00006000, + CMPLE_p_p_zw = SVEIntCompareVectorsFixed | 0x00006010, + CMPGE_p_p_zz = SVEIntCompareVectorsFixed | 0x00008000, + CMPGT_p_p_zz = SVEIntCompareVectorsFixed | 0x00008010, + CMPEQ_p_p_zz = SVEIntCompareVectorsFixed | 0x0000A000, + CMPNE_p_p_zz = SVEIntCompareVectorsFixed | 0x0000A010, + CMPHS_p_p_zw = SVEIntCompareVectorsFixed | 0x0000C000, + CMPHI_p_p_zw = SVEIntCompareVectorsFixed | 0x0000C010, + CMPLO_p_p_zw = SVEIntCompareVectorsFixed | 0x0000E000, + CMPLS_p_p_zw = SVEIntCompareVectorsFixed | 0x0000E010 }; enum SVEIntConvertToFPOp : uint32_t { - SVEIntConvertToFPFixed = 0x6510A000u, - SVEIntConvertToFPFMask = 0xFF38E000u, - SVEIntConvertToFPMask = 0xFFFFE000u, - SCVTF_z_p_z_h2fp16 = SVEIntConvertToFPFixed | 0x00420000u, - UCVTF_z_p_z_h2fp16 = SVEIntConvertToFPFixed | 0x00430000u, - SCVTF_z_p_z_w2fp16 = SVEIntConvertToFPFixed | 0x00440000u, - UCVTF_z_p_z_w2fp16 = SVEIntConvertToFPFixed | 0x00450000u, - SCVTF_z_p_z_x2fp16 = SVEIntConvertToFPFixed | 0x00460000u, - UCVTF_z_p_z_x2fp16 = SVEIntConvertToFPFixed | 0x00470000u, - SCVTF_z_p_z_w2s = SVEIntConvertToFPFixed | 0x00840000u, - UCVTF_z_p_z_w2s = SVEIntConvertToFPFixed | 0x00850000u, - SCVTF_z_p_z_w2d = SVEIntConvertToFPFixed | 0x00C00000u, - UCVTF_z_p_z_w2d = SVEIntConvertToFPFixed | 0x00C10000u, - SCVTF_z_p_z_x2s = SVEIntConvertToFPFixed | 0x00C40000u, - UCVTF_z_p_z_x2s = SVEIntConvertToFPFixed | 0x00C50000u, - SCVTF_z_p_z_x2d = SVEIntConvertToFPFixed | 0x00C60000u, - UCVTF_z_p_z_x2d = SVEIntConvertToFPFixed | 0x00C70000u + SVEIntConvertToFPFixed = 0x6510A000, + SVEIntConvertToFPFMask = 0xFF38E000, + SVEIntConvertToFPMask = 0xFFFFE000, + SCVTF_z_p_z_h2fp16 = SVEIntConvertToFPFixed | 0x00420000, + UCVTF_z_p_z_h2fp16 = SVEIntConvertToFPFixed | 0x00430000, + SCVTF_z_p_z_w2fp16 = SVEIntConvertToFPFixed | 0x00440000, + UCVTF_z_p_z_w2fp16 = SVEIntConvertToFPFixed | 0x00450000, + SCVTF_z_p_z_x2fp16 = SVEIntConvertToFPFixed | 0x00460000, + UCVTF_z_p_z_x2fp16 = SVEIntConvertToFPFixed | 0x00470000, + SCVTF_z_p_z_w2s = SVEIntConvertToFPFixed | 0x00840000, + UCVTF_z_p_z_w2s = SVEIntConvertToFPFixed | 0x00850000, + SCVTF_z_p_z_w2d = SVEIntConvertToFPFixed | 0x00C00000, + UCVTF_z_p_z_w2d = SVEIntConvertToFPFixed | 0x00C10000, + SCVTF_z_p_z_x2s = SVEIntConvertToFPFixed | 0x00C40000, + UCVTF_z_p_z_x2s = SVEIntConvertToFPFixed | 0x00C50000, + SCVTF_z_p_z_x2d = SVEIntConvertToFPFixed | 0x00C60000, + UCVTF_z_p_z_x2d = SVEIntConvertToFPFixed | 0x00C70000 }; enum SVEIntDivideVectors_PredicatedOp : uint32_t { - SVEIntDivideVectors_PredicatedFixed = 0x04140000u, - SVEIntDivideVectors_PredicatedFMask = 0xFF3CE000u, - SVEIntDivideVectors_PredicatedMask = 0xFF3FE000u, + SVEIntDivideVectors_PredicatedFixed = 0x04140000, + SVEIntDivideVectors_PredicatedFMask = 0xFF3CE000, + SVEIntDivideVectors_PredicatedMask = 0xFF3FE000, SDIV_z_p_zz = SVEIntDivideVectors_PredicatedFixed, - UDIV_z_p_zz = SVEIntDivideVectors_PredicatedFixed | 0x00010000u, - SDIVR_z_p_zz = SVEIntDivideVectors_PredicatedFixed | 0x00020000u, - UDIVR_z_p_zz = SVEIntDivideVectors_PredicatedFixed | 0x00030000u + UDIV_z_p_zz = SVEIntDivideVectors_PredicatedFixed | 0x00010000, + SDIVR_z_p_zz = SVEIntDivideVectors_PredicatedFixed | 0x00020000, + UDIVR_z_p_zz = SVEIntDivideVectors_PredicatedFixed | 0x00030000 }; enum SVEIntMinMaxDifference_PredicatedOp : uint32_t { - SVEIntMinMaxDifference_PredicatedFixed = 0x04080000u, - SVEIntMinMaxDifference_PredicatedFMask = 0xFF38E000u, - SVEIntMinMaxDifference_PredicatedMask = 0xFF3FE000u, + SVEIntMinMaxDifference_PredicatedFixed = 0x04080000, + SVEIntMinMaxDifference_PredicatedFMask = 0xFF38E000, + SVEIntMinMaxDifference_PredicatedMask = 0xFF3FE000, SMAX_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed, - UMAX_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed | 0x00010000u, - SMIN_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed | 0x00020000u, - UMIN_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed | 0x00030000u, - SABD_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed | 0x00040000u, - UABD_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed | 0x00050000u + UMAX_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed | 0x00010000, + SMIN_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed | 0x00020000, + UMIN_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed | 0x00030000, + SABD_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed | 0x00040000, + UABD_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed | 0x00050000 }; enum SVEIntMinMaxImm_UnpredicatedOp : uint32_t { - SVEIntMinMaxImm_UnpredicatedFixed = 0x2528C000u, - SVEIntMinMaxImm_UnpredicatedFMask = 0xFF38C000u, - SVEIntMinMaxImm_UnpredicatedMask = 0xFF3FE000u, + SVEIntMinMaxImm_UnpredicatedFixed = 0x2528C000, + SVEIntMinMaxImm_UnpredicatedFMask = 0xFF38C000, + SVEIntMinMaxImm_UnpredicatedMask = 0xFF3FE000, SMAX_z_zi = SVEIntMinMaxImm_UnpredicatedFixed, - UMAX_z_zi = SVEIntMinMaxImm_UnpredicatedFixed | 0x00010000u, - SMIN_z_zi = SVEIntMinMaxImm_UnpredicatedFixed | 0x00020000u, - UMIN_z_zi = SVEIntMinMaxImm_UnpredicatedFixed | 0x00030000u + UMAX_z_zi = SVEIntMinMaxImm_UnpredicatedFixed | 0x00010000, + SMIN_z_zi = SVEIntMinMaxImm_UnpredicatedFixed | 0x00020000, + UMIN_z_zi = SVEIntMinMaxImm_UnpredicatedFixed | 0x00030000 }; enum SVEIntMulAddPredicatedOp : uint32_t { - SVEIntMulAddPredicatedFixed = 0x04004000u, - SVEIntMulAddPredicatedFMask = 0xFF204000u, - SVEIntMulAddPredicatedMask = 0xFF20E000u, + SVEIntMulAddPredicatedFixed = 0x04004000, + SVEIntMulAddPredicatedFMask = 0xFF204000, + SVEIntMulAddPredicatedMask = 0xFF20E000, MLA_z_p_zzz = SVEIntMulAddPredicatedFixed, - MLS_z_p_zzz = SVEIntMulAddPredicatedFixed | 0x00002000u, - MAD_z_p_zzz = SVEIntMulAddPredicatedFixed | 0x00008000u, - MSB_z_p_zzz = SVEIntMulAddPredicatedFixed | 0x0000A000u + MLS_z_p_zzz = SVEIntMulAddPredicatedFixed | 0x00002000, + MAD_z_p_zzz = SVEIntMulAddPredicatedFixed | 0x00008000, + MSB_z_p_zzz = SVEIntMulAddPredicatedFixed | 0x0000A000 }; enum SVEIntMulAddUnpredicatedOp : uint32_t { - SVEIntMulAddUnpredicatedFixed = 0x44000000u, - SVEIntMulAddUnpredicatedFMask = 0xFF208000u, - SVEIntMulAddUnpredicatedMask = 0xFF20FC00u, + SVEIntMulAddUnpredicatedFixed = 0x44000000, + SVEIntMulAddUnpredicatedFMask = 0xFF208000, + SVEIntMulAddUnpredicatedMask = 0xFF20FC00, SDOT_z_zzz = SVEIntMulAddUnpredicatedFixed, - UDOT_z_zzz = SVEIntMulAddUnpredicatedFixed | 0x00000400u + UDOT_z_zzz = SVEIntMulAddUnpredicatedFixed | 0x00000400 }; enum SVEIntMulImm_UnpredicatedOp : uint32_t { - SVEIntMulImm_UnpredicatedFixed = 0x2530C000u, - SVEIntMulImm_UnpredicatedFMask = 0xFF38C000u, - SVEIntMulImm_UnpredicatedMask = 0xFF3FE000u, + SVEIntMulImm_UnpredicatedFixed = 0x2530C000, + SVEIntMulImm_UnpredicatedFMask = 0xFF38C000, + SVEIntMulImm_UnpredicatedMask = 0xFF3FE000, MUL_z_zi = SVEIntMulImm_UnpredicatedFixed }; enum SVEIntMulVectors_PredicatedOp : uint32_t { - SVEIntMulVectors_PredicatedFixed = 0x04100000u, - SVEIntMulVectors_PredicatedFMask = 0xFF3CE000u, - SVEIntMulVectors_PredicatedMask = 0xFF3FE000u, + SVEIntMulVectors_PredicatedFixed = 0x04100000, + SVEIntMulVectors_PredicatedFMask = 0xFF3CE000, + SVEIntMulVectors_PredicatedMask = 0xFF3FE000, MUL_z_p_zz = SVEIntMulVectors_PredicatedFixed, - SMULH_z_p_zz = SVEIntMulVectors_PredicatedFixed | 0x00020000u, - UMULH_z_p_zz = SVEIntMulVectors_PredicatedFixed | 0x00030000u + SMULH_z_p_zz = SVEIntMulVectors_PredicatedFixed | 0x00020000, + UMULH_z_p_zz = SVEIntMulVectors_PredicatedFixed | 0x00030000 }; enum SVEMovprfxOp : uint32_t { - SVEMovprfxFixed = 0x04002000u, - SVEMovprfxFMask = 0xFF20E000u, - SVEMovprfxMask = 0xFF3EE000u, - MOVPRFX_z_p_z = SVEMovprfxFixed | 0x00100000u + SVEMovprfxFixed = 0x04002000, + SVEMovprfxFMask = 0xFF20E000, + SVEMovprfxMask = 0xFF3EE000, + MOVPRFX_z_p_z = SVEMovprfxFixed | 0x00100000 }; enum SVEIntReductionOp : uint32_t { - SVEIntReductionFixed = 0x04002000u, - SVEIntReductionFMask = 0xFF20E000u, - SVEIntReductionMask = 0xFF3FE000u, + SVEIntReductionFixed = 0x04002000, + SVEIntReductionFMask = 0xFF20E000, + SVEIntReductionMask = 0xFF3FE000, SADDV_r_p_z = SVEIntReductionFixed, - UADDV_r_p_z = SVEIntReductionFixed | 0x00010000u, - SMAXV_r_p_z = SVEIntReductionFixed | 0x00080000u, - UMAXV_r_p_z = SVEIntReductionFixed | 0x00090000u, - SMINV_r_p_z = SVEIntReductionFixed | 0x000A0000u, - UMINV_r_p_z = SVEIntReductionFixed | 0x000B0000u + UADDV_r_p_z = SVEIntReductionFixed | 0x00010000, + SMAXV_r_p_z = SVEIntReductionFixed | 0x00080000, + UMAXV_r_p_z = SVEIntReductionFixed | 0x00090000, + SMINV_r_p_z = SVEIntReductionFixed | 0x000A0000, + UMINV_r_p_z = SVEIntReductionFixed | 0x000B0000 }; enum SVEIntReductionLogicalOp : uint32_t { - SVEIntReductionLogicalFixed = 0x04182000u, - SVEIntReductionLogicalFMask = 0xFF38E000u, - SVEIntReductionLogicalMask = 0xFF3FE000u, - ORV_r_p_z = SVEIntReductionLogicalFixed | 0x00180000u, - EORV_r_p_z = SVEIntReductionLogicalFixed | 0x00190000u, - ANDV_r_p_z = SVEIntReductionLogicalFixed | 0x001A0000u + SVEIntReductionLogicalFixed = 0x04182000, + SVEIntReductionLogicalFMask = 0xFF38E000, + SVEIntReductionLogicalMask = 0xFF3FE000, + ORV_r_p_z = SVEIntReductionLogicalFixed | 0x00180000, + EORV_r_p_z = SVEIntReductionLogicalFixed | 0x00190000, + ANDV_r_p_z = SVEIntReductionLogicalFixed | 0x001A0000 }; enum SVEIntUnaryArithmeticPredicatedOp : uint32_t { - SVEIntUnaryArithmeticPredicatedFixed = 0x0400A000u, - SVEIntUnaryArithmeticPredicatedFMask = 0xFF20E000u, - SVEIntUnaryArithmeticPredicatedMask = 0xFF3FE000u, - SXTB_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00100000u, - UXTB_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00110000u, - SXTH_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00120000u, - UXTH_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00130000u, - SXTW_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00140000u, - UXTW_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00150000u, - ABS_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00160000u, - NEG_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00170000u, - CLS_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00180000u, - CLZ_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00190000u, - CNT_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x001A0000u, - CNOT_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x001B0000u, - FABS_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x001C0000u, - FNEG_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x001D0000u, - NOT_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x001E0000u + SVEIntUnaryArithmeticPredicatedFixed = 0x0400A000, + SVEIntUnaryArithmeticPredicatedFMask = 0xFF20E000, + SVEIntUnaryArithmeticPredicatedMask = 0xFF3FE000, + SXTB_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00100000, + UXTB_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00110000, + SXTH_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00120000, + UXTH_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00130000, + SXTW_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00140000, + UXTW_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00150000, + ABS_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00160000, + NEG_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00170000, + CLS_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00180000, + CLZ_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00190000, + CNT_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x001A0000, + CNOT_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x001B0000, + FABS_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x001C0000, + FNEG_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x001D0000, + NOT_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x001E0000 }; enum SVELoadAndBroadcastElementOp : uint32_t { - SVELoadAndBroadcastElementFixed = 0x84408000u, - SVELoadAndBroadcastElementFMask = 0xFE408000u, - SVELoadAndBroadcastElementMask = 0xFFC0E000u, + SVELoadAndBroadcastElementFixed = 0x84408000, + SVELoadAndBroadcastElementFMask = 0xFE408000, + SVELoadAndBroadcastElementMask = 0xFFC0E000, LD1RB_z_p_bi_u8 = SVELoadAndBroadcastElementFixed, - LD1RB_z_p_bi_u16 = SVELoadAndBroadcastElementFixed | 0x00002000u, - LD1RB_z_p_bi_u32 = SVELoadAndBroadcastElementFixed | 0x00004000u, - LD1RB_z_p_bi_u64 = SVELoadAndBroadcastElementFixed | 0x00006000u, - LD1RSW_z_p_bi_s64 = SVELoadAndBroadcastElementFixed | 0x00800000u, - LD1RH_z_p_bi_u16 = SVELoadAndBroadcastElementFixed | 0x00802000u, - LD1RH_z_p_bi_u32 = SVELoadAndBroadcastElementFixed | 0x00804000u, - LD1RH_z_p_bi_u64 = SVELoadAndBroadcastElementFixed | 0x00806000u, - LD1RSH_z_p_bi_s64 = SVELoadAndBroadcastElementFixed | 0x01000000u, - LD1RSH_z_p_bi_s32 = SVELoadAndBroadcastElementFixed | 0x01002000u, - LD1RW_z_p_bi_u32 = SVELoadAndBroadcastElementFixed | 0x01004000u, - LD1RW_z_p_bi_u64 = SVELoadAndBroadcastElementFixed | 0x01006000u, - LD1RSB_z_p_bi_s64 = SVELoadAndBroadcastElementFixed | 0x01800000u, - LD1RSB_z_p_bi_s32 = SVELoadAndBroadcastElementFixed | 0x01802000u, - LD1RSB_z_p_bi_s16 = SVELoadAndBroadcastElementFixed | 0x01804000u, - LD1RD_z_p_bi_u64 = SVELoadAndBroadcastElementFixed | 0x01806000u + LD1RB_z_p_bi_u16 = SVELoadAndBroadcastElementFixed | 0x00002000, + LD1RB_z_p_bi_u32 = SVELoadAndBroadcastElementFixed | 0x00004000, + LD1RB_z_p_bi_u64 = SVELoadAndBroadcastElementFixed | 0x00006000, + LD1RSW_z_p_bi_s64 = SVELoadAndBroadcastElementFixed | 0x00800000, + LD1RH_z_p_bi_u16 = SVELoadAndBroadcastElementFixed | 0x00802000, + LD1RH_z_p_bi_u32 = SVELoadAndBroadcastElementFixed | 0x00804000, + LD1RH_z_p_bi_u64 = SVELoadAndBroadcastElementFixed | 0x00806000, + LD1RSH_z_p_bi_s64 = SVELoadAndBroadcastElementFixed | 0x01000000, + LD1RSH_z_p_bi_s32 = SVELoadAndBroadcastElementFixed | 0x01002000, + LD1RW_z_p_bi_u32 = SVELoadAndBroadcastElementFixed | 0x01004000, + LD1RW_z_p_bi_u64 = SVELoadAndBroadcastElementFixed | 0x01006000, + LD1RSB_z_p_bi_s64 = SVELoadAndBroadcastElementFixed | 0x01800000, + LD1RSB_z_p_bi_s32 = SVELoadAndBroadcastElementFixed | 0x01802000, + LD1RSB_z_p_bi_s16 = SVELoadAndBroadcastElementFixed | 0x01804000, + LD1RD_z_p_bi_u64 = SVELoadAndBroadcastElementFixed | 0x01806000 }; enum SVELoadAndBroadcastQuadword_ScalarPlusImmOp : uint32_t { - SVELoadAndBroadcastQuadword_ScalarPlusImmFixed = 0xA4002000u, - SVELoadAndBroadcastQuadword_ScalarPlusImmFMask = 0xFE10E000u, - SVELoadAndBroadcastQuadword_ScalarPlusImmMask = 0xFFF0E000u, + SVELoadAndBroadcastQuadword_ScalarPlusImmFixed = 0xA4002000, + SVELoadAndBroadcastQuadword_ScalarPlusImmFMask = 0xFE10E000, + SVELoadAndBroadcastQuadword_ScalarPlusImmMask = 0xFFF0E000, LD1RQB_z_p_bi_u8 = SVELoadAndBroadcastQuadword_ScalarPlusImmFixed, - LD1RQH_z_p_bi_u16 = SVELoadAndBroadcastQuadword_ScalarPlusImmFixed | 0x00800000u, - LD1RQW_z_p_bi_u32 = SVELoadAndBroadcastQuadword_ScalarPlusImmFixed | 0x01000000u, - LD1RQD_z_p_bi_u64 = SVELoadAndBroadcastQuadword_ScalarPlusImmFixed | 0x01800000u + LD1RQH_z_p_bi_u16 = SVELoadAndBroadcastQuadword_ScalarPlusImmFixed | 0x00800000, + LD1RQW_z_p_bi_u32 = SVELoadAndBroadcastQuadword_ScalarPlusImmFixed | 0x01000000, + LD1RQD_z_p_bi_u64 = SVELoadAndBroadcastQuadword_ScalarPlusImmFixed | 0x01800000 }; enum SVELoadAndBroadcastQuadword_ScalarPlusScalarOp : uint32_t { - SVELoadAndBroadcastQuadword_ScalarPlusScalarFixed = 0xA4000000u, - SVELoadAndBroadcastQuadword_ScalarPlusScalarFMask = 0xFE00E000u, - SVELoadAndBroadcastQuadword_ScalarPlusScalarMask = 0xFFE0E000u, + SVELoadAndBroadcastQuadword_ScalarPlusScalarFixed = 0xA4000000, + SVELoadAndBroadcastQuadword_ScalarPlusScalarFMask = 0xFE00E000, + SVELoadAndBroadcastQuadword_ScalarPlusScalarMask = 0xFFE0E000, LD1RQB_z_p_br_contiguous = SVELoadAndBroadcastQuadword_ScalarPlusScalarFixed, - LD1RQH_z_p_br_contiguous = SVELoadAndBroadcastQuadword_ScalarPlusScalarFixed | 0x00800000u, - LD1RQW_z_p_br_contiguous = SVELoadAndBroadcastQuadword_ScalarPlusScalarFixed | 0x01000000u, - LD1RQD_z_p_br_contiguous = SVELoadAndBroadcastQuadword_ScalarPlusScalarFixed | 0x01800000u + LD1RQH_z_p_br_contiguous = SVELoadAndBroadcastQuadword_ScalarPlusScalarFixed | 0x00800000, + LD1RQW_z_p_br_contiguous = SVELoadAndBroadcastQuadword_ScalarPlusScalarFixed | 0x01000000, + LD1RQD_z_p_br_contiguous = SVELoadAndBroadcastQuadword_ScalarPlusScalarFixed | 0x01800000 }; enum SVELoadMultipleStructures_ScalarPlusImmOp : uint32_t { - SVELoadMultipleStructures_ScalarPlusImmFixed = 0xA400E000u, - SVELoadMultipleStructures_ScalarPlusImmFMask = 0xFE10E000u, - SVELoadMultipleStructures_ScalarPlusImmMask = 0xFFF0E000u, - LD2B_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00200000u, - LD3B_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00400000u, - LD4B_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00600000u, - LD2H_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00A00000u, - LD3H_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00C00000u, - LD4H_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00E00000u, - LD2W_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01200000u, - LD3W_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01400000u, - LD4W_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01600000u, - LD2D_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01A00000u, - LD3D_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01C00000u, - LD4D_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01E00000u + SVELoadMultipleStructures_ScalarPlusImmFixed = 0xA400E000, + SVELoadMultipleStructures_ScalarPlusImmFMask = 0xFE10E000, + SVELoadMultipleStructures_ScalarPlusImmMask = 0xFFF0E000, + LD2B_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00200000, + LD3B_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00400000, + LD4B_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00600000, + LD2H_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00A00000, + LD3H_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00C00000, + LD4H_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00E00000, + LD2W_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01200000, + LD3W_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01400000, + LD4W_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01600000, + LD2D_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01A00000, + LD3D_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01C00000, + LD4D_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01E00000 }; enum SVELoadMultipleStructures_ScalarPlusScalarOp : uint32_t { - SVELoadMultipleStructures_ScalarPlusScalarFixed = 0xA400C000u, - SVELoadMultipleStructures_ScalarPlusScalarFMask = 0xFE00E000u, - SVELoadMultipleStructures_ScalarPlusScalarMask = 0xFFE0E000u, - LD2B_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00200000u, - LD3B_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00400000u, - LD4B_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00600000u, - LD2H_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00A00000u, - LD3H_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00C00000u, - LD4H_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00E00000u, - LD2W_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01200000u, - LD3W_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01400000u, - LD4W_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01600000u, - LD2D_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01A00000u, - LD3D_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01C00000u, - LD4D_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01E00000u + SVELoadMultipleStructures_ScalarPlusScalarFixed = 0xA400C000, + SVELoadMultipleStructures_ScalarPlusScalarFMask = 0xFE00E000, + SVELoadMultipleStructures_ScalarPlusScalarMask = 0xFFE0E000, + LD2B_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00200000, + LD3B_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00400000, + LD4B_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00600000, + LD2H_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00A00000, + LD3H_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00C00000, + LD4H_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00E00000, + LD2W_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01200000, + LD3W_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01400000, + LD4W_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01600000, + LD2D_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01A00000, + LD3D_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01C00000, + LD4D_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01E00000 }; enum SVELoadPredicateRegisterOp : uint32_t { - SVELoadPredicateRegisterFixed = 0x85800000u, - SVELoadPredicateRegisterFMask = 0xFFC0E010u, - SVELoadPredicateRegisterMask = 0xFFC0E010u, + SVELoadPredicateRegisterFixed = 0x85800000, + SVELoadPredicateRegisterFMask = 0xFFC0E010, + SVELoadPredicateRegisterMask = 0xFFC0E010, LDR_p_bi = SVELoadPredicateRegisterFixed }; enum SVELoadVectorRegisterOp : uint32_t { - SVELoadVectorRegisterFixed = 0x85804000u, - SVELoadVectorRegisterFMask = 0xFFC0E000u, - SVELoadVectorRegisterMask = 0xFFC0E000u, + SVELoadVectorRegisterFixed = 0x85804000, + SVELoadVectorRegisterFMask = 0xFFC0E000, + SVELoadVectorRegisterMask = 0xFFC0E000, LDR_z_bi = SVELoadVectorRegisterFixed }; enum SVEMulIndexOp : uint32_t { - SVEMulIndexFixed = 0x44200000u, - SVEMulIndexFMask = 0xFF200000u, - SVEMulIndexMask = 0xFFE0FC00u, - SDOT_z_zzzi_s = SVEMulIndexFixed | 0x00800000u, - UDOT_z_zzzi_s = SVEMulIndexFixed | 0x00800400u, - SDOT_z_zzzi_d = SVEMulIndexFixed | 0x00C00000u, - UDOT_z_zzzi_d = SVEMulIndexFixed | 0x00C00400u + SVEMulIndexFixed = 0x44200000, + SVEMulIndexFMask = 0xFF200000, + SVEMulIndexMask = 0xFFE0FC00, + SDOT_z_zzzi_s = SVEMulIndexFixed | 0x00800000, + UDOT_z_zzzi_s = SVEMulIndexFixed | 0x00800400, + SDOT_z_zzzi_d = SVEMulIndexFixed | 0x00C00000, + UDOT_z_zzzi_d = SVEMulIndexFixed | 0x00C00400 }; enum SVEPartitionBreakConditionOp : uint32_t { - SVEPartitionBreakConditionFixed = 0x25104000u, - SVEPartitionBreakConditionFMask = 0xFF3FC200u, - SVEPartitionBreakConditionMask = 0xFFFFC200u, + SVEPartitionBreakConditionFixed = 0x25104000, + SVEPartitionBreakConditionFMask = 0xFF3FC200, + SVEPartitionBreakConditionMask = 0xFFFFC200, BRKA_p_p_p = SVEPartitionBreakConditionFixed, - BRKAS_p_p_p_z = SVEPartitionBreakConditionFixed | 0x00400000u, - BRKB_p_p_p = SVEPartitionBreakConditionFixed | 0x00800000u, - BRKBS_p_p_p_z = SVEPartitionBreakConditionFixed | 0x00C00000u + BRKAS_p_p_p_z = SVEPartitionBreakConditionFixed | 0x00400000, + BRKB_p_p_p = SVEPartitionBreakConditionFixed | 0x00800000, + BRKBS_p_p_p_z = SVEPartitionBreakConditionFixed | 0x00C00000 }; enum SVEPermutePredicateElementsOp : uint32_t { - SVEPermutePredicateElementsFixed = 0x05204000u, - SVEPermutePredicateElementsFMask = 0xFF30E210u, - SVEPermutePredicateElementsMask = 0xFF30FE10u, + SVEPermutePredicateElementsFixed = 0x05204000, + SVEPermutePredicateElementsFMask = 0xFF30E210, + SVEPermutePredicateElementsMask = 0xFF30FE10, ZIP1_p_pp = SVEPermutePredicateElementsFixed, - ZIP2_p_pp = SVEPermutePredicateElementsFixed | 0x00000400u, - UZP1_p_pp = SVEPermutePredicateElementsFixed | 0x00000800u, - UZP2_p_pp = SVEPermutePredicateElementsFixed | 0x00000C00u, - TRN1_p_pp = SVEPermutePredicateElementsFixed | 0x00001000u, - TRN2_p_pp = SVEPermutePredicateElementsFixed | 0x00001400u + ZIP2_p_pp = SVEPermutePredicateElementsFixed | 0x00000400, + UZP1_p_pp = SVEPermutePredicateElementsFixed | 0x00000800, + UZP2_p_pp = SVEPermutePredicateElementsFixed | 0x00000C00, + TRN1_p_pp = SVEPermutePredicateElementsFixed | 0x00001000, + TRN2_p_pp = SVEPermutePredicateElementsFixed | 0x00001400 }; enum SVEPermuteVectorExtractOp : uint32_t { - SVEPermuteVectorExtractFixed = 0x05200000u, - SVEPermuteVectorExtractFMask = 0xFF20E000u, - SVEPermuteVectorExtractMask = 0xFFE0E000u, + SVEPermuteVectorExtractFixed = 0x05200000, + SVEPermuteVectorExtractFMask = 0xFF20E000, + SVEPermuteVectorExtractMask = 0xFFE0E000, EXT_z_zi_des = SVEPermuteVectorExtractFixed }; enum SVEPermuteVectorInterleavingOp : uint32_t { - SVEPermuteVectorInterleavingFixed = 0x05206000u, - SVEPermuteVectorInterleavingFMask = 0xFF20E000u, - SVEPermuteVectorInterleavingMask = 0xFF20FC00u, + SVEPermuteVectorInterleavingFixed = 0x05206000, + SVEPermuteVectorInterleavingFMask = 0xFF20E000, + SVEPermuteVectorInterleavingMask = 0xFF20FC00, ZIP1_z_zz = SVEPermuteVectorInterleavingFixed, - ZIP2_z_zz = SVEPermuteVectorInterleavingFixed | 0x00000400u, - UZP1_z_zz = SVEPermuteVectorInterleavingFixed | 0x00000800u, - UZP2_z_zz = SVEPermuteVectorInterleavingFixed | 0x00000C00u, - TRN1_z_zz = SVEPermuteVectorInterleavingFixed | 0x00001000u, - TRN2_z_zz = SVEPermuteVectorInterleavingFixed | 0x00001400u + ZIP2_z_zz = SVEPermuteVectorInterleavingFixed | 0x00000400, + UZP1_z_zz = SVEPermuteVectorInterleavingFixed | 0x00000800, + UZP2_z_zz = SVEPermuteVectorInterleavingFixed | 0x00000C00, + TRN1_z_zz = SVEPermuteVectorInterleavingFixed | 0x00001000, + TRN2_z_zz = SVEPermuteVectorInterleavingFixed | 0x00001400 }; enum SVEPredicateCountOp : uint32_t { - SVEPredicateCountFixed = 0x25208000u, - SVEPredicateCountFMask = 0xFF38C000u, - SVEPredicateCountMask = 0xFF3FC200u, + SVEPredicateCountFixed = 0x25208000, + SVEPredicateCountFMask = 0xFF38C000, + SVEPredicateCountMask = 0xFF3FC200, CNTP_r_p_p = SVEPredicateCountFixed }; enum SVEPredicateFirstActiveOp : uint32_t { - SVEPredicateFirstActiveFixed = 0x2518C000u, - SVEPredicateFirstActiveFMask = 0xFF3FFE10u, - SVEPredicateFirstActiveMask = 0xFFFFFE10u, - PFIRST_p_p_p = SVEPredicateFirstActiveFixed | 0x00400000u + SVEPredicateFirstActiveFixed = 0x2518C000, + SVEPredicateFirstActiveFMask = 0xFF3FFE10, + SVEPredicateFirstActiveMask = 0xFFFFFE10, + PFIRST_p_p_p = SVEPredicateFirstActiveFixed | 0x00400000 }; enum SVEPredicateInitializeOp : uint32_t { - SVEPredicateInitializeFixed = 0x2518E000u, - SVEPredicateInitializeFMask = 0xFF3EFC10u, - SVEPredicateInitializeMask = 0xFF3FFC10u, - SVEPredicateInitializeSetFlagsBit = 0x00010000u, - PTRUE_p_s = SVEPredicateInitializeFixed | 0x00000000u, + SVEPredicateInitializeFixed = 0x2518E000, + SVEPredicateInitializeFMask = 0xFF3EFC10, + SVEPredicateInitializeMask = 0xFF3FFC10, + SVEPredicateInitializeSetFlagsBit = 0x00010000, + PTRUE_p_s = SVEPredicateInitializeFixed | 0x00000000, PTRUES_p_s = SVEPredicateInitializeFixed | SVEPredicateInitializeSetFlagsBit }; enum SVEPredicateLogicalOp : uint32_t { - SVEPredicateLogicalFixed = 0x25004000u, - SVEPredicateLogicalFMask = 0xFF30C000u, - SVEPredicateLogicalMask = 0xFFF0C210u, - SVEPredicateLogicalSetFlagsBit = 0x00400000u, + SVEPredicateLogicalFixed = 0x25004000, + SVEPredicateLogicalFMask = 0xFF30C000, + SVEPredicateLogicalMask = 0xFFF0C210, + SVEPredicateLogicalSetFlagsBit = 0x00400000, AND_p_p_pp_z = SVEPredicateLogicalFixed, ANDS_p_p_pp_z = AND_p_p_pp_z | SVEPredicateLogicalSetFlagsBit, - BIC_p_p_pp_z = SVEPredicateLogicalFixed | 0x00000010u, + BIC_p_p_pp_z = SVEPredicateLogicalFixed | 0x00000010, BICS_p_p_pp_z = BIC_p_p_pp_z | SVEPredicateLogicalSetFlagsBit, - EOR_p_p_pp_z = SVEPredicateLogicalFixed | 0x00000200u, + EOR_p_p_pp_z = SVEPredicateLogicalFixed | 0x00000200, EORS_p_p_pp_z = EOR_p_p_pp_z | SVEPredicateLogicalSetFlagsBit, - ORR_p_p_pp_z = SVEPredicateLogicalFixed | 0x00800000u, + ORR_p_p_pp_z = SVEPredicateLogicalFixed | 0x00800000, ORRS_p_p_pp_z = ORR_p_p_pp_z | SVEPredicateLogicalSetFlagsBit, - ORN_p_p_pp_z = SVEPredicateLogicalFixed | 0x00800010u, + ORN_p_p_pp_z = SVEPredicateLogicalFixed | 0x00800010, ORNS_p_p_pp_z = ORN_p_p_pp_z | SVEPredicateLogicalSetFlagsBit, - NAND_p_p_pp_z = SVEPredicateLogicalFixed | 0x00800210u, + NAND_p_p_pp_z = SVEPredicateLogicalFixed | 0x00800210, NANDS_p_p_pp_z = NAND_p_p_pp_z | SVEPredicateLogicalSetFlagsBit, - NOR_p_p_pp_z = SVEPredicateLogicalFixed | 0x00800200u, + NOR_p_p_pp_z = SVEPredicateLogicalFixed | 0x00800200, NORS_p_p_pp_z = NOR_p_p_pp_z | SVEPredicateLogicalSetFlagsBit, - SEL_p_p_pp = SVEPredicateLogicalFixed | 0x00000210u + SEL_p_p_pp = SVEPredicateLogicalFixed | 0x00000210 }; enum SVEPredicateNextActiveOp : uint32_t { - SVEPredicateNextActiveFixed = 0x2519C400u, - SVEPredicateNextActiveFMask = 0xFF3FFE10u, - SVEPredicateNextActiveMask = 0xFF3FFE10u, + SVEPredicateNextActiveFixed = 0x2519C400, + SVEPredicateNextActiveFMask = 0xFF3FFE10, + SVEPredicateNextActiveMask = 0xFF3FFE10, PNEXT_p_p_p = SVEPredicateNextActiveFixed }; enum SVEPredicateReadFromFFR_PredicatedOp : uint32_t { - SVEPredicateReadFromFFR_PredicatedFixed = 0x2518F000u, - SVEPredicateReadFromFFR_PredicatedFMask = 0xFF3FFE10u, - SVEPredicateReadFromFFR_PredicatedMask = 0xFFFFFE10u, + SVEPredicateReadFromFFR_PredicatedFixed = 0x2518F000, + SVEPredicateReadFromFFR_PredicatedFMask = 0xFF3FFE10, + SVEPredicateReadFromFFR_PredicatedMask = 0xFFFFFE10, RDFFR_p_p_f = SVEPredicateReadFromFFR_PredicatedFixed, - RDFFRS_p_p_f = SVEPredicateReadFromFFR_PredicatedFixed | 0x00400000u + RDFFRS_p_p_f = SVEPredicateReadFromFFR_PredicatedFixed | 0x00400000 }; enum SVEPredicateReadFromFFR_UnpredicatedOp : uint32_t { - SVEPredicateReadFromFFR_UnpredicatedFixed = 0x2519F000u, - SVEPredicateReadFromFFR_UnpredicatedFMask = 0xFF3FFFF0u, - SVEPredicateReadFromFFR_UnpredicatedMask = 0xFFFFFFF0u, + SVEPredicateReadFromFFR_UnpredicatedFixed = 0x2519F000, + SVEPredicateReadFromFFR_UnpredicatedFMask = 0xFF3FFFF0, + SVEPredicateReadFromFFR_UnpredicatedMask = 0xFFFFFFF0, RDFFR_p_f = SVEPredicateReadFromFFR_UnpredicatedFixed }; enum SVEPredicateTestOp : uint32_t { - SVEPredicateTestFixed = 0x2510C000u, - SVEPredicateTestFMask = 0xFF3FC210u, - SVEPredicateTestMask = 0xFFFFC21Fu, - PTEST_p_p = SVEPredicateTestFixed | 0x00400000u + SVEPredicateTestFixed = 0x2510C000, + SVEPredicateTestFMask = 0xFF3FC210, + SVEPredicateTestMask = 0xFFFFC21F, + PTEST_p_p = SVEPredicateTestFixed | 0x00400000 }; enum SVEPredicateZeroOp : uint32_t { - SVEPredicateZeroFixed = 0x2518E400u, - SVEPredicateZeroFMask = 0xFF3FFFF0u, - SVEPredicateZeroMask = 0xFFFFFFF0u, + SVEPredicateZeroFixed = 0x2518E400, + SVEPredicateZeroFMask = 0xFF3FFFF0, + SVEPredicateZeroMask = 0xFFFFFFF0, PFALSE_p = SVEPredicateZeroFixed }; enum SVEPropagateBreakOp : uint32_t { - SVEPropagateBreakFixed = 0x2500C000u, - SVEPropagateBreakFMask = 0xFF30C000u, - SVEPropagateBreakMask = 0xFFF0C210u, + SVEPropagateBreakFixed = 0x2500C000, + SVEPropagateBreakFMask = 0xFF30C000, + SVEPropagateBreakMask = 0xFFF0C210, BRKPA_p_p_pp = SVEPropagateBreakFixed, - BRKPB_p_p_pp = SVEPropagateBreakFixed | 0x00000010u, - BRKPAS_p_p_pp = SVEPropagateBreakFixed | 0x00400000u, - BRKPBS_p_p_pp = SVEPropagateBreakFixed | 0x00400010u + BRKPB_p_p_pp = SVEPropagateBreakFixed | 0x00000010, + BRKPAS_p_p_pp = SVEPropagateBreakFixed | 0x00400000, + BRKPBS_p_p_pp = SVEPropagateBreakFixed | 0x00400010 }; enum SVEPropagateBreakToNextPartitionOp : uint32_t { - SVEPropagateBreakToNextPartitionFixed = 0x25184000u, - SVEPropagateBreakToNextPartitionFMask = 0xFFBFC210u, - SVEPropagateBreakToNextPartitionMask = 0xFFFFC210u, + SVEPropagateBreakToNextPartitionFixed = 0x25184000, + SVEPropagateBreakToNextPartitionFMask = 0xFFBFC210, + SVEPropagateBreakToNextPartitionMask = 0xFFFFC210, BRKN_p_p_pp = SVEPropagateBreakToNextPartitionFixed, - BRKNS_p_p_pp = SVEPropagateBreakToNextPartitionFixed | 0x00400000u + BRKNS_p_p_pp = SVEPropagateBreakToNextPartitionFixed | 0x00400000 }; enum SVEReversePredicateElementsOp : uint32_t { - SVEReversePredicateElementsFixed = 0x05344000u, - SVEReversePredicateElementsFMask = 0xFF3FFE10u, - SVEReversePredicateElementsMask = 0xFF3FFE10u, + SVEReversePredicateElementsFixed = 0x05344000, + SVEReversePredicateElementsFMask = 0xFF3FFE10, + SVEReversePredicateElementsMask = 0xFF3FFE10, REV_p_p = SVEReversePredicateElementsFixed }; enum SVEReverseVectorElementsOp : uint32_t { - SVEReverseVectorElementsFixed = 0x05383800u, - SVEReverseVectorElementsFMask = 0xFF3FFC00u, - SVEReverseVectorElementsMask = 0xFF3FFC00u, + SVEReverseVectorElementsFixed = 0x05383800, + SVEReverseVectorElementsFMask = 0xFF3FFC00, + SVEReverseVectorElementsMask = 0xFF3FFC00, REV_z_z = SVEReverseVectorElementsFixed }; enum SVEReverseWithinElementsOp : uint32_t { - SVEReverseWithinElementsFixed = 0x05248000u, - SVEReverseWithinElementsFMask = 0xFF3CE000u, - SVEReverseWithinElementsMask = 0xFF3FE000u, + SVEReverseWithinElementsFixed = 0x05248000, + SVEReverseWithinElementsFMask = 0xFF3CE000, + SVEReverseWithinElementsMask = 0xFF3FE000, REVB_z_z = SVEReverseWithinElementsFixed, - REVH_z_z = SVEReverseWithinElementsFixed | 0x00010000u, - REVW_z_z = SVEReverseWithinElementsFixed | 0x00020000u, - RBIT_z_p_z = SVEReverseWithinElementsFixed | 0x00030000u + REVH_z_z = SVEReverseWithinElementsFixed | 0x00010000, + REVW_z_z = SVEReverseWithinElementsFixed | 0x00020000, + RBIT_z_p_z = SVEReverseWithinElementsFixed | 0x00030000 }; enum SVESaturatingIncDecRegisterByElementCountOp : uint32_t { - SVESaturatingIncDecRegisterByElementCountFixed = 0x0420F000u, - SVESaturatingIncDecRegisterByElementCountFMask = 0xFF20F000u, - SVESaturatingIncDecRegisterByElementCountMask = 0xFFF0FC00u, + SVESaturatingIncDecRegisterByElementCountFixed = 0x0420F000, + SVESaturatingIncDecRegisterByElementCountFMask = 0xFF20F000, + SVESaturatingIncDecRegisterByElementCountMask = 0xFFF0FC00, SQINCB_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed, - UQINCB_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00000400u, - SQDECB_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00000800u, - UQDECB_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00000C00u, - SQINCB_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00100000u, - UQINCB_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00100400u, - SQDECB_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00100800u, - UQDECB_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00100C00u, - SQINCH_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00400000u, - UQINCH_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00400400u, - SQDECH_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00400800u, - UQDECH_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00400C00u, - SQINCH_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00500000u, - UQINCH_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00500400u, - SQDECH_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00500800u, - UQDECH_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00500C00u, - SQINCW_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00800000u, - UQINCW_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00800400u, - SQDECW_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00800800u, - UQDECW_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00800C00u, - SQINCW_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00900000u, - UQINCW_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00900400u, - SQDECW_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00900800u, - UQDECW_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00900C00u, - SQINCD_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00C00000u, - UQINCD_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00C00400u, - SQDECD_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00C00800u, - UQDECD_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00C00C00u, - SQINCD_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00D00000u, - UQINCD_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00D00400u, - SQDECD_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00D00800u, - UQDECD_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00D00C00u + UQINCB_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00000400, + SQDECB_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00000800, + UQDECB_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00000C00, + SQINCB_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00100000, + UQINCB_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00100400, + SQDECB_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00100800, + UQDECB_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00100C00, + SQINCH_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00400000, + UQINCH_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00400400, + SQDECH_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00400800, + UQDECH_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00400C00, + SQINCH_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00500000, + UQINCH_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00500400, + SQDECH_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00500800, + UQDECH_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00500C00, + SQINCW_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00800000, + UQINCW_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00800400, + SQDECW_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00800800, + UQDECW_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00800C00, + SQINCW_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00900000, + UQINCW_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00900400, + SQDECW_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00900800, + UQDECW_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00900C00, + SQINCD_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00C00000, + UQINCD_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00C00400, + SQDECD_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00C00800, + UQDECD_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00C00C00, + SQINCD_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00D00000, + UQINCD_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00D00400, + SQDECD_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00D00800, + UQDECD_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00D00C00 }; enum SVESaturatingIncDecVectorByElementCountOp : uint32_t { - SVESaturatingIncDecVectorByElementCountFixed = 0x0420C000u, - SVESaturatingIncDecVectorByElementCountFMask = 0xFF30F000u, - SVESaturatingIncDecVectorByElementCountMask = 0xFFF0FC00u, - SQINCH_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00400000u, - UQINCH_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00400400u, - SQDECH_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00400800u, - UQDECH_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00400C00u, - SQINCW_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00800000u, - UQINCW_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00800400u, - SQDECW_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00800800u, - UQDECW_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00800C00u, - SQINCD_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00C00000u, - UQINCD_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00C00400u, - SQDECD_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00C00800u, - UQDECD_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00C00C00u + SVESaturatingIncDecVectorByElementCountFixed = 0x0420C000, + SVESaturatingIncDecVectorByElementCountFMask = 0xFF30F000, + SVESaturatingIncDecVectorByElementCountMask = 0xFFF0FC00, + SQINCH_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00400000, + UQINCH_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00400400, + SQDECH_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00400800, + UQDECH_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00400C00, + SQINCW_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00800000, + UQINCW_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00800400, + SQDECW_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00800800, + UQDECW_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00800C00, + SQINCD_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00C00000, + UQINCD_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00C00400, + SQDECD_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00C00800, + UQDECD_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00C00C00 }; -enum SVEStackFrameAdjustmentOp { - SVEStackFrameAdjustmentFixed = 0x04205000u, - SVEStackFrameAdjustmentFMask = 0xFFA0F800u, - SVEStackFrameAdjustmentMask = 0xFFE0F800u, +enum SVEStackFrameAdjustmentOp : uint32_t { + SVEStackFrameAdjustmentFixed = 0x04205000, + SVEStackFrameAdjustmentFMask = 0xFFA0F800, + SVEStackFrameAdjustmentMask = 0xFFE0F800, ADDVL_r_ri = SVEStackFrameAdjustmentFixed, - ADDPL_r_ri = SVEStackFrameAdjustmentFixed | 0x00400000u + ADDPL_r_ri = SVEStackFrameAdjustmentFixed | 0x00400000 }; enum SVEStackFrameSizeOp : uint32_t { - SVEStackFrameSizeFixed = 0x04BF5000u, - SVEStackFrameSizeFMask = 0xFFFFF800u, - SVEStackFrameSizeMask = 0xFFFFF800u, + SVEStackFrameSizeFixed = 0x04BF5000, + SVEStackFrameSizeFMask = 0xFFFFF800, + SVEStackFrameSizeMask = 0xFFFFF800, RDVL_r_i = SVEStackFrameSizeFixed }; enum SVEStoreMultipleStructures_ScalarPlusImmOp : uint32_t { - SVEStoreMultipleStructures_ScalarPlusImmFixed = 0xE410E000u, - SVEStoreMultipleStructures_ScalarPlusImmFMask = 0xFE10E000u, - SVEStoreMultipleStructures_ScalarPlusImmMask = 0xFFF0E000u, - ST2B_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00200000u, - ST3B_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00400000u, - ST4B_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00600000u, - ST2H_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00A00000u, - ST3H_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00C00000u, - ST4H_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00E00000u, - ST2W_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01200000u, - ST3W_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01400000u, - ST4W_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01600000u, - ST2D_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01A00000u, - ST3D_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01C00000u, - ST4D_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01E00000u + SVEStoreMultipleStructures_ScalarPlusImmFixed = 0xE410E000, + SVEStoreMultipleStructures_ScalarPlusImmFMask = 0xFE10E000, + SVEStoreMultipleStructures_ScalarPlusImmMask = 0xFFF0E000, + ST2B_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00200000, + ST3B_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00400000, + ST4B_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00600000, + ST2H_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00A00000, + ST3H_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00C00000, + ST4H_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00E00000, + ST2W_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01200000, + ST3W_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01400000, + ST4W_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01600000, + ST2D_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01A00000, + ST3D_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01C00000, + ST4D_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01E00000 }; enum SVEStoreMultipleStructures_ScalarPlusScalarOp : uint32_t { - SVEStoreMultipleStructures_ScalarPlusScalarFixed = 0xE4006000u, - SVEStoreMultipleStructures_ScalarPlusScalarFMask = 0xFE00E000u, - SVEStoreMultipleStructures_ScalarPlusScalarMask = 0xFFE0E000u, - ST2B_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00200000u, - ST3B_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00400000u, - ST4B_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00600000u, - ST2H_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00A00000u, - ST3H_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00C00000u, - ST4H_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00E00000u, - ST2W_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01200000u, - ST3W_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01400000u, - ST4W_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01600000u, - ST2D_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01A00000u, - ST3D_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01C00000u, - ST4D_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01E00000u + SVEStoreMultipleStructures_ScalarPlusScalarFixed = 0xE4006000, + SVEStoreMultipleStructures_ScalarPlusScalarFMask = 0xFE00E000, + SVEStoreMultipleStructures_ScalarPlusScalarMask = 0xFFE0E000, + ST2B_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00200000, + ST3B_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00400000, + ST4B_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00600000, + ST2H_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00A00000, + ST3H_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00C00000, + ST4H_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00E00000, + ST2W_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01200000, + ST3W_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01400000, + ST4W_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01600000, + ST2D_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01A00000, + ST3D_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01C00000, + ST4D_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01E00000 }; enum SVEStorePredicateRegisterOp : uint32_t { - SVEStorePredicateRegisterFixed = 0xE5800000u, - SVEStorePredicateRegisterFMask = 0xFFC0E010u, - SVEStorePredicateRegisterMask = 0xFFC0E010u, + SVEStorePredicateRegisterFixed = 0xE5800000, + SVEStorePredicateRegisterFMask = 0xFFC0E010, + SVEStorePredicateRegisterMask = 0xFFC0E010, STR_p_bi = SVEStorePredicateRegisterFixed }; enum SVEStoreVectorRegisterOp : uint32_t { - SVEStoreVectorRegisterFixed = 0xE5804000u, - SVEStoreVectorRegisterFMask = 0xFFC0E000u, - SVEStoreVectorRegisterMask = 0xFFC0E000u, + SVEStoreVectorRegisterFixed = 0xE5804000, + SVEStoreVectorRegisterFMask = 0xFFC0E000, + SVEStoreVectorRegisterMask = 0xFFC0E000, STR_z_bi = SVEStoreVectorRegisterFixed }; enum SVETableLookupOp : uint32_t { - SVETableLookupFixed = 0x05203000u, - SVETableLookupFMask = 0xFF20FC00u, - SVETableLookupMask = 0xFF20FC00u, + SVETableLookupFixed = 0x05203000, + SVETableLookupFMask = 0xFF20FC00, + SVETableLookupMask = 0xFF20FC00, TBL_z_zz_1 = SVETableLookupFixed }; enum SVEUnpackPredicateElementsOp : uint32_t { - SVEUnpackPredicateElementsFixed = 0x05304000u, - SVEUnpackPredicateElementsFMask = 0xFFFEFE10u, - SVEUnpackPredicateElementsMask = 0xFFFFFE10u, + SVEUnpackPredicateElementsFixed = 0x05304000, + SVEUnpackPredicateElementsFMask = 0xFFFEFE10, + SVEUnpackPredicateElementsMask = 0xFFFFFE10, PUNPKLO_p_p = SVEUnpackPredicateElementsFixed, - PUNPKHI_p_p = SVEUnpackPredicateElementsFixed | 0x00010000u + PUNPKHI_p_p = SVEUnpackPredicateElementsFixed | 0x00010000 }; enum SVEUnpackVectorElementsOp : uint32_t { - SVEUnpackVectorElementsFixed = 0x05303800u, - SVEUnpackVectorElementsFMask = 0xFF3CFC00u, - SVEUnpackVectorElementsMask = 0xFF3FFC00u, + SVEUnpackVectorElementsFixed = 0x05303800, + SVEUnpackVectorElementsFMask = 0xFF3CFC00, + SVEUnpackVectorElementsMask = 0xFF3FFC00, SUNPKLO_z_z = SVEUnpackVectorElementsFixed, - SUNPKHI_z_z = SVEUnpackVectorElementsFixed | 0x00010000u, - UUNPKLO_z_z = SVEUnpackVectorElementsFixed | 0x00020000u, - UUNPKHI_z_z = SVEUnpackVectorElementsFixed | 0x00030000u + SUNPKHI_z_z = SVEUnpackVectorElementsFixed | 0x00010000, + UUNPKLO_z_z = SVEUnpackVectorElementsFixed | 0x00020000, + UUNPKHI_z_z = SVEUnpackVectorElementsFixed | 0x00030000 }; enum SVEVectorSelectOp : uint32_t { - SVEVectorSelectFixed = 0x0520C000u, - SVEVectorSelectFMask = 0xFF20C000u, - SVEVectorSelectMask = 0xFF20C000u, + SVEVectorSelectFixed = 0x0520C000, + SVEVectorSelectFMask = 0xFF20C000, + SVEVectorSelectMask = 0xFF20C000, SEL_z_p_zz = SVEVectorSelectFixed }; enum SVEVectorSpliceOp : uint32_t { - SVEVectorSpliceFixed = 0x052C8000u, - SVEVectorSpliceFMask = 0xFF3FE000u, - SVEVectorSpliceMask = 0xFF3FE000u, + SVEVectorSpliceFixed = 0x052C8000, + SVEVectorSpliceFMask = 0xFF3FE000, + SVEVectorSpliceMask = 0xFF3FE000, SPLICE_z_p_zz_des = SVEVectorSpliceFixed }; enum ReservedOp : uint32_t { - ReservedFixed = 0x00000000u, - ReservedFMask = 0x1E000000u, - ReservedMask = 0xFFFF0000u, - UDF = ReservedFixed | 0x00000000u + ReservedFixed = 0x00000000, + ReservedFMask = 0x1E000000, + ReservedMask = 0xFFFF0000, + UDF = ReservedFixed | 0x00000000 }; // Unimplemented and unallocated instructions. These are defined to make fixed // bit assertion easier. enum UnimplementedOp : uint32_t { - UnimplementedFixed = 0x00000000u, - UnimplementedFMask = 0x00000000u + UnimplementedFixed = 0x00000000, + UnimplementedFMask = 0x00000000 }; enum UnallocatedOp : uint32_t { - UnallocatedFixed = 0x00000000u, - UnallocatedFMask = 0x00000000u + UnallocatedFixed = 0x00000000, + UnallocatedFMask = 0x00000000 }; // Re-enable `clang-format` after the `enum`s. @@ -4449,8 +4458,4 @@ enum UnallocatedOp : uint32_t { } // namespace aarch64 } // namespace vixl -#ifdef __clang__ -#pragma clang diagnostic pop -#endif - #endif // VIXL_AARCH64_CONSTANTS_AARCH64_H_ diff --git a/3rdparty/vixl/include/vixl/aarch64/cpu-features-auditor-aarch64.h b/3rdparty/vixl/include/vixl/aarch64/cpu-features-auditor-aarch64.h index 0d87cf283c..7d5ca2f455 100644 --- a/3rdparty/vixl/include/vixl/aarch64/cpu-features-auditor-aarch64.h +++ b/3rdparty/vixl/include/vixl/aarch64/cpu-features-auditor-aarch64.h @@ -32,6 +32,7 @@ #include #include "../cpu-features.h" + #include "decoder-aarch64.h" #include "decoder-visitor-map-aarch64.h" @@ -112,6 +113,7 @@ class CPUFeaturesAuditor : public DecoderVisitor { #define DECLARE(A) virtual void Visit##A(const Instruction* instr); VISITOR_LIST(DECLARE) #undef DECLARE + void VisitCryptoSM3(const Instruction* instr); void LoadStoreHelper(const Instruction* instr); void LoadStorePairHelper(const Instruction* instr); @@ -126,6 +128,7 @@ class CPUFeaturesAuditor : public DecoderVisitor { uint32_t, std::function>; static const FormToVisitorFnMap* GetFormToVisitorFnMap(); + uint32_t form_hash_; }; } // namespace aarch64 diff --git a/3rdparty/vixl/include/vixl/aarch64/debugger-aarch64.h b/3rdparty/vixl/include/vixl/aarch64/debugger-aarch64.h new file mode 100644 index 0000000000..ee5fa24c86 --- /dev/null +++ b/3rdparty/vixl/include/vixl/aarch64/debugger-aarch64.h @@ -0,0 +1,276 @@ +// Copyright 2023, VIXL authors +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of ARM Limited nor the names of its contributors may be +// used to endorse or promote products derived from this software without +// specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND +// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +#ifndef VIXL_AARCH64_DEBUGGER_AARCH64_H_ +#define VIXL_AARCH64_DEBUGGER_AARCH64_H_ + +#include +#include +#include + +#include "../cpu-features.h" +#include "../globals-vixl.h" +#include "../utils-vixl.h" + +#include "abi-aarch64.h" +#include "cpu-features-auditor-aarch64.h" +#include "disasm-aarch64.h" +#include "instructions-aarch64.h" +#include "simulator-aarch64.h" +#include "simulator-constants-aarch64.h" + +#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64 + +namespace vixl { +namespace aarch64 { + +class Simulator; + +enum DebugReturn { DebugContinue, DebugExit }; + + +// A debugger command that performs some action when used by the simulator +// debugger. +class DebuggerCmd { + public: + DebuggerCmd(Simulator* sim, + std::string cmd_word, + std::string cmd_alias, + std::string usage, + std::string description); + virtual ~DebuggerCmd() {} + + // Perform some action based on the arguments passed in. Returns true if the + // debugger should exit after the action, false otherwise. + virtual DebugReturn Action(const std::vector& args) = 0; + + // Return the command word. + std::string_view GetCommandWord() { return command_word_; } + // Return the alias for this command. Returns an empty string if this command + // has no alias. + std::string_view GetCommandAlias() { return command_alias_; } + // Return this commands usage. + std::string_view GetArgsString() { return args_str_; } + // Return this commands description. + std::string_view GetDescription() { return description_; } + + protected: + // Simulator which this command will be performed on. + Simulator* sim_; + // Stream to output the result of the command to. + FILE* ostream_; + // Command word that, when given to the interactive debugger, calls Action. + std::string command_word_; + // Optional alias for the command_word. + std::string command_alias_; + // Optional string showing the arguments that can be passed to the command. + std::string args_str_; + // Optional description of the command. + std::string description_; +}; + + +// +// Base debugger command handlers: +// + + +class HelpCmd : public DebuggerCmd { + public: + HelpCmd(Simulator* sim) + : DebuggerCmd(sim, "help", "h", "", "Display this help message.") {} + + DebugReturn Action(const std::vector& args) override; +}; + + +class BreakCmd : public DebuggerCmd { + public: + BreakCmd(Simulator* sim) + : DebuggerCmd(sim, + "break", + "b", + "
", + "Set or remove a breakpoint.") {} + + DebugReturn Action(const std::vector& args) override; +}; + + +class StepCmd : public DebuggerCmd { + public: + StepCmd(Simulator* sim) + : DebuggerCmd(sim, + "step", + "s", + "[]", + "Step n instructions, default step 1 instruction.") {} + + DebugReturn Action(const std::vector& args) override; +}; + + +class ContinueCmd : public DebuggerCmd { + public: + ContinueCmd(Simulator* sim) + : DebuggerCmd(sim, + "continue", + "c", + "", + "Exit the debugger and continue executing instructions.") {} + + DebugReturn Action(const std::vector& args) override; +}; + + +class PrintCmd : public DebuggerCmd { + public: + PrintCmd(Simulator* sim) + : DebuggerCmd(sim, + "print", + "p", + "", + "Print the contents of a register, all registers or all" + " system registers.") {} + + DebugReturn Action(const std::vector& args) override; +}; + + +class TraceCmd : public DebuggerCmd { + public: + TraceCmd(Simulator* sim) + : DebuggerCmd(sim, + "trace", + "t", + "", + "Start/stop memory and register tracing.") {} + + DebugReturn Action(const std::vector& args) override; +}; + + +class GdbCmd : public DebuggerCmd { + public: + GdbCmd(Simulator* sim) + : DebuggerCmd(sim, + "gdb", + "g", + "", + "Enter an already running instance of gdb.") {} + + DebugReturn Action(const std::vector& args) override; +}; + + +// A debugger for the Simulator which takes input from the user in order to +// control the running of the Simulator. +class Debugger { + public: + // A pair consisting of a register character (e.g: W, X, V) and a register + // code (e.g: 0, 1 ...31) which represents a single parsed register. + // + // Note: the register character is guaranteed to be upper case. + using RegisterParsedFormat = std::pair; + + Debugger(Simulator* sim); + + // Set the input stream, from which commands are read, to a custom stream. + void SetInputStream(std::istream* stream) { input_stream_ = stream; } + + // Register a new command for the debugger. + template + void RegisterCmd(); + + // Set a breakpoint at the given address. + void RegisterBreakpoint(uint64_t addr) { breakpoints_.insert(addr); } + // Remove a breakpoint at the given address. + void RemoveBreakpoint(uint64_t addr) { breakpoints_.erase(addr); } + // Return true if the address is the location of a breakpoint. + bool IsBreakpoint(uint64_t addr) const { + return (breakpoints_.find(addr) != breakpoints_.end()); + } + // Return true if the simulator pc is a breakpoint. + bool IsAtBreakpoint() const; + + // Main loop for the debugger. Keep prompting for user inputted debugger + // commands and try to execute them until a command is given that exits the + // interactive debugger. + void Debug(); + + // Get an unsigned integer value from a string and return it in 'value'. + // Base is used to determine the numeric base of the number to be read, + // i.e: 8 for octal, 10 for decimal, 16 for hexadecimal and 0 for + // auto-detect. Return true if an integer value was found, false otherwise. + static std::optional ParseUint64String(std::string_view uint64_str, + int base = 0); + + // Get a register from a string and return it in 'reg'. Return true if a + // valid register character and code (e.g: W0, X29, V31) was found, false + // otherwise. + static std::optional ParseRegString( + std::string_view reg_str); + + // Print the usage of each debugger command. + void PrintUsage(); + + private: + // Split a string based on the separator given (a single space character by + // default) and return as a std::vector of strings. + static std::vector Tokenize(std::string_view input_line, + char separator = ' '); + + // Try to execute a single debugger command. + DebugReturn ExecDebugCommand(const std::vector& tokenized_cmd); + + // Return true if the string is zero, i.e: all characters in the string + // (other than prefixes) are zero. + static bool IsZeroUint64String(std::string_view uint64_str, int base); + + // The simulator that this debugger acts on. + Simulator* sim_; + + // A vector of all commands recognised by the debugger. + std::vector> debugger_cmds_; + + // Input stream from which commands are read. Default is std::cin. + std::istream* input_stream_; + + // Output stream from the simulator. + FILE* ostream_; + + // A list of all instruction addresses that, when executed by the + // simulator, will start the interactive debugger if it hasn't already. + std::unordered_set breakpoints_; +}; + + +} // namespace aarch64 +} // namespace vixl + +#endif // VIXL_INCLUDE_SIMULATOR_AARCH64 + +#endif // VIXL_AARCH64_DEBUGGER_AARCH64_H_ diff --git a/3rdparty/vixl/include/vixl/aarch64/decoder-constants-aarch64.h b/3rdparty/vixl/include/vixl/aarch64/decoder-constants-aarch64.h index 70e01a103f..af50a55270 100644 --- a/3rdparty/vixl/include/vixl/aarch64/decoder-constants-aarch64.h +++ b/3rdparty/vixl/include/vixl/aarch64/decoder-constants-aarch64.h @@ -3764,7 +3764,7 @@ static const DecodeMapping kDecodeMapping[] = { {"001110"_b, "autiaz_hi_hints"}, {"001111"_b, "autibz_hi_hints"}, {"0100xx"_b, "bti_hb_hints"}, - {"010100"_b, "chkfeat_hi_hints"}, + {"010100"_b, "chkfeat_hf_hints"}, {"0101x1"_b, "hint_hm_hints"}, {"01x110"_b, "hint_hm_hints"}, {"10xxxx"_b, "hint_hm_hints"}, diff --git a/3rdparty/vixl/include/vixl/aarch64/decoder-visitor-map-aarch64.h b/3rdparty/vixl/include/vixl/aarch64/decoder-visitor-map-aarch64.h index 8ae438c104..b4b39f559a 100644 --- a/3rdparty/vixl/include/vixl/aarch64/decoder-visitor-map-aarch64.h +++ b/3rdparty/vixl/include/vixl/aarch64/decoder-visitor-map-aarch64.h @@ -2074,7 +2074,6 @@ {"scvtf_asimdmiscfp16_r"_h, &VISITORCLASS::VisitNEON2RegMiscFP16}, \ {"ucvtf_asimdmiscfp16_r"_h, &VISITORCLASS::VisitNEON2RegMiscFP16}, \ {"addhn_asimddiff_n"_h, &VISITORCLASS::VisitNEON3Different}, \ - {"pmull_asimddiff_l"_h, &VISITORCLASS::VisitNEON3Different}, \ {"raddhn_asimddiff_n"_h, &VISITORCLASS::VisitNEON3Different}, \ {"rsubhn_asimddiff_n"_h, &VISITORCLASS::VisitNEON3Different}, \ {"sabal_asimddiff_l"_h, &VISITORCLASS::VisitNEON3Different}, \ @@ -2592,6 +2591,7 @@ {"dmb_bo_barriers"_h, &VISITORCLASS::VisitSystem}, \ {"dsb_bo_barriers"_h, &VISITORCLASS::VisitSystem}, \ {"hint_hm_hints"_h, &VISITORCLASS::VisitSystem}, \ + {"chkfeat_hf_hints"_h, &VISITORCLASS::VisitSystem}, \ {"mrs_rs_systemmove"_h, &VISITORCLASS::VisitSystem}, \ {"msr_sr_systemmove"_h, &VISITORCLASS::VisitSystem}, \ {"psb_hc_hints"_h, &VISITORCLASS::VisitSystem}, \ @@ -2638,7 +2638,6 @@ &VISITORCLASS::VisitUnconditionalBranchToRegister}, \ {"ret_64r_branch_reg"_h, \ &VISITORCLASS::VisitUnconditionalBranchToRegister}, \ - {"bcax_vvv16_crypto4"_h, &VISITORCLASS::VisitUnimplemented}, \ {"bfcvtn_asimdmisc_4s"_h, &VISITORCLASS::VisitUnimplemented}, \ {"bfdot_asimdelem_e"_h, &VISITORCLASS::VisitUnimplemented}, \ {"bfdot_asimdsame2_d"_h, &VISITORCLASS::VisitUnimplemented}, \ @@ -2646,7 +2645,6 @@ {"bfmlal_asimdsame2_f"_h, &VISITORCLASS::VisitUnimplemented}, \ {"bfmmla_asimdsame2_e"_h, &VISITORCLASS::VisitUnimplemented}, \ {"dsb_bon_barriers"_h, &VISITORCLASS::VisitUnimplemented}, \ - {"eor3_vvv16_crypto4"_h, &VISITORCLASS::VisitUnimplemented}, \ {"ld64b_64l_memop"_h, &VISITORCLASS::VisitUnimplemented}, \ {"ldgm_64bulk_ldsttags"_h, &VISITORCLASS::VisitUnimplemented}, \ {"ldtrb_32_ldst_unpriv"_h, &VISITORCLASS::VisitUnimplemented}, \ @@ -2658,18 +2656,13 @@ {"ldtrsw_64_ldst_unpriv"_h, &VISITORCLASS::VisitUnimplemented}, \ {"ldtr_32_ldst_unpriv"_h, &VISITORCLASS::VisitUnimplemented}, \ {"ldtr_64_ldst_unpriv"_h, &VISITORCLASS::VisitUnimplemented}, \ - {"rax1_vvv2_cryptosha512_3"_h, &VISITORCLASS::VisitUnimplemented}, \ - {"sha512h2_qqv_cryptosha512_3"_h, &VISITORCLASS::VisitUnimplemented}, \ - {"sha512h_qqv_cryptosha512_3"_h, &VISITORCLASS::VisitUnimplemented}, \ - {"sha512su0_vv2_cryptosha512_2"_h, &VISITORCLASS::VisitUnimplemented}, \ - {"sha512su1_vvv2_cryptosha512_3"_h, &VISITORCLASS::VisitUnimplemented}, \ - {"sm3partw1_vvv4_cryptosha512_3"_h, &VISITORCLASS::VisitUnimplemented}, \ - {"sm3partw2_vvv4_cryptosha512_3"_h, &VISITORCLASS::VisitUnimplemented}, \ - {"sm3ss1_vvv4_crypto4"_h, &VISITORCLASS::VisitUnimplemented}, \ - {"sm3tt1a_vvv4_crypto3_imm2"_h, &VISITORCLASS::VisitUnimplemented}, \ - {"sm3tt1b_vvv4_crypto3_imm2"_h, &VISITORCLASS::VisitUnimplemented}, \ - {"sm3tt2a_vvv4_crypto3_imm2"_h, &VISITORCLASS::VisitUnimplemented}, \ - {"sm3tt2b_vvv_crypto3_imm2"_h, &VISITORCLASS::VisitUnimplemented}, \ + {"sm3partw1_vvv4_cryptosha512_3"_h, &VISITORCLASS::VisitCryptoSM3}, \ + {"sm3partw2_vvv4_cryptosha512_3"_h, &VISITORCLASS::VisitCryptoSM3}, \ + {"sm3ss1_vvv4_crypto4"_h, &VISITORCLASS::VisitCryptoSM3}, \ + {"sm3tt1a_vvv4_crypto3_imm2"_h, &VISITORCLASS::VisitCryptoSM3}, \ + {"sm3tt1b_vvv4_crypto3_imm2"_h, &VISITORCLASS::VisitCryptoSM3}, \ + {"sm3tt2a_vvv4_crypto3_imm2"_h, &VISITORCLASS::VisitCryptoSM3}, \ + {"sm3tt2b_vvv_crypto3_imm2"_h, &VISITORCLASS::VisitCryptoSM3}, \ {"sm4ekey_vvv4_cryptosha512_3"_h, &VISITORCLASS::VisitUnimplemented}, \ {"sm4e_vv4_cryptosha512_2"_h, &VISITORCLASS::VisitUnimplemented}, \ {"st64b_64l_memop"_h, &VISITORCLASS::VisitUnimplemented}, \ @@ -2686,7 +2679,6 @@ {"ttest_br_systemresult"_h, &VISITORCLASS::VisitUnimplemented}, \ {"wfet_only_systeminstrswithreg"_h, &VISITORCLASS::VisitUnimplemented}, \ {"wfit_only_systeminstrswithreg"_h, &VISITORCLASS::VisitUnimplemented}, \ - {"xar_vvv2_crypto3_imm6"_h, &VISITORCLASS::VisitUnimplemented}, \ {"bfcvt_z_p_z_s2bf"_h, &VISITORCLASS::VisitUnimplemented}, \ {"bfcvtnt_z_p_z_s2bf"_h, &VISITORCLASS::VisitUnimplemented}, \ {"bfdot_z_zzz"_h, &VISITORCLASS::VisitUnimplemented}, \ @@ -2827,6 +2819,7 @@ {"fmlal_asimdsame_f"_h, &VISITORCLASS::VisitNEON3Same}, \ {"fmlsl2_asimdsame_f"_h, &VISITORCLASS::VisitNEON3Same}, \ {"fmlsl_asimdsame_f"_h, &VISITORCLASS::VisitNEON3Same}, \ + {"pmull_asimddiff_l"_h, &VISITORCLASS::VisitNEON3Different}, \ {"ushll_asimdshf_l"_h, &VISITORCLASS::VisitNEONShiftImmediate}, \ {"sshll_asimdshf_l"_h, &VISITORCLASS::VisitNEONShiftImmediate}, \ {"shrn_asimdshf_n"_h, &VISITORCLASS::VisitNEONShiftImmediate}, \ diff --git a/3rdparty/vixl/include/vixl/aarch64/disasm-aarch64.h b/3rdparty/vixl/include/vixl/aarch64/disasm-aarch64.h index cc941bb19e..b139c4c24c 100644 --- a/3rdparty/vixl/include/vixl/aarch64/disasm-aarch64.h +++ b/3rdparty/vixl/include/vixl/aarch64/disasm-aarch64.h @@ -228,6 +228,11 @@ class Disassembler : public DecoderVisitor { void DisassembleNEONScalarShiftRightNarrowImm(const Instruction* instr); void DisassembleNEONScalar2RegMiscOnlyD(const Instruction* instr); void DisassembleNEONFPScalar2RegMisc(const Instruction* instr); + void DisassembleNEONPolynomialMul(const Instruction* instr); + void DisassembleNEON4Same(const Instruction* instr); + void DisassembleNEONXar(const Instruction* instr); + void DisassembleNEONRax1(const Instruction* instr); + void DisassembleSHA512(const Instruction* instr); void DisassembleMTELoadTag(const Instruction* instr); void DisassembleMTEStoreTag(const Instruction* instr); @@ -238,6 +243,8 @@ class Disassembler : public DecoderVisitor { void Disassemble_Xd_XnSP_Xm(const Instruction* instr); void Disassemble_Xd_XnSP_XmSP(const Instruction* instr); + void VisitCryptoSM3(const Instruction* instr); + void Format(const Instruction* instr, const char* mnemonic, const char* format0, diff --git a/3rdparty/vixl/include/vixl/aarch64/instructions-aarch64.h b/3rdparty/vixl/include/vixl/aarch64/instructions-aarch64.h index 0834a039b5..ce08ea3bd8 100644 --- a/3rdparty/vixl/include/vixl/aarch64/instructions-aarch64.h +++ b/3rdparty/vixl/include/vixl/aarch64/instructions-aarch64.h @@ -32,11 +32,6 @@ #include "constants-aarch64.h" -#ifdef __clang__ -#pragma clang diagnostic push -#pragma clang diagnostic ignored "-Wdeprecated-enum-enum-conversion" -#endif - namespace vixl { namespace aarch64 { // ISA constants. -------------------------------------------------------------- @@ -152,19 +147,19 @@ const unsigned kMTETagWidth = 4; // Make these moved float constants backwards compatible // with explicit vixl::aarch64:: namespace references. -using vixl::kDoubleMantissaBits; using vixl::kDoubleExponentBits; -using vixl::kFloatMantissaBits; -using vixl::kFloatExponentBits; -using vixl::kFloat16MantissaBits; +using vixl::kDoubleMantissaBits; using vixl::kFloat16ExponentBits; +using vixl::kFloat16MantissaBits; +using vixl::kFloatExponentBits; +using vixl::kFloatMantissaBits; -using vixl::kFP16PositiveInfinity; using vixl::kFP16NegativeInfinity; -using vixl::kFP32PositiveInfinity; +using vixl::kFP16PositiveInfinity; using vixl::kFP32NegativeInfinity; -using vixl::kFP64PositiveInfinity; +using vixl::kFP32PositiveInfinity; using vixl::kFP64NegativeInfinity; +using vixl::kFP64PositiveInfinity; using vixl::kFP16DefaultNaN; using vixl::kFP32DefaultNaN; @@ -222,9 +217,10 @@ enum VectorFormat { kFormatVnQ = kFormatSVEQ | kFormatSVE, kFormatVnO = kFormatSVEO | kFormatSVE, - // An artificial value, used by simulator trace tests and a few oddball + // Artificial values, used by simulator trace tests and a few oddball // instructions (such as FMLAL). - kFormat2H = 0xfffffffe + kFormat2H = 0xfffffffe, + kFormat1Q = 0xfffffffd }; // Instructions. --------------------------------------------------------------- @@ -1141,8 +1137,4 @@ class NEONFormatDecoder { } // namespace aarch64 } // namespace vixl -#ifdef __clang__ -#pragma clang diagnostic pop -#endif - #endif // VIXL_AARCH64_INSTRUCTIONS_AARCH64_H_ diff --git a/3rdparty/vixl/include/vixl/aarch64/macro-assembler-aarch64.h b/3rdparty/vixl/include/vixl/aarch64/macro-assembler-aarch64.h index 2219bb8a1e..b74be350ff 100644 --- a/3rdparty/vixl/include/vixl/aarch64/macro-assembler-aarch64.h +++ b/3rdparty/vixl/include/vixl/aarch64/macro-assembler-aarch64.h @@ -664,6 +664,10 @@ enum FPMacroNaNPropagationOption { class MacroAssembler : public Assembler, public MacroAssemblerInterface { public: + explicit MacroAssembler( + PositionIndependentCodeOption pic = PositionIndependentCode); + MacroAssembler(size_t capacity, + PositionIndependentCodeOption pic = PositionIndependentCode); MacroAssembler(byte* buffer, size_t capacity, PositionIndependentCodeOption pic = PositionIndependentCode); @@ -1750,7 +1754,7 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface { V(casah, Casah) \ V(caslh, Caslh) \ V(casalh, Casalh) -// clang-format on + // clang-format on #define DEFINE_MACRO_ASM_FUNC(ASM, MASM) \ void MASM(const Register& rs, const Register& rt, const MemOperand& src) { \ @@ -1768,7 +1772,7 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface { V(caspa, Caspa) \ V(caspl, Caspl) \ V(caspal, Caspal) -// clang-format on + // clang-format on #define DEFINE_MACRO_ASM_FUNC(ASM, MASM) \ void MASM(const Register& rs, \ @@ -1813,7 +1817,7 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface { V(MASM##alb, ASM##alb) \ V(MASM##ah, ASM##ah) \ V(MASM##alh, ASM##alh) -// clang-format on + // clang-format on #define DEFINE_MACRO_LOAD_ASM_FUNC(MASM, ASM) \ void MASM(const Register& rs, const Register& rt, const MemOperand& src) { \ @@ -2713,6 +2717,27 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface { subps(xd, xn, xm); } void Cmpp(const Register& xn, const Register& xm) { Subps(xzr, xn, xm); } + void Chkfeat(const Register& xdn); + void Gcspushm(const Register& rt) { + VIXL_ASSERT(allow_macro_instructions_); + SingleEmissionCheckScope guard(this); + gcspushm(rt); + } + void Gcspopm(const Register& rt = xzr) { + VIXL_ASSERT(allow_macro_instructions_); + SingleEmissionCheckScope guard(this); + gcspopm(rt); + } + void Gcsss1(const Register& rt) { + VIXL_ASSERT(allow_macro_instructions_); + SingleEmissionCheckScope guard(this); + gcsss1(rt); + } + void Gcsss2(const Register& rt) { + VIXL_ASSERT(allow_macro_instructions_); + SingleEmissionCheckScope guard(this); + gcsss2(rt); + } // NEON 3 vector register instructions. #define NEON_3VREG_MACRO_LIST(V) \ @@ -2762,6 +2787,7 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface { V(pmull2, Pmull2) \ V(raddhn, Raddhn) \ V(raddhn2, Raddhn2) \ + V(rax1, Rax1) \ V(rsubhn, Rsubhn) \ V(rsubhn2, Rsubhn2) \ V(saba, Saba) \ @@ -2774,8 +2800,20 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface { V(saddl2, Saddl2) \ V(saddw, Saddw) \ V(saddw2, Saddw2) \ + V(sha1c, Sha1c) \ + V(sha1m, Sha1m) \ + V(sha1p, Sha1p) \ + V(sha1su0, Sha1su0) \ + V(sha256h, Sha256h) \ + V(sha256h2, Sha256h2) \ + V(sha256su1, Sha256su1) \ + V(sha512h, Sha512h) \ + V(sha512h2, Sha512h2) \ + V(sha512su1, Sha512su1) \ V(shadd, Shadd) \ V(shsub, Shsub) \ + V(sm3partw1, Sm3partw1) \ + V(sm3partw2, Sm3partw2) \ V(smax, Smax) \ V(smaxp, Smaxp) \ V(smin, Smin) \ @@ -2870,6 +2908,10 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface { V(abs, Abs) \ V(addp, Addp) \ V(addv, Addv) \ + V(aesd, Aesd) \ + V(aese, Aese) \ + V(aesimc, Aesimc) \ + V(aesmc, Aesmc) \ V(cls, Cls) \ V(clz, Clz) \ V(cnt, Cnt) \ @@ -2918,6 +2960,10 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface { V(sadalp, Sadalp) \ V(saddlp, Saddlp) \ V(saddlv, Saddlv) \ + V(sha1h, Sha1h) \ + V(sha1su1, Sha1su1) \ + V(sha256su0, Sha256su0) \ + V(sha512su0, Sha512su0) \ V(smaxv, Smaxv) \ V(sminv, Sminv) \ V(sqabs, Sqabs) \ @@ -3008,7 +3054,11 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface { V(umlsl, Umlsl) \ V(umlsl2, Umlsl2) \ V(sudot, Sudot) \ - V(usdot, Usdot) + V(usdot, Usdot) \ + V(sm3tt1a, Sm3tt1a) \ + V(sm3tt1b, Sm3tt1b) \ + V(sm3tt2a, Sm3tt2a) \ + V(sm3tt2b, Sm3tt2b) #define DEFINE_MACRO_ASM_FUNC(ASM, MASM) \ @@ -3127,6 +3177,14 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface { SVE_3VREG_COMMUTATIVE_MACRO_LIST(DEFINE_MACRO_ASM_FUNC) #undef DEFINE_MACRO_ASM_FUNC + void Bcax(const VRegister& vd, + const VRegister& vn, + const VRegister& vm, + const VRegister& va) { + VIXL_ASSERT(allow_macro_instructions_); + SingleEmissionCheckScope guard(this); + bcax(vd, vn, vm, va); + } void Bic(const VRegister& vd, const int imm8, const int left_shift = 0) { VIXL_ASSERT(allow_macro_instructions_); SingleEmissionCheckScope guard(this); @@ -3167,6 +3225,14 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface { SingleEmissionCheckScope guard(this); dup(vd, rn); } + void Eor3(const VRegister& vd, + const VRegister& vn, + const VRegister& vm, + const VRegister& va) { + VIXL_ASSERT(allow_macro_instructions_); + SingleEmissionCheckScope guard(this); + eor3(vd, vn, vm, va); + } void Ext(const VRegister& vd, const VRegister& vn, const VRegister& vm, @@ -3463,6 +3529,14 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface { SingleEmissionCheckScope guard(this); st4(vt, vt2, vt3, vt4, lane, dst); } + void Sm3ss1(const VRegister& vd, + const VRegister& vn, + const VRegister& vm, + const VRegister& va) { + VIXL_ASSERT(allow_macro_instructions_); + SingleEmissionCheckScope guard(this); + sm3ss1(vd, vn, vm, va); + } void Smov(const Register& rd, const VRegister& vn, int vn_index) { VIXL_ASSERT(allow_macro_instructions_); SingleEmissionCheckScope guard(this); @@ -3473,6 +3547,14 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface { SingleEmissionCheckScope guard(this); umov(rd, vn, vn_index); } + void Xar(const VRegister& vd, + const VRegister& vn, + const VRegister& vm, + int rotate) { + VIXL_ASSERT(allow_macro_instructions_); + SingleEmissionCheckScope guard(this); + xar(vd, vn, vm, rotate); + } void Crc32b(const Register& rd, const Register& rn, const Register& rm) { VIXL_ASSERT(allow_macro_instructions_); SingleEmissionCheckScope guard(this); @@ -8580,6 +8662,16 @@ class UseScratchRegisterScope { return AcquireFrom(available, kGoverningPRegisterMask).P(); } + // TODO: extend to other scratch register lists. + bool TryAcquire(const Register& required_reg) { + CPURegList* list = masm_->GetScratchRegisterList(); + if (list->IncludesAliasOf(required_reg)) { + list->Remove(required_reg); + return true; + } + return false; + } + Register AcquireRegisterOfSize(int size_in_bits); Register AcquireSameSizeAs(const Register& reg) { return AcquireRegisterOfSize(reg.GetSizeInBits()); diff --git a/3rdparty/vixl/include/vixl/aarch64/operands-aarch64.h b/3rdparty/vixl/include/vixl/aarch64/operands-aarch64.h index ba3df18133..5469542207 100644 --- a/3rdparty/vixl/include/vixl/aarch64/operands-aarch64.h +++ b/3rdparty/vixl/include/vixl/aarch64/operands-aarch64.h @@ -735,7 +735,7 @@ class SVEMemOperand { class IntegerOperand { public: #define VIXL_INT_TYPES(V) \ - V(char) V(short) V(int) V(long) V(long long) // NOLINT(runtime/int) + V(char) V(short) V(int) V(long) V(long long) // NOLINT(google-runtime-int) #define VIXL_DECL_INT_OVERLOADS(T) \ /* These are allowed to be implicit constructors because this is a */ \ /* wrapper class that doesn't normally perform any type conversion. */ \ @@ -993,7 +993,7 @@ class GenericOperand { // We only support sizes up to X/D register sizes. size_t mem_op_size_; }; -} -} // namespace vixl::aarch64 +} // namespace aarch64 +} // namespace vixl #endif // VIXL_AARCH64_OPERANDS_AARCH64_H_ diff --git a/3rdparty/vixl/include/vixl/aarch64/registers-aarch64.h b/3rdparty/vixl/include/vixl/aarch64/registers-aarch64.h index f9a6d897f5..53bbe132f7 100644 --- a/3rdparty/vixl/include/vixl/aarch64/registers-aarch64.h +++ b/3rdparty/vixl/include/vixl/aarch64/registers-aarch64.h @@ -575,6 +575,7 @@ class VRegister : public CPURegister { VRegister V4S() const; VRegister V1D() const; VRegister V2D() const; + VRegister V1Q() const; VRegister S4B() const; bool IsValid() const { return IsValidVRegister(); } @@ -895,7 +896,7 @@ bool AreSameLaneSize(const CPURegister& reg1, const CPURegister& reg2, const CPURegister& reg3 = NoCPUReg, const CPURegister& reg4 = NoCPUReg); -} -} // namespace vixl::aarch64 +} // namespace aarch64 +} // namespace vixl #endif // VIXL_AARCH64_REGISTERS_AARCH64_H_ diff --git a/3rdparty/vixl/include/vixl/aarch64/simulator-aarch64.h b/3rdparty/vixl/include/vixl/aarch64/simulator-aarch64.h index fc2eedd54f..fa530bd42d 100644 --- a/3rdparty/vixl/include/vixl/aarch64/simulator-aarch64.h +++ b/3rdparty/vixl/include/vixl/aarch64/simulator-aarch64.h @@ -28,15 +28,18 @@ #define VIXL_AARCH64_SIMULATOR_AARCH64_H_ #include +#include +#include #include #include +#include "../cpu-features.h" #include "../globals-vixl.h" #include "../utils-vixl.h" -#include "../cpu-features.h" #include "abi-aarch64.h" #include "cpu-features-auditor-aarch64.h" +#include "debugger-aarch64.h" #include "disasm-aarch64.h" #include "instructions-aarch64.h" #include "simulator-constants-aarch64.h" @@ -67,6 +70,28 @@ namespace aarch64 { class Simulator; struct RuntimeCallStructHelper; +enum class MemoryAccessResult { Success = 0, Failure = 1 }; + +// Try to access a piece of memory at the given address. Accessing that memory +// might raise a signal which, if handled by a custom signal handler, should +// setup the native and simulated context in order to continue. Return whether +// the memory access failed (i.e: raised a signal) or succeeded. +MemoryAccessResult TryMemoryAccess(uintptr_t address, uintptr_t access_size); + +#ifdef VIXL_ENABLE_IMPLICIT_CHECKS +// Access a byte of memory from the address at the given offset. If the memory +// could be accessed then return MemoryAccessResult::Success. If the memory +// could not be accessed, and therefore raised a signal, setup the simulated +// context and return MemoryAccessResult::Failure. +// +// If a signal is raised then it is expected that the signal handler will place +// MemoryAccessResult::Failure in the native return register and the address of +// _vixl_internal_AccessMemory_continue into the native instruction pointer. +extern "C" MemoryAccessResult _vixl_internal_ReadMemory(uintptr_t address, + uintptr_t offset); +extern "C" uintptr_t _vixl_internal_AccessMemory_continue(); +#endif // VIXL_ENABLE_IMPLICIT_CHECKS + class SimStack { public: SimStack() {} @@ -135,7 +160,7 @@ class SimStack { // Allocate the stack, locking the parameters. Allocated Allocate() { - size_t align_to = 1 << align_log2_; + size_t align_to = uint64_t{1} << align_log2_; size_t l = AlignUp(limit_guard_size_, align_to); size_t u = AlignUp(usable_size_, align_to); size_t b = AlignUp(base_guard_size_, align_to); @@ -365,7 +390,7 @@ class Memory { } template - T Read(A address, Instruction const* pc = nullptr) const { + std::optional Read(A address, Instruction const* pc = nullptr) const { T value; VIXL_STATIC_ASSERT((sizeof(value) == 1) || (sizeof(value) == 2) || (sizeof(value) == 4) || (sizeof(value) == 8) || @@ -377,12 +402,16 @@ class Memory { if (!IsMTETagsMatched(address, pc)) { VIXL_ABORT_WITH_MSG("Tag mismatch."); } + if (TryMemoryAccess(reinterpret_cast(base), sizeof(value)) == + MemoryAccessResult::Failure) { + return std::nullopt; + } memcpy(&value, base, sizeof(value)); return value; } template - void Write(A address, T value, Instruction const* pc = nullptr) const { + bool Write(A address, T value, Instruction const* pc = nullptr) const { VIXL_STATIC_ASSERT((sizeof(value) == 1) || (sizeof(value) == 2) || (sizeof(value) == 4) || (sizeof(value) == 8) || (sizeof(value) == 16)); @@ -393,11 +422,16 @@ class Memory { if (!IsMTETagsMatched(address, pc)) { VIXL_ABORT_WITH_MSG("Tag mismatch."); } + if (TryMemoryAccess(reinterpret_cast(base), sizeof(value)) == + MemoryAccessResult::Failure) { + return false; + } memcpy(base, &value, sizeof(value)); + return true; } template - uint64_t ReadUint(int size_in_bytes, A address) const { + std::optional ReadUint(int size_in_bytes, A address) const { switch (size_in_bytes) { case 1: return Read(address); @@ -413,7 +447,7 @@ class Memory { } template - int64_t ReadInt(int size_in_bytes, A address) const { + std::optional ReadInt(int size_in_bytes, A address) const { switch (size_in_bytes) { case 1: return Read(address); @@ -429,7 +463,7 @@ class Memory { } template - void Write(int size_in_bytes, A address, uint64_t value) const { + bool Write(int size_in_bytes, A address, uint64_t value) const { switch (size_in_bytes) { case 1: return Write(address, static_cast(value)); @@ -441,6 +475,7 @@ class Memory { return Write(address, value); } VIXL_UNREACHABLE(); + return false; } void AppendMetaData(MetaDataDepot* metadata_depot) { @@ -649,7 +684,7 @@ class LogicPRegister { void SetAllBits() { int chunk_size = sizeof(ChunkType) * kBitsPerByte; - ChunkType bits = GetUintMask(chunk_size); + ChunkType bits = static_cast(GetUintMask(chunk_size)); for (int lane = 0; lane < (static_cast(register_.GetSizeInBits() / chunk_size)); lane++) { @@ -702,6 +737,8 @@ class LogicPRegister { SimPRegister& register_; }; +using vixl_uint128_t = std::pair; + // Representation of a vector register, with typed getters and setters for lanes // and additional information to represent lane state. class LogicVRegister { @@ -830,6 +867,17 @@ class LogicVRegister { } } + void SetUint(VectorFormat vform, int index, vixl_uint128_t value) const { + if (LaneSizeInBitsFromFormat(vform) <= 64) { + SetUint(vform, index, value.second); + return; + } + // TODO: Extend this to SVE. + VIXL_ASSERT((vform == kFormat1Q) && (index == 0)); + SetUint(kFormat2D, 0, value.second); + SetUint(kFormat2D, 1, value.first); + } + void SetUintArray(VectorFormat vform, const uint64_t* src) const { ClearForWrite(vform); for (int i = 0; i < LaneCountFromFormat(vform); i++) { @@ -1233,6 +1281,11 @@ class SimExclusiveGlobalMonitor { uint32_t seed_; }; +class Debugger; + +template +uint64_t CryptoOp(uint64_t x, uint64_t y, uint64_t z); + class Simulator : public DecoderVisitor { public: explicit Simulator(Decoder* decoder, @@ -1248,7 +1301,7 @@ class Simulator : public DecoderVisitor { #if defined(VIXL_HAS_ABI_SUPPORT) && __cplusplus >= 201103L && \ - (defined(__clang__) || GCC_VERSION_OR_NEWER(4, 9, 1)) + (defined(_MSC_VER) || defined(__clang__) || GCC_VERSION_OR_NEWER(4, 9, 1)) // Templated `RunFrom` version taking care of passing arguments and returning // the result value. // This allows code like: @@ -1307,6 +1360,8 @@ class Simulator : public DecoderVisitor { static const Instruction* kEndOfSimAddress; // Simulation helpers. + bool IsSimulationFinished() const { return pc_ == kEndOfSimAddress; } + const Instruction* ReadPc() const { return pc_; } VIXL_DEPRECATED("ReadPc", const Instruction* pc() const) { return ReadPc(); } @@ -1456,6 +1511,7 @@ class Simulator : public DecoderVisitor { void SimulateNEONFPMulByElementLong(const Instruction* instr); void SimulateNEONComplexMulByElement(const Instruction* instr); void SimulateNEONDotProdByElement(const Instruction* instr); + void SimulateNEONSHA3(const Instruction* instr); void SimulateMTEAddSubTag(const Instruction* instr); void SimulateMTETagMaskInsert(const Instruction* instr); void SimulateMTESubPointer(const Instruction* instr); @@ -1475,7 +1531,9 @@ class Simulator : public DecoderVisitor { void SimulateSetGM(const Instruction* instr); void SimulateSignedMinMax(const Instruction* instr); void SimulateUnsignedMinMax(const Instruction* instr); + void SimulateSHA512(const Instruction* instr); + void VisitCryptoSM3(const Instruction* instr); // Integer register accessors. @@ -2006,62 +2064,66 @@ class Simulator : public DecoderVisitor { } template - T MemRead(A address) const { + std::optional MemRead(A address) const { Instruction const* pc = ReadPc(); return memory_.Read(address, pc); } template - void MemWrite(A address, T value) const { + bool MemWrite(A address, T value) const { Instruction const* pc = ReadPc(); return memory_.Write(address, value, pc); } template - uint64_t MemReadUint(int size_in_bytes, A address) const { + std::optional MemReadUint(int size_in_bytes, A address) const { return memory_.ReadUint(size_in_bytes, address); } template - int64_t MemReadInt(int size_in_bytes, A address) const { + std::optional MemReadInt(int size_in_bytes, A address) const { return memory_.ReadInt(size_in_bytes, address); } template - void MemWrite(int size_in_bytes, A address, uint64_t value) const { + bool MemWrite(int size_in_bytes, A address, uint64_t value) const { return memory_.Write(size_in_bytes, address, value); } - void LoadLane(LogicVRegister dst, + bool LoadLane(LogicVRegister dst, VectorFormat vform, int index, uint64_t addr) const { unsigned msize_in_bytes = LaneSizeInBytesFromFormat(vform); - LoadUintToLane(dst, vform, msize_in_bytes, index, addr); + return LoadUintToLane(dst, vform, msize_in_bytes, index, addr); } - void LoadUintToLane(LogicVRegister dst, + bool LoadUintToLane(LogicVRegister dst, VectorFormat vform, unsigned msize_in_bytes, int index, uint64_t addr) const { - dst.SetUint(vform, index, MemReadUint(msize_in_bytes, addr)); + VIXL_DEFINE_OR_RETURN_FALSE(value, MemReadUint(msize_in_bytes, addr)); + dst.SetUint(vform, index, value); + return true; } - void LoadIntToLane(LogicVRegister dst, + bool LoadIntToLane(LogicVRegister dst, VectorFormat vform, unsigned msize_in_bytes, int index, uint64_t addr) const { - dst.SetInt(vform, index, MemReadInt(msize_in_bytes, addr)); + VIXL_DEFINE_OR_RETURN_FALSE(value, MemReadInt(msize_in_bytes, addr)); + dst.SetInt(vform, index, value); + return true; } - void StoreLane(const LogicVRegister& src, + bool StoreLane(const LogicVRegister& src, VectorFormat vform, int index, uint64_t addr) const { unsigned msize_in_bytes = LaneSizeInBytesFromFormat(vform); - MemWrite(msize_in_bytes, addr, src.Uint(vform, index)); + return MemWrite(msize_in_bytes, addr, src.Uint(vform, index)); } uint64_t ComputeMemOperandAddress(const MemOperand& mem_op) const; @@ -2072,12 +2134,14 @@ class Simulator : public DecoderVisitor { return ReadCPURegister(operand.GetCPURegister()); } else { VIXL_ASSERT(operand.IsMemOperand()); - return MemRead(ComputeMemOperandAddress(operand.GetMemOperand())); + auto res = MemRead(ComputeMemOperandAddress(operand.GetMemOperand())); + VIXL_ASSERT(res); + return *res; } } template - void WriteGenericOperand(GenericOperand operand, + bool WriteGenericOperand(GenericOperand operand, T value, RegLogMode log_mode = LogRegWrites) { if (operand.IsCPURegister()) { @@ -2093,8 +2157,9 @@ class Simulator : public DecoderVisitor { WriteCPURegister(operand.GetCPURegister(), raw, log_mode); } else { VIXL_ASSERT(operand.IsMemOperand()); - MemWrite(ComputeMemOperandAddress(operand.GetMemOperand()), value); + return MemWrite(ComputeMemOperandAddress(operand.GetMemOperand()), value); } + return true; } bool ReadN() const { return nzcv_.GetN() != 0; } @@ -2470,12 +2535,16 @@ class Simulator : public DecoderVisitor { // Other state updates, including system registers. void PrintSystemRegister(SystemRegister id); void PrintTakenBranch(const Instruction* target); + void PrintGCS(bool is_push, uint64_t addr, size_t entry); void LogSystemRegister(SystemRegister id) { if (ShouldTraceSysRegs()) PrintSystemRegister(id); } void LogTakenBranch(const Instruction* target) { if (ShouldTraceBranches()) PrintTakenBranch(target); } + void LogGCS(bool is_push, uint64_t addr, size_t entry) { + if (ShouldTraceSysRegs()) PrintGCS(is_push, addr, entry); + } // Trace memory accesses. @@ -2837,7 +2906,7 @@ class Simulator : public DecoderVisitor { } if (offset == 0) { - while ((exclude & (1 << tag)) != 0) { + while ((exclude & (uint64_t{1} << tag)) != 0) { tag = (tag + 1) % 16; } } @@ -2845,7 +2914,7 @@ class Simulator : public DecoderVisitor { while (offset > 0) { offset--; tag = (tag + 1) % 16; - while ((exclude & (1 << tag)) != 0) { + while ((exclude & (uint64_t{1} << tag)) != 0) { tag = (tag + 1) % 16; } } @@ -2857,12 +2926,15 @@ class Simulator : public DecoderVisitor { return (addr & ~(UINT64_C(0xf) << 56)) | (tag << 56); } +#if __linux__ +#define VIXL_HAS_SIMULATED_MMAP // Create or remove a mapping with memory protection. Memory attributes such // as MTE and BTI are represented by metadata in Simulator. void* Mmap( void* address, size_t length, int prot, int flags, int fd, off_t offset); int Munmap(void* address, size_t length, int prot); +#endif // The common CPUFeatures interface with the set of available features. @@ -2885,7 +2957,7 @@ class Simulator : public DecoderVisitor { // Also, the initialisation of the tuples in RuntimeCall(Non)Void is incorrect // in GCC before 4.9.1: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=51253 #if defined(VIXL_HAS_ABI_SUPPORT) && __cplusplus >= 201103L && \ - (defined(__clang__) || GCC_VERSION_OR_NEWER(4, 9, 1)) + (defined(_MSC_VER) || defined(__clang__) || GCC_VERSION_OR_NEWER(4, 9, 1)) #define VIXL_HAS_SIMULATED_RUNTIME_CALL_SUPPORT @@ -2943,7 +3015,10 @@ class Simulator : public DecoderVisitor { R return_value = DoRuntimeCall(function, argument_operands, __local_index_sequence_for{}); - WriteGenericOperand(abi.GetReturnGenericOperand(), return_value); + bool succeeded = + WriteGenericOperand(abi.GetReturnGenericOperand(), return_value); + USE(succeeded); + VIXL_ASSERT(succeeded); } template @@ -3076,8 +3151,9 @@ class Simulator : public DecoderVisitor { // either MTE protected or not. if (count != expected) { std::stringstream sstream; - sstream << std::hex << "MTE WARNING : the memory region being unmapped " - "starting at address 0x" + sstream << std::hex + << "MTE WARNING : the memory region being unmapped " + "starting at address 0x" << reinterpret_cast(address) << "is not fully MTE protected.\n"; VIXL_WARNING(sstream.str().c_str()); @@ -3115,6 +3191,52 @@ class Simulator : public DecoderVisitor { meta_data_.RegisterBranchInterception(*function, callback); } + // Return the current output stream in use by the simulator. + FILE* GetOutputStream() const { return stream_; } + + bool IsDebuggerEnabled() const { return debugger_enabled_; } + + void SetDebuggerEnabled(bool enabled) { debugger_enabled_ = enabled; } + + Debugger* GetDebugger() const { return debugger_.get(); } + +#ifdef VIXL_ENABLE_IMPLICIT_CHECKS + // Returns true if the faulting instruction address (usually the program + // counter or instruction pointer) comes from an internal VIXL memory access. + // This can be used by signal handlers to check if a signal was raised from + // the simulator (via TryMemoryAccess) before the actual + // access occurs. + bool IsSimulatedMemoryAccess(uintptr_t fault_pc) const { + return (fault_pc == + reinterpret_cast(&_vixl_internal_ReadMemory)); + } + + // Get the instruction address of the internal VIXL memory access continuation + // label. Signal handlers can resume execution at this address to return to + // TryMemoryAccess which will continue simulation. + uintptr_t GetSignalReturnAddress() const { + return reinterpret_cast(&_vixl_internal_AccessMemory_continue); + } + + // Replace the fault address reported by the kernel with the actual faulting + // address. + // + // This is required because TryMemoryAccess reads a section of + // memory 1 byte at a time meaning the fault address reported may not be the + // base address of memory being accessed. + void ReplaceFaultAddress(siginfo_t* siginfo, void* context) { +#ifdef __x86_64__ + // The base address being accessed is passed in as the first argument to + // _vixl_internal_ReadMemory. + ucontext_t* uc = reinterpret_cast(context); + siginfo->si_addr = reinterpret_cast(uc->uc_mcontext.gregs[REG_RDI]); +#else + USE(siginfo); + USE(context); +#endif // __x86_64__ + } +#endif // VIXL_ENABLE_IMPLICIT_CHECKS + protected: const char* clr_normal; const char* clr_flag_name; @@ -3195,8 +3317,9 @@ class Simulator : public DecoderVisitor { uint64_t left, uint64_t right, int carry_in); - using vixl_uint128_t = std::pair; vixl_uint128_t Add128(vixl_uint128_t x, vixl_uint128_t y); + vixl_uint128_t Lsl128(vixl_uint128_t x, unsigned shift) const; + vixl_uint128_t Eor128(vixl_uint128_t x, vixl_uint128_t y) const; vixl_uint128_t Mul64(uint64_t x, uint64_t y); vixl_uint128_t Neg128(vixl_uint128_t x); void LogicalHelper(const Instruction* instr, int64_t op2); @@ -3278,92 +3401,95 @@ class Simulator : public DecoderVisitor { uint64_t PolynomialMult(uint64_t op1, uint64_t op2, int lane_size_in_bits) const; + vixl_uint128_t PolynomialMult128(uint64_t op1, + uint64_t op2, + int lane_size_in_bits) const; - void ld1(VectorFormat vform, LogicVRegister dst, uint64_t addr); - void ld1(VectorFormat vform, LogicVRegister dst, int index, uint64_t addr); - void ld1r(VectorFormat vform, LogicVRegister dst, uint64_t addr); - void ld1r(VectorFormat vform, + bool ld1(VectorFormat vform, LogicVRegister dst, uint64_t addr); + bool ld1(VectorFormat vform, LogicVRegister dst, int index, uint64_t addr); + bool ld1r(VectorFormat vform, LogicVRegister dst, uint64_t addr); + bool ld1r(VectorFormat vform, VectorFormat unpack_vform, LogicVRegister dst, uint64_t addr, bool is_signed = false); - void ld2(VectorFormat vform, + bool ld2(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, uint64_t addr); - void ld2(VectorFormat vform, + bool ld2(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, int index, uint64_t addr); - void ld2r(VectorFormat vform, + bool ld2r(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, uint64_t addr); - void ld3(VectorFormat vform, + bool ld3(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, LogicVRegister dst3, uint64_t addr); - void ld3(VectorFormat vform, + bool ld3(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, LogicVRegister dst3, int index, uint64_t addr); - void ld3r(VectorFormat vform, + bool ld3r(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, LogicVRegister dst3, uint64_t addr); - void ld4(VectorFormat vform, + bool ld4(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, LogicVRegister dst3, LogicVRegister dst4, uint64_t addr); - void ld4(VectorFormat vform, + bool ld4(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, LogicVRegister dst3, LogicVRegister dst4, int index, uint64_t addr); - void ld4r(VectorFormat vform, + bool ld4r(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, LogicVRegister dst3, LogicVRegister dst4, uint64_t addr); - void st1(VectorFormat vform, LogicVRegister src, uint64_t addr); - void st1(VectorFormat vform, LogicVRegister src, int index, uint64_t addr); - void st2(VectorFormat vform, + bool st1(VectorFormat vform, LogicVRegister src, uint64_t addr); + bool st1(VectorFormat vform, LogicVRegister src, int index, uint64_t addr); + bool st2(VectorFormat vform, LogicVRegister src, LogicVRegister src2, uint64_t addr); - void st2(VectorFormat vform, + bool st2(VectorFormat vform, LogicVRegister src, LogicVRegister src2, int index, uint64_t addr); - void st3(VectorFormat vform, + bool st3(VectorFormat vform, LogicVRegister src, LogicVRegister src2, LogicVRegister src3, uint64_t addr); - void st3(VectorFormat vform, + bool st3(VectorFormat vform, LogicVRegister src, LogicVRegister src2, LogicVRegister src3, int index, uint64_t addr); - void st4(VectorFormat vform, + bool st4(VectorFormat vform, LogicVRegister src, LogicVRegister src2, LogicVRegister src3, LogicVRegister src4, uint64_t addr); - void st4(VectorFormat vform, + bool st4(VectorFormat vform, LogicVRegister src, LogicVRegister src2, LogicVRegister src3, @@ -3649,6 +3775,10 @@ class Simulator : public DecoderVisitor { LogicVRegister dst, const LogicVRegister& src, int rotation); + LogicVRegister rol(VectorFormat vform, + LogicVRegister dst, + const LogicVRegister& src, + int rotation); LogicVRegister ext(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, @@ -4373,6 +4503,90 @@ class Simulator : public DecoderVisitor { LogicVRegister srcdst, const LogicVRegister& src1, const LogicVRegister& src2); + + template + static void SHARotateEltsLeftOne(uint64_t (&x)[N]) { + VIXL_STATIC_ASSERT(N == 4); + uint64_t temp = x[3]; + x[3] = x[2]; + x[2] = x[1]; + x[1] = x[0]; + x[0] = temp; + } + + template + LogicVRegister sha1(LogicVRegister srcdst, + const LogicVRegister& src1, + const LogicVRegister& src2) { + uint64_t y = src1.Uint(kFormat4S, 0); + uint64_t sd[4] = {}; + srcdst.UintArray(kFormat4S, sd); + + for (unsigned i = 0; i < ArrayLength(sd); i++) { + uint64_t t = CryptoOp(sd[1], sd[2], sd[3]); + + y += RotateLeft(sd[0], 5, kSRegSize) + t; + y += src2.Uint(kFormat4S, i); + + sd[1] = RotateLeft(sd[1], 30, kSRegSize); + + // y:sd = ROL(y:sd, 32) + SHARotateEltsLeftOne(sd); + std::swap(sd[0], y); + } + + srcdst.SetUintArray(kFormat4S, sd); + return srcdst; + } + + LogicVRegister sha2h(LogicVRegister srcdst, + const LogicVRegister& src1, + const LogicVRegister& src2, + bool part1); + LogicVRegister sha2su0(LogicVRegister srcdst, const LogicVRegister& src1); + LogicVRegister sha2su1(LogicVRegister srcdst, + const LogicVRegister& src1, + const LogicVRegister& src2); + LogicVRegister sha512h(LogicVRegister srcdst, + const LogicVRegister& src1, + const LogicVRegister& src2); + LogicVRegister sha512h2(LogicVRegister srcdst, + const LogicVRegister& src1, + const LogicVRegister& src2); + LogicVRegister sha512su0(LogicVRegister srcdst, const LogicVRegister& src1); + LogicVRegister sha512su1(LogicVRegister srcdst, + const LogicVRegister& src1, + const LogicVRegister& src2); + + + LogicVRegister aes(LogicVRegister srcdst, + const LogicVRegister& src1, + bool decrypt); + LogicVRegister aesmix(LogicVRegister srcdst, + const LogicVRegister& src1, + bool inverse); + + LogicVRegister sm3partw1(LogicVRegister dst, + const LogicVRegister& src1, + const LogicVRegister& src2); + LogicVRegister sm3partw2(LogicVRegister dst, + const LogicVRegister& src1, + const LogicVRegister& src2); + LogicVRegister sm3ss1(LogicVRegister dst, + const LogicVRegister& src1, + const LogicVRegister& src2, + const LogicVRegister& src3); + LogicVRegister sm3tt1(LogicVRegister srcdst, + const LogicVRegister& src1, + const LogicVRegister& src2, + int index, + bool is_a); + LogicVRegister sm3tt2(LogicVRegister srcdst, + const LogicVRegister& src1, + const LogicVRegister& src2, + int index, + bool is_a); + #define NEON_3VREG_LOGIC_LIST(V) \ V(addhn) \ V(addhn2) \ @@ -4940,7 +5154,8 @@ class Simulator : public DecoderVisitor { unsigned zt_code, const LogicSVEAddressVector& addr); // Load each active zt[lane] from `addr.GetElementAddress(lane, ...)`. - void SVEStructuredLoadHelper(VectorFormat vform, + // Returns false if a load failed. + bool SVEStructuredLoadHelper(VectorFormat vform, const LogicPRegister& pg, unsigned zt_code, const LogicSVEAddressVector& addr, @@ -5138,10 +5353,12 @@ class Simulator : public DecoderVisitor { bool CanReadMemory(uintptr_t address, size_t size); +#ifndef _WIN32 // CanReadMemory needs placeholder file descriptors, so we use a pipe. We can // save some system call overhead by opening them on construction, rather than // on every call to CanReadMemory. int placeholder_pipe_fd_[2]; +#endif template static T FPDefaultNaN(); @@ -5220,11 +5437,15 @@ class Simulator : public DecoderVisitor { CPUFeaturesAuditor cpu_features_auditor_; std::vector saved_cpu_features_; - // State for *rand48 functions, used to simulate randomness with repeatable + // linear_congruential_engine, used to simulate randomness with repeatable // behaviour (so that tests are deterministic). This is used to simulate RNDR // and RNDRRS, as well as to simulate a source of entropy for architecturally // undefined behaviour. - uint16_t rand_state_[3]; + std::linear_congruential_engine(1) << 48> + rand_gen_; // A configurable size of SVE vector registers. unsigned vector_length_; @@ -5232,6 +5453,167 @@ class Simulator : public DecoderVisitor { // Representation of memory attributes such as MTE tagging and BTI page // protection in addition to branch interceptions. MetaDataDepot meta_data_; + + // True if the debugger is enabled and might get entered. + bool debugger_enabled_; + + // Debugger for the simulator. + std::unique_ptr debugger_; + + // The Guarded Control Stack is represented using a vector, where the more + // recently stored addresses are at higher-numbered indices. + using GuardedControlStack = std::vector; + + // The GCSManager handles the synchronisation of GCS across multiple + // Simulator instances. Each Simulator has its own stack, but all share + // a GCSManager instance. This allows exchanging stacks between Simulators + // in a threaded application. + class GCSManager { + public: + // Allocate a new Guarded Control Stack and add it to the vector of stacks. + uint64_t AllocateStack() { + const std::lock_guard lock(stacks_mtx_); + + GuardedControlStack* new_stack = new GuardedControlStack; + uint64_t result; + + // Put the new stack into the first available slot. + for (result = 0; result < stacks_.size(); result++) { + if (stacks_[result] == nullptr) { + stacks_[result] = new_stack; + break; + } + } + + // If there were no slots, create a new one. + if (result == stacks_.size()) { + stacks_.push_back(new_stack); + } + + // Shift the index to look like a stack pointer aligned to a page. + result <<= kPageSizeLog2; + + // Push the tagged index onto the new stack as a seal. + new_stack->push_back(result + 1); + return result; + } + + // Free a Guarded Control Stack and set the stacks_ slot to null. + void FreeStack(uint64_t gcs) { + const std::lock_guard lock(stacks_mtx_); + uint64_t gcs_index = GetGCSIndex(gcs); + GuardedControlStack* gcsptr = stacks_[gcs_index]; + if (gcsptr == nullptr) { + VIXL_ABORT_WITH_MSG("Tried to free unallocated GCS "); + } else { + delete gcsptr; + stacks_[gcs_index] = nullptr; + } + } + + // Get a pointer to the GCS vector using a GCS id. + GuardedControlStack* GetGCSPtr(uint64_t gcs) const { + return stacks_[GetGCSIndex(gcs)]; + } + + private: + uint64_t GetGCSIndex(uint64_t gcs) const { return gcs >> 12; } + + std::vector stacks_; + std::mutex stacks_mtx_; + }; + + // A GCS id indicating no GCS has been allocated. + static const uint64_t kGCSNoStack = kPageSize - 1; + uint64_t gcs_; + bool gcs_enabled_; + + public: + GCSManager& GetGCSManager() { + static GCSManager manager; + return manager; + } + + void EnableGCSCheck() { gcs_enabled_ = true; } + void DisableGCSCheck() { gcs_enabled_ = false; } + bool IsGCSCheckEnabled() const { return gcs_enabled_; } + + private: + bool IsAllocatedGCS(uint64_t gcs) const { return gcs != kGCSNoStack; } + void ResetGCSState() { + GCSManager& m = GetGCSManager(); + if (IsAllocatedGCS(gcs_)) { + m.FreeStack(gcs_); + } + ActivateGCS(m.AllocateStack()); + GCSPop(); // Remove seal. + } + + GuardedControlStack* GetGCSPtr(uint64_t gcs) { + GCSManager& m = GetGCSManager(); + GuardedControlStack* result = m.GetGCSPtr(gcs); + return result; + } + GuardedControlStack* GetActiveGCSPtr() { return GetGCSPtr(gcs_); } + + uint64_t ActivateGCS(uint64_t gcs) { + uint64_t outgoing_gcs = gcs_; + gcs_ = gcs; + return outgoing_gcs; + } + + void GCSPush(uint64_t addr) { + GetActiveGCSPtr()->push_back(addr); + size_t entry = GetActiveGCSPtr()->size() - 1; + LogGCS(/* is_push = */ true, addr, entry); + } + + uint64_t GCSPop() { + GuardedControlStack* gcs = GetActiveGCSPtr(); + if (gcs->empty()) { + return 0; + } + uint64_t return_addr = gcs->back(); + size_t entry = gcs->size() - 1; + gcs->pop_back(); + LogGCS(/* is_push = */ false, return_addr, entry); + return return_addr; + } + + uint64_t GCSPeek() { + GuardedControlStack* gcs = GetActiveGCSPtr(); + if (gcs->empty()) { + return 0; + } + uint64_t return_addr = gcs->back(); + return return_addr; + } + + void ReportGCSFailure(const char* msg) { + if (IsGCSCheckEnabled()) { + GuardedControlStack* gcs = GetActiveGCSPtr(); + printf("%s", msg); + if (gcs == nullptr) { + printf("GCS pointer is null\n"); + } else { + printf("GCS records, most recent first:\n"); + int most_recent_index = static_cast(gcs->size()) - 1; + for (int i = 0; i < 8; i++) { + if (!gcs->empty()) { + uint64_t entry = gcs->back(); + gcs->pop_back(); + int index = most_recent_index - i; + printf(" gcs%" PRIu64 "[%d]: 0x%016" PRIx64 "\n", + gcs_, + index, + entry); + } + } + printf("End of GCS records.\n"); + } + VIXL_ABORT_WITH_MSG("GCS failed "); + } + } }; #if defined(VIXL_HAS_SIMULATED_RUNTIME_CALL_SUPPORT) && __cplusplus < 201402L diff --git a/3rdparty/vixl/include/vixl/assembler-base-vixl.h b/3rdparty/vixl/include/vixl/assembler-base-vixl.h index ff866c4fbe..7bd6af29e4 100644 --- a/3rdparty/vixl/include/vixl/assembler-base-vixl.h +++ b/3rdparty/vixl/include/vixl/assembler-base-vixl.h @@ -43,6 +43,9 @@ namespace internal { class AssemblerBase { public: + AssemblerBase() : allow_assembler_(false) {} + explicit AssemblerBase(size_t capacity) + : buffer_(capacity), allow_assembler_(false) {} AssemblerBase(byte* buffer, size_t capacity) : buffer_(buffer, capacity), allow_assembler_(false) {} diff --git a/3rdparty/vixl/include/vixl/code-buffer-vixl.h b/3rdparty/vixl/include/vixl/code-buffer-vixl.h index a59026894f..cb9031fefc 100644 --- a/3rdparty/vixl/include/vixl/code-buffer-vixl.h +++ b/3rdparty/vixl/include/vixl/code-buffer-vixl.h @@ -36,11 +36,21 @@ namespace vixl { class CodeBuffer { public: + static const size_t kDefaultCapacity = 4 * KBytes; + + explicit CodeBuffer(size_t capacity = kDefaultCapacity); CodeBuffer(byte* buffer, size_t capacity); ~CodeBuffer() VIXL_NEGATIVE_TESTING_ALLOW_EXCEPTION; void Reset(); + // Make the buffer executable or writable. These states are mutually + // exclusive. + // Note that these require page-aligned memory blocks, which we can only + // guarantee with VIXL_CODE_BUFFER_MMAP. + void SetExecutable(); + void SetWritable(); + ptrdiff_t GetOffsetFrom(ptrdiff_t offset) const { ptrdiff_t cursor_offset = cursor_ - buffer_; VIXL_ASSERT((offset >= 0) && (offset <= cursor_offset)); @@ -136,6 +146,10 @@ class CodeBuffer { return GetCapacity(); } + bool IsManaged() const { return managed_; } + + void Grow(size_t new_capacity); + bool IsDirty() const { return dirty_; } void SetClean() { dirty_ = false; } @@ -144,9 +158,24 @@ class CodeBuffer { return GetRemainingBytes() >= amount; } + void EnsureSpaceFor(size_t amount, bool* has_grown) { + bool is_full = !HasSpaceFor(amount); + if (is_full) Grow(capacity_ * 2 + amount); + VIXL_ASSERT(has_grown != NULL); + *has_grown = is_full; + } + void EnsureSpaceFor(size_t amount) { + bool placeholder; + EnsureSpaceFor(amount, &placeholder); + } + private: // Backing store of the buffer. byte* buffer_; + // If true the backing store is allocated and deallocated by the buffer. The + // backing store can then grow on demand. If false the backing store is + // provided by the user and cannot be resized internally. + bool managed_; // Pointer to the next location to be written. byte* cursor_; // True if there has been any write since the buffer was created or cleaned. diff --git a/3rdparty/vixl/include/vixl/code-generation-scopes-vixl.h b/3rdparty/vixl/include/vixl/code-generation-scopes-vixl.h index 2818ceda0d..f019b685fe 100644 --- a/3rdparty/vixl/include/vixl/code-generation-scopes-vixl.h +++ b/3rdparty/vixl/include/vixl/code-generation-scopes-vixl.h @@ -68,14 +68,19 @@ class CodeBufferCheckScope { size_t size, BufferSpacePolicy check_policy = kReserveBufferSpace, SizePolicy size_policy = kMaximumSize) - : assembler_(NULL), initialised_(false) { + : CodeBufferCheckScope() { Open(assembler, size, check_policy, size_policy); } // This constructor does not implicitly initialise the scope. Instead, the // user is required to explicitly call the `Open` function before using the // scope. - CodeBufferCheckScope() : assembler_(NULL), initialised_(false) { + CodeBufferCheckScope() + : assembler_(NULL), + assert_policy_(kMaximumSize), + limit_(0), + previous_allow_assembler_(false), + initialised_(false) { // Nothing to do. } @@ -90,7 +95,7 @@ class CodeBufferCheckScope { VIXL_ASSERT(assembler != NULL); assembler_ = assembler; if (check_policy == kReserveBufferSpace) { - VIXL_ASSERT(assembler->GetBuffer()->HasSpaceFor(size)); + assembler->GetBuffer()->EnsureSpaceFor(size); } #ifdef VIXL_DEBUG limit_ = assembler_->GetSizeOfCodeGenerated() + size; @@ -152,14 +157,15 @@ class EmissionCheckScope : public CodeBufferCheckScope { // constructed. EmissionCheckScope(MacroAssemblerInterface* masm, size_t size, - SizePolicy size_policy = kMaximumSize) { + SizePolicy size_policy = kMaximumSize) + : EmissionCheckScope() { Open(masm, size, size_policy); } // This constructor does not implicitly initialise the scope. Instead, the // user is required to explicitly call the `Open` function before using the // scope. - EmissionCheckScope() {} + EmissionCheckScope() : masm_(nullptr), pool_policy_(kBlockPools) {} virtual ~EmissionCheckScope() { Close(); } @@ -250,14 +256,15 @@ class ExactAssemblyScope : public EmissionCheckScope { // constructed. ExactAssemblyScope(MacroAssemblerInterface* masm, size_t size, - SizePolicy size_policy = kExactSize) { + SizePolicy size_policy = kExactSize) + : ExactAssemblyScope() { Open(masm, size, size_policy); } // This constructor does not implicitly initialise the scope. Instead, the // user is required to explicitly call the `Open` function before using the // scope. - ExactAssemblyScope() {} + ExactAssemblyScope() : previous_allow_macro_assembler_(false) {} virtual ~ExactAssemblyScope() { Close(); } diff --git a/3rdparty/vixl/include/vixl/compiler-intrinsics-vixl.h b/3rdparty/vixl/include/vixl/compiler-intrinsics-vixl.h index 50ed3579b7..8d0849a814 100644 --- a/3rdparty/vixl/include/vixl/compiler-intrinsics-vixl.h +++ b/3rdparty/vixl/include/vixl/compiler-intrinsics-vixl.h @@ -29,6 +29,7 @@ #define VIXL_COMPILER_INTRINSICS_H #include + #include "globals-vixl.h" namespace vixl { @@ -112,7 +113,8 @@ inline int CountLeadingSignBits(V value, int width = (sizeof(V) * 8)) { VIXL_ASSERT(IsPowerOf2(width) && (width <= 64)); #if COMPILER_HAS_BUILTIN_CLRSB VIXL_ASSERT((LLONG_MIN <= value) && (value <= LLONG_MAX)); - int ll_width = sizeof(long long) * kBitsPerByte; // NOLINT(runtime/int) + int ll_width = + sizeof(long long) * kBitsPerByte; // NOLINT(google-runtime-int) int result = __builtin_clrsbll(value) - (ll_width - width); // Check that the value fits in the specified width. VIXL_ASSERT(result >= 0); diff --git a/3rdparty/vixl/include/vixl/cpu-features.h b/3rdparty/vixl/include/vixl/cpu-features.h index 97eb661a23..1a041f6610 100644 --- a/3rdparty/vixl/include/vixl/cpu-features.h +++ b/3rdparty/vixl/include/vixl/cpu-features.h @@ -201,7 +201,8 @@ namespace vixl { /* Extended BFloat16 instructions */ \ V(kEBF16, "EBF16", "ebf16") \ V(kSVE_EBF16, "EBF16 (SVE)", "sveebf16") \ - V(kCSSC, "CSSC", "cssc") + V(kCSSC, "CSSC", "cssc") \ + V(kGCS, "GCS", "gcs") // clang-format on diff --git a/3rdparty/vixl/include/vixl/globals-vixl.h b/3rdparty/vixl/include/vixl/globals-vixl.h index 4548ba897f..b096c7f37a 100644 --- a/3rdparty/vixl/include/vixl/globals-vixl.h +++ b/3rdparty/vixl/include/vixl/globals-vixl.h @@ -27,8 +27,8 @@ #ifndef VIXL_GLOBALS_H #define VIXL_GLOBALS_H -#if __cplusplus < 201402L -#error VIXL requires C++14 +#if __cplusplus < 201703L +#error VIXL requires C++17 #endif // Get standard C99 macros for integer types. @@ -215,6 +215,18 @@ inline void USE(const T1&, const T2&, const T3&, const T4&) {} } while (0) #endif +// Evaluate 'init' to an std::optional and return if it's empty. If 'init' is +// not empty then define a variable 'name' with the value inside the +// std::optional. +#define VIXL_DEFINE_OR_RETURN(name, init) \ + auto opt##name = init; \ + if (!opt##name) return; \ + auto name = *opt##name; +#define VIXL_DEFINE_OR_RETURN_FALSE(name, init) \ + auto opt##name = init; \ + if (!opt##name) return false; \ + auto name = *opt##name; + #if __cplusplus >= 201103L #define VIXL_NO_RETURN [[noreturn]] #else diff --git a/3rdparty/vixl/include/vixl/invalset-vixl.h b/3rdparty/vixl/include/vixl/invalset-vixl.h index dc15149599..b5a710ffe1 100644 --- a/3rdparty/vixl/include/vixl/invalset-vixl.h +++ b/3rdparty/vixl/include/vixl/invalset-vixl.h @@ -1,4 +1,3 @@ -// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -27,9 +26,8 @@ #ifndef VIXL_INVALSET_H_ #define VIXL_INVALSET_H_ -#include - #include +#include #include #include "globals-vixl.h" @@ -92,6 +90,7 @@ class InvalSet { public: InvalSet(); ~InvalSet() VIXL_NEGATIVE_TESTING_ALLOW_EXCEPTION; + InvalSet(InvalSet&&); // movable static const size_t kNPreallocatedElements = N_PREALLOCATED_ELEMENTS; static const KeyType kInvalidKey = INVALID_KEY; @@ -245,12 +244,11 @@ class InvalSet { template class InvalSetIterator { - public: using iterator_category = std::forward_iterator_tag; using value_type = typename S::_ElementType; using difference_type = std::ptrdiff_t; - using pointer = typename S::_ElementType*; - using reference = typename S::_ElementType&; + using pointer = S*; + using reference = S&; private: // Redefine types to mirror the associated set types. @@ -327,6 +325,27 @@ InvalSet::InvalSet() #endif } +template +InvalSet::InvalSet(InvalSet&& other) + : valid_cached_min_(false), sorted_(true), size_(0), vector_(NULL) { + VIXL_ASSERT(other.monitor() == 0); + if (this != &other) { + sorted_ = other.sorted_; + size_ = other.size_; +#ifdef VIXL_DEBUG + monitor_ = 0; +#endif + if (other.IsUsingVector()) { + vector_ = other.vector_; + other.vector_ = NULL; + } else { + std::move(other.preallocated_, + other.preallocated_ + other.size_, + preallocated_); + } + other.clear(); + } +} template InvalSet::~InvalSet() diff --git a/3rdparty/vixl/include/vixl/pool-manager-impl.h b/3rdparty/vixl/include/vixl/pool-manager-impl.h index a1bcaaad83..5baf66b348 100644 --- a/3rdparty/vixl/include/vixl/pool-manager-impl.h +++ b/3rdparty/vixl/include/vixl/pool-manager-impl.h @@ -27,10 +27,10 @@ #ifndef VIXL_POOL_MANAGER_IMPL_H_ #define VIXL_POOL_MANAGER_IMPL_H_ -#include "pool-manager.h" - #include + #include "assembler-base-vixl.h" +#include "pool-manager.h" namespace vixl { @@ -487,7 +487,7 @@ void PoolManager::Release(T pc) { } template -PoolManager::~PoolManager() VIXL_NEGATIVE_TESTING_ALLOW_EXCEPTION { +PoolManager::~PoolManager() VIXL_NEGATIVE_TESTING_ALLOW_EXCEPTION { #ifdef VIXL_DEBUG // Check for unbound objects. for (objects_iter iter = objects_.begin(); iter != objects_.end(); ++iter) { @@ -517,6 +517,6 @@ int PoolManager::GetPoolSizeForTest() const { } return size; } -} +} // namespace vixl #endif // VIXL_POOL_MANAGER_IMPL_H_ diff --git a/3rdparty/vixl/include/vixl/pool-manager.h b/3rdparty/vixl/include/vixl/pool-manager.h index 27fa69ec2c..f5101cc77d 100644 --- a/3rdparty/vixl/include/vixl/pool-manager.h +++ b/3rdparty/vixl/include/vixl/pool-manager.h @@ -27,11 +27,10 @@ #ifndef VIXL_POOL_MANAGER_H_ #define VIXL_POOL_MANAGER_H_ -#include - #include #include #include +#include #include #include "globals-vixl.h" diff --git a/3rdparty/vixl/include/vixl/utils-vixl.h b/3rdparty/vixl/include/vixl/utils-vixl.h index a6632b2fc0..40b5b2703c 100644 --- a/3rdparty/vixl/include/vixl/utils-vixl.h +++ b/3rdparty/vixl/include/vixl/utils-vixl.h @@ -239,6 +239,11 @@ inline uint64_t RotateRight(uint64_t value, return value & width_mask; } +inline uint64_t RotateLeft(uint64_t value, + unsigned int rotate, + unsigned int width) { + return RotateRight(value, width - rotate, width); +} // Wrapper class for passing FP16 values through the assembler. // This is purely to aid with type checking/casting. @@ -291,6 +296,12 @@ T UnsignedNegate(T value) { return ~value + 1; } +template +bool CanBeNegated(T value) { + VIXL_STATIC_ASSERT(std::is_signed::value); + return (value == std::numeric_limits::min()) ? false : true; +} + // An absolute operation for signed integers that is defined for results outside // the representable range. Specifically, Abs(MIN_INT) is MIN_INT. template @@ -548,13 +559,14 @@ inline T SignExtend(T val, int size_in_bits) { template T ReverseBytes(T value, int block_bytes_log2) { VIXL_ASSERT((sizeof(value) == 4) || (sizeof(value) == 8)); - VIXL_ASSERT((1U << block_bytes_log2) <= sizeof(value)); + VIXL_ASSERT((uint64_t{1} << block_bytes_log2) <= sizeof(value)); // Split the 64-bit value into an 8-bit array, where b[0] is the least // significant byte, and b[7] is the most significant. uint8_t bytes[8]; uint64_t mask = UINT64_C(0xff00000000000000); for (int i = 7; i >= 0; i--) { - bytes[i] = (static_cast(value) & mask) >> (i * 8); + bytes[i] = + static_cast((static_cast(value) & mask) >> (i * 8)); mask >>= 8; } @@ -611,6 +623,39 @@ bool IsWordAligned(T pointer) { return IsAligned<4>(pointer); } +template +bool IsRepeatingPattern(T value) { + VIXL_STATIC_ASSERT(std::is_unsigned::value); + VIXL_ASSERT(IsMultiple(sizeof(value) * kBitsPerByte, BITS)); + VIXL_ASSERT(IsMultiple(BITS, 2)); + VIXL_STATIC_ASSERT(BITS >= 2); +#if (defined(__x86_64__) || defined(__i386)) && \ + __clang_major__ >= 17 && __clang_major__ <= 19 + // Workaround for https://github.com/llvm/llvm-project/issues/108722 + unsigned hbits = BITS / 2; + T midmask = (~static_cast(0) >> BITS) << hbits; + // E.g. for bytes in a word (0xb3b2b1b0): .b3b2b1. == .b2b1b0. + return (((value >> hbits) & midmask) == ((value << hbits) & midmask)); +#else + return value == RotateRight(value, BITS, sizeof(value) * kBitsPerByte); +#endif +} + +template +bool AllBytesMatch(T value) { + return IsRepeatingPattern(value); +} + +template +bool AllHalfwordsMatch(T value) { + return IsRepeatingPattern(value); +} + +template +bool AllWordsMatch(T value) { + return IsRepeatingPattern(value); +} + // Increment a pointer until it has the specified alignment. The alignment must // be a power of two. template diff --git a/3rdparty/vixl/src/aarch64/assembler-aarch64.cc b/3rdparty/vixl/src/aarch64/assembler-aarch64.cc index 993d854cd1..31d5875501 100644 --- a/3rdparty/vixl/src/aarch64/assembler-aarch64.cc +++ b/3rdparty/vixl/src/aarch64/assembler-aarch64.cc @@ -25,9 +25,10 @@ // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +#include "assembler-aarch64.h" + #include -#include "assembler-aarch64.h" #include "macro-assembler-aarch64.h" namespace vixl { @@ -1176,8 +1177,7 @@ void Assembler::LoadStorePairNonTemporal(const CPURegister& rt, VIXL_ASSERT(addr.IsImmediateOffset()); unsigned size = - CalcLSPairDataSize(static_cast( - static_cast(op) & static_cast(LoadStorePairMask))); + CalcLSPairDataSize(static_cast(op & LoadStorePairMask)); VIXL_ASSERT(IsImmLSPair(addr.GetOffset(), size)); int offset = static_cast(addr.GetOffset()); Emit(op | Rt(rt) | Rt2(rt2) | RnSP(addr.GetBaseRegister()) | @@ -1918,6 +1918,12 @@ void Assembler::sys(int op, const Register& xt) { } +void Assembler::sysl(int op, const Register& xt) { + VIXL_ASSERT(xt.Is64Bits()); + Emit(SYSL | SysOp(op) | Rt(xt)); +} + + void Assembler::dc(DataCacheOp op, const Register& rt) { if (op == CVAP) VIXL_ASSERT(CPUHas(CPUFeatures::kDCPoP)); if (op == CVADP) VIXL_ASSERT(CPUHas(CPUFeatures::kDCCVADP)); @@ -1930,6 +1936,35 @@ void Assembler::ic(InstructionCacheOp op, const Register& rt) { sys(op, rt); } +void Assembler::gcspushm(const Register& rt) { + VIXL_ASSERT(CPUHas(CPUFeatures::kGCS)); + sys(GCSPUSHM, rt); +} + +void Assembler::gcspopm(const Register& rt) { + VIXL_ASSERT(CPUHas(CPUFeatures::kGCS)); + sysl(GCSPOPM, rt); +} + + +void Assembler::gcsss1(const Register& rt) { + VIXL_ASSERT(CPUHas(CPUFeatures::kGCS)); + sys(GCSSS1, rt); +} + + +void Assembler::gcsss2(const Register& rt) { + VIXL_ASSERT(CPUHas(CPUFeatures::kGCS)); + sysl(GCSSS2, rt); +} + + +void Assembler::chkfeat(const Register& rd) { + VIXL_ASSERT(rd.Is(x16)); + USE(rd); + hint(CHKFEAT); +} + void Assembler::hint(SystemHint code) { hint(static_cast(code)); } @@ -2913,6 +2948,25 @@ void Assembler::st1(const VRegister& vt, int lane, const MemOperand& dst) { LoadStoreStructSingle(vt, lane, dst, NEONLoadStoreSingleStructStore1); } +void Assembler::pmull(const VRegister& vd, + const VRegister& vn, + const VRegister& vm) { + VIXL_ASSERT(CPUHas(CPUFeatures::kNEON)); + VIXL_ASSERT(AreSameFormat(vn, vm)); + VIXL_ASSERT((vn.Is8B() && vd.Is8H()) || (vn.Is1D() && vd.Is1Q())); + VIXL_ASSERT(CPUHas(CPUFeatures::kPmull1Q) || vd.Is8H()); + Emit(VFormat(vn) | NEON_PMULL | Rm(vm) | Rn(vn) | Rd(vd)); +} + +void Assembler::pmull2(const VRegister& vd, + const VRegister& vn, + const VRegister& vm) { + VIXL_ASSERT(CPUHas(CPUFeatures::kNEON)); + VIXL_ASSERT(AreSameFormat(vn, vm)); + VIXL_ASSERT((vn.Is16B() && vd.Is8H()) || (vn.Is2D() && vd.Is1Q())); + VIXL_ASSERT(CPUHas(CPUFeatures::kPmull1Q) || vd.Is8H()); + Emit(VFormat(vn) | NEON_PMULL2 | Rm(vm) | Rn(vn) | Rd(vd)); +} void Assembler::NEON3DifferentL(const VRegister& vd, const VRegister& vn, @@ -2925,7 +2979,7 @@ void Assembler::NEON3DifferentL(const VRegister& vd, (vn.Is8H() && vd.Is4S()) || (vn.Is4S() && vd.Is2D())); Instr format, op = vop; if (vd.IsScalar()) { - op |= static_cast(NEON_Q) | static_cast(NEONScalar); + op |= NEON_Q | NEONScalar; format = SFormat(vn); } else { format = VFormat(vn); @@ -2960,8 +3014,6 @@ void Assembler::NEON3DifferentHN(const VRegister& vd, // clang-format off #define NEON_3DIFF_LONG_LIST(V) \ - V(pmull, NEON_PMULL, vn.IsVector() && vn.Is8B()) \ - V(pmull2, NEON_PMULL2, vn.IsVector() && vn.Is16B()) \ V(saddl, NEON_SADDL, vn.IsVector() && vn.IsD()) \ V(saddl2, NEON_SADDL2, vn.IsVector() && vn.IsQ()) \ V(sabal, NEON_SABAL, vn.IsVector() && vn.IsD()) \ @@ -3650,7 +3702,7 @@ void Assembler::NEONFPConvertToInt(const VRegister& vd, Instr op) { if (vn.IsScalar()) { VIXL_ASSERT((vd.Is1S() && vn.Is1S()) || (vd.Is1D() && vn.Is1D())); - op |= static_cast(NEON_Q) | static_cast(NEONScalar); + op |= NEON_Q | NEONScalar; } Emit(FPFormat(vn) | op | Rn(vn) | Rd(vd)); } @@ -3662,9 +3714,9 @@ void Assembler::NEONFP16ConvertToInt(const VRegister& vd, VIXL_ASSERT(AreSameFormat(vd, vn)); VIXL_ASSERT(vn.IsLaneSizeH()); if (vn.IsScalar()) { - op |= static_cast(NEON_Q) | static_cast(NEONScalar); + op |= NEON_Q | NEONScalar; } else if (vn.Is8H()) { - op |= static_cast(NEON_Q); + op |= NEON_Q; } Emit(op | Rn(vn) | Rd(vd)); } @@ -3838,7 +3890,7 @@ void Assembler::NEON3Same(const VRegister& vd, Instr format, op = vop; if (vd.IsScalar()) { - op |= static_cast(NEON_Q) | static_cast(NEONScalar); + op |= NEON_Q | NEONScalar; format = SFormat(vd); } else { format = VFormat(vd); @@ -3890,18 +3942,15 @@ void Assembler::NEON3SameFP16(const VRegister& vd, Instr op; \ if (vd.IsScalar()) { \ if (vd.Is1H()) { \ - if ((static_cast(SCA_OP_H) & \ - static_cast(NEONScalar2RegMiscFP16FMask)) == \ - static_cast(NEONScalar2RegMiscFP16Fixed)) { \ + if ((SCA_OP_H & NEONScalar2RegMiscFP16FMask) == \ + NEONScalar2RegMiscFP16Fixed) { \ VIXL_ASSERT(CPUHas(CPUFeatures::kNEON, CPUFeatures::kNEONHalf)); \ } else { \ VIXL_ASSERT(CPUHas(CPUFeatures::kFPHalf)); \ } \ op = SCA_OP_H; \ } else { \ - if ((static_cast(SCA_OP) & \ - static_cast(NEONScalar2RegMiscFMask)) == \ - static_cast(NEONScalar2RegMiscFixed)) { \ + if ((SCA_OP & NEONScalar2RegMiscFMask) == NEONScalar2RegMiscFixed) { \ VIXL_ASSERT(CPUHas(CPUFeatures::kNEON)); \ } \ VIXL_ASSERT(vd.Is1S() || vd.Is1D()); \ @@ -3915,7 +3964,7 @@ void Assembler::NEON3SameFP16(const VRegister& vd, VIXL_ASSERT(CPUHas(CPUFeatures::kNEONHalf)); \ op = VEC_OP##_H; \ if (vd.Is8H()) { \ - op |= static_cast(NEON_Q); \ + op |= NEON_Q; \ } \ } else { \ op = VEC_OP; \ @@ -3981,7 +4030,7 @@ void Assembler::NEON2RegMisc(const VRegister& vd, Instr format, op = vop; if (vd.IsScalar()) { - op |= static_cast(NEON_Q) | static_cast(NEONScalar); + op |= NEON_Q | NEONScalar; format = SFormat(vd); } else { format = VFormat(vd); @@ -4057,7 +4106,7 @@ void Assembler::NEONFP2RegMisc(const VRegister& vd, Instr op = vop; if (vd.IsScalar()) { VIXL_ASSERT(vd.Is1S() || vd.Is1D()); - op |= static_cast(NEON_Q) | static_cast(NEONScalar); + op |= NEON_Q | NEONScalar; } else { VIXL_ASSERT(vd.Is2S() || vd.Is2D() || vd.Is4S()); } @@ -4077,11 +4126,11 @@ void Assembler::NEONFP2RegMiscFP16(const VRegister& vd, Instr op = vop; if (vd.IsScalar()) { VIXL_ASSERT(vd.Is1H()); - op |= static_cast(NEON_Q) | static_cast(NEONScalar); + op |= NEON_Q | NEONScalar; } else { VIXL_ASSERT(vd.Is4H() || vd.Is8H()); if (vd.Is8H()) { - op |= static_cast(NEON_Q); + op |= NEON_Q; } } @@ -4273,9 +4322,7 @@ NEON_3SAME_LIST(VIXL_DEFINE_ASM_FUNC) op = SCA_OP_H; \ } else { \ VIXL_ASSERT(vd.Is1H() || vd.Is1S() || vd.Is1D()); \ - if ((static_cast(SCA_OP) & \ - static_cast(NEONScalar3SameFMask)) == \ - static_cast(NEONScalar3SameFixed)) { \ + if ((SCA_OP & NEONScalar3SameFMask) == NEONScalar3SameFixed) { \ VIXL_ASSERT(CPUHas(CPUFeatures::kNEON)); \ if (vd.Is1H()) VIXL_ASSERT(CPUHas(CPUFeatures::kNEONHalf)); \ } else if (vd.Is1H()) { \ @@ -4341,11 +4388,11 @@ void Assembler::sqrdmlah(const VRegister& vd, const VRegister& vm) { VIXL_ASSERT(CPUHas(CPUFeatures::kNEON, CPUFeatures::kRDM)); VIXL_ASSERT(AreSameFormat(vd, vn, vm)); - VIXL_ASSERT(vd.IsVector() || !vd.IsQ()); + VIXL_ASSERT(vd.IsLaneSizeH() || vd.IsLaneSizeS()); Instr format, op = NEON_SQRDMLAH; if (vd.IsScalar()) { - op |= static_cast(NEON_Q) | static_cast(NEONScalar); + op |= NEON_Q | NEONScalar; format = SFormat(vd); } else { format = VFormat(vd); @@ -4360,11 +4407,11 @@ void Assembler::sqrdmlsh(const VRegister& vd, const VRegister& vm) { VIXL_ASSERT(CPUHas(CPUFeatures::kNEON, CPUFeatures::kRDM)); VIXL_ASSERT(AreSameFormat(vd, vn, vm)); - VIXL_ASSERT(vd.IsVector() || !vd.IsQ()); + VIXL_ASSERT(vd.IsLaneSizeH() || vd.IsLaneSizeS()); Instr format, op = NEON_SQRDMLSH; if (vd.IsScalar()) { - op |= static_cast(NEON_Q) | static_cast(NEONScalar); + op |= NEON_Q | NEONScalar; format = SFormat(vd); } else { format = VFormat(vd); @@ -4625,13 +4672,13 @@ void Assembler::NEONFPByElement(const VRegister& vd, } if (vd.IsScalar()) { - op |= static_cast(NEON_Q) | static_cast(NEONScalar); + op |= NEON_Q | NEONScalar; } if (!vm.Is1H()) { op |= FPFormat(vd); } else if (vd.Is8H()) { - op |= static_cast(NEON_Q); + op |= NEON_Q; } Emit(op | ImmNEONHLM(vm_index, index_num_bits) | Rm(vm) | Rn(vn) | Rd(vd)); @@ -4653,7 +4700,7 @@ void Assembler::NEONByElement(const VRegister& vd, Instr format, op = vop; int index_num_bits = vm.Is1H() ? 3 : 2; if (vd.IsScalar()) { - op |= static_cast(NEONScalar) | static_cast(NEON_Q); + op |= NEONScalar | NEON_Q; format = SFormat(vn); } else { format = VFormat(vn); @@ -4681,7 +4728,7 @@ void Assembler::NEONByElementL(const VRegister& vd, Instr format, op = vop; int index_num_bits = vm.Is1H() ? 3 : 2; if (vd.IsScalar()) { - op |= static_cast(NEONScalar) | static_cast(NEON_Q); + op |= NEONScalar | NEON_Q; format = SFormat(vn); } else { format = VFormat(vn); @@ -4917,7 +4964,7 @@ void Assembler::NEONXtn(const VRegister& vd, if (vd.IsScalar()) { VIXL_ASSERT((vd.Is1B() && vn.Is1H()) || (vd.Is1H() && vn.Is1S()) || (vd.Is1S() && vn.Is1D())); - op |= static_cast(NEON_Q) | static_cast(NEONScalar); + op |= NEON_Q | NEONScalar; format = SFormat(vd); } else { VIXL_ASSERT((vd.Is8B() && vn.Is8H()) || (vd.Is4H() && vn.Is4S()) || @@ -5829,6 +5876,247 @@ void Assembler::ummla(const VRegister& vd, const VRegister& vn, const VRegister& Emit(0x6e80a400 | Rd(vd) | Rn(vn) | Rm(vm)); } +void Assembler::bcax(const VRegister& vd, const VRegister& vn, const VRegister& vm, const VRegister& va) { + VIXL_ASSERT(CPUHas(CPUFeatures::kNEON)); + VIXL_ASSERT(CPUHas(CPUFeatures::kSHA3)); + VIXL_ASSERT(vd.Is16B() && vn.Is16B() && vm.Is16B()); + + Emit(0xce200000 | Rd(vd) | Rn(vn) | Rm(vm) | Ra(va)); +} + +void Assembler::eor3(const VRegister& vd, const VRegister& vn, const VRegister& vm, const VRegister& va) { + VIXL_ASSERT(CPUHas(CPUFeatures::kNEON)); + VIXL_ASSERT(CPUHas(CPUFeatures::kSHA3)); + VIXL_ASSERT(vd.Is16B() && vn.Is16B() && vm.Is16B() && va.Is16B()); + + Emit(0xce000000 | Rd(vd) | Rn(vn) | Rm(vm) | Ra(va)); +} + +void Assembler::xar(const VRegister& vd, const VRegister& vn, const VRegister& vm, int rotate) { + VIXL_ASSERT(CPUHas(CPUFeatures::kNEON)); + VIXL_ASSERT(CPUHas(CPUFeatures::kSHA3)); + VIXL_ASSERT(vd.Is2D() && vn.Is2D() && vm.Is2D()); + VIXL_ASSERT(IsUint6(rotate)); + + Emit(0xce800000 | Rd(vd) | Rn(vn) | Rm(vm) | rotate << 10); +} + +void Assembler::rax1(const VRegister& vd, const VRegister& vn, const VRegister& vm) { + VIXL_ASSERT(CPUHas(CPUFeatures::kNEON)); + VIXL_ASSERT(CPUHas(CPUFeatures::kSHA3)); + VIXL_ASSERT(vd.Is2D() && vn.Is2D() && vm.Is2D()); + + Emit(0xce608c00 | Rd(vd) | Rn(vn) | Rm(vm)); +} + +void Assembler::sha1c(const VRegister& vd, const VRegister& vn, const VRegister& vm) { + VIXL_ASSERT(CPUHas(CPUFeatures::kNEON)); + VIXL_ASSERT(CPUHas(CPUFeatures::kSHA1)); + VIXL_ASSERT(vd.IsQ() && vn.IsS() && vm.Is4S()); + + Emit(0x5e000000 | Rd(vd) | Rn(vn) | Rm(vm)); +} + +void Assembler::sha1h(const VRegister& sd, const VRegister& sn) { + VIXL_ASSERT(CPUHas(CPUFeatures::kNEON)); + VIXL_ASSERT(CPUHas(CPUFeatures::kSHA1)); + VIXL_ASSERT(sd.IsS() && sn.IsS()); + + Emit(0x5e280800 | Rd(sd) | Rn(sn)); +} + +void Assembler::sha1m(const VRegister& vd, const VRegister& vn, const VRegister& vm) { + VIXL_ASSERT(CPUHas(CPUFeatures::kNEON)); + VIXL_ASSERT(CPUHas(CPUFeatures::kSHA1)); + VIXL_ASSERT(vd.IsQ() && vn.IsS() && vm.Is4S()); + + Emit(0x5e002000 | Rd(vd) | Rn(vn) | Rm(vm)); +} + +void Assembler::sha1p(const VRegister& vd, const VRegister& vn, const VRegister& vm) { + VIXL_ASSERT(CPUHas(CPUFeatures::kNEON)); + VIXL_ASSERT(CPUHas(CPUFeatures::kSHA1)); + VIXL_ASSERT(vd.IsQ() && vn.IsS() && vm.Is4S()); + + Emit(0x5e001000 | Rd(vd) | Rn(vn) | Rm(vm)); +} + +void Assembler::sha1su0(const VRegister& vd, const VRegister& vn, const VRegister& vm) { + VIXL_ASSERT(CPUHas(CPUFeatures::kNEON)); + VIXL_ASSERT(CPUHas(CPUFeatures::kSHA1)); + VIXL_ASSERT(vd.Is4S() && vn.Is4S() && vm.Is4S()); + + Emit(0x5e003000 | Rd(vd) | Rn(vn) | Rm(vm)); +} + +void Assembler::sha1su1(const VRegister& vd, const VRegister& vn) { + VIXL_ASSERT(CPUHas(CPUFeatures::kNEON)); + VIXL_ASSERT(CPUHas(CPUFeatures::kSHA1)); + VIXL_ASSERT(vd.Is4S() && vn.Is4S()); + + Emit(0x5e281800 | Rd(vd) | Rn(vn)); +} + +void Assembler::sha256h(const VRegister& vd, const VRegister& vn, const VRegister& vm) { + VIXL_ASSERT(CPUHas(CPUFeatures::kNEON)); + VIXL_ASSERT(CPUHas(CPUFeatures::kSHA2)); + VIXL_ASSERT(vd.IsQ() && vn.IsQ() && vm.Is4S()); + + Emit(0x5e004000 | Rd(vd) | Rn(vn) | Rm(vm)); +} + +void Assembler::sha256h2(const VRegister& vd, const VRegister& vn, const VRegister& vm) { + VIXL_ASSERT(CPUHas(CPUFeatures::kNEON)); + VIXL_ASSERT(CPUHas(CPUFeatures::kSHA2)); + VIXL_ASSERT(vd.IsQ() && vn.IsQ() && vm.Is4S()); + + Emit(0x5e005000 | Rd(vd) | Rn(vn) | Rm(vm)); +} + +void Assembler::sha256su0(const VRegister& vd, const VRegister& vn) { + VIXL_ASSERT(CPUHas(CPUFeatures::kNEON)); + VIXL_ASSERT(CPUHas(CPUFeatures::kSHA2)); + VIXL_ASSERT(vd.Is4S() && vn.Is4S()); + + Emit(0x5e282800 | Rd(vd) | Rn(vn)); +} + +void Assembler::sha256su1(const VRegister& vd, const VRegister& vn, const VRegister& vm) { + VIXL_ASSERT(CPUHas(CPUFeatures::kNEON)); + VIXL_ASSERT(CPUHas(CPUFeatures::kSHA2)); + VIXL_ASSERT(vd.Is4S() && vn.Is4S() && vm.Is4S()); + + Emit(0x5e006000 | Rd(vd) | Rn(vn) | Rm(vm)); +} + +void Assembler::sha512h(const VRegister& vd, const VRegister& vn, const VRegister& vm) { + VIXL_ASSERT(CPUHas(CPUFeatures::kNEON)); + VIXL_ASSERT(CPUHas(CPUFeatures::kSHA512)); + VIXL_ASSERT(vd.IsQ() && vn.IsQ() && vm.Is2D()); + + Emit(0xce608000 | Rd(vd) | Rn(vn) | Rm(vm)); +} + +void Assembler::sha512h2(const VRegister& vd, const VRegister& vn, const VRegister& vm) { + VIXL_ASSERT(CPUHas(CPUFeatures::kNEON)); + VIXL_ASSERT(CPUHas(CPUFeatures::kSHA512)); + VIXL_ASSERT(vd.IsQ() && vn.IsQ() && vm.Is2D()); + + Emit(0xce608400 | Rd(vd) | Rn(vn) | Rm(vm)); +} + +void Assembler::sha512su0(const VRegister& vd, const VRegister& vn) { + VIXL_ASSERT(CPUHas(CPUFeatures::kNEON)); + VIXL_ASSERT(CPUHas(CPUFeatures::kSHA512)); + VIXL_ASSERT(vd.Is2D() && vn.Is2D()); + + Emit(0xcec08000 | Rd(vd) | Rn(vn)); +} + +void Assembler::sha512su1(const VRegister& vd, const VRegister& vn, const VRegister& vm) { + VIXL_ASSERT(CPUHas(CPUFeatures::kNEON)); + VIXL_ASSERT(CPUHas(CPUFeatures::kSHA512)); + VIXL_ASSERT(vd.Is2D() && vn.Is2D() && vm.Is2D()); + + Emit(0xce608800 | Rd(vd) | Rn(vn) | Rm(vm)); +} + +void Assembler::aesd(const VRegister& vd, const VRegister& vn) { + VIXL_ASSERT(CPUHas(CPUFeatures::kNEON)); + VIXL_ASSERT(CPUHas(CPUFeatures::kAES)); + VIXL_ASSERT(vd.Is16B() && vn.Is16B()); + + Emit(0x4e285800 | Rd(vd) | Rn(vn)); +} + +void Assembler::aese(const VRegister& vd, const VRegister& vn) { + VIXL_ASSERT(CPUHas(CPUFeatures::kNEON)); + VIXL_ASSERT(CPUHas(CPUFeatures::kAES)); + VIXL_ASSERT(vd.Is16B() && vn.Is16B()); + + Emit(0x4e284800 | Rd(vd) | Rn(vn)); +} + +void Assembler::aesimc(const VRegister& vd, const VRegister& vn) { + VIXL_ASSERT(CPUHas(CPUFeatures::kNEON)); + VIXL_ASSERT(CPUHas(CPUFeatures::kAES)); + VIXL_ASSERT(vd.Is16B() && vn.Is16B()); + + Emit(0x4e287800 | Rd(vd) | Rn(vn)); +} + +void Assembler::aesmc(const VRegister& vd, const VRegister& vn) { + VIXL_ASSERT(CPUHas(CPUFeatures::kNEON)); + VIXL_ASSERT(CPUHas(CPUFeatures::kAES)); + VIXL_ASSERT(vd.Is16B() && vn.Is16B()); + + Emit(0x4e286800 | Rd(vd) | Rn(vn)); +} + +void Assembler::sm3partw1(const VRegister& vd, const VRegister& vn, const VRegister& vm) { + VIXL_ASSERT(CPUHas(CPUFeatures::kNEON)); + VIXL_ASSERT(CPUHas(CPUFeatures::kSM3)); + VIXL_ASSERT(vd.Is4S() && vn.Is4S() && vm.Is4S()); + + Emit(0xce60c000 | Rd(vd) | Rn(vn) | Rm(vm)); +} + +void Assembler::sm3partw2(const VRegister& vd, const VRegister& vn, const VRegister& vm) { + VIXL_ASSERT(CPUHas(CPUFeatures::kNEON)); + VIXL_ASSERT(CPUHas(CPUFeatures::kSM3)); + VIXL_ASSERT(vd.Is4S() && vn.Is4S() && vm.Is4S()); + + Emit(0xce60c400 | Rd(vd) | Rn(vn) | Rm(vm)); +} + +void Assembler::sm3ss1(const VRegister& vd, const VRegister& vn, const VRegister& vm, const VRegister& va) { + VIXL_ASSERT(CPUHas(CPUFeatures::kNEON)); + VIXL_ASSERT(CPUHas(CPUFeatures::kSM3)); + VIXL_ASSERT(vd.Is4S() && vn.Is4S() && vm.Is4S() && va.Is4S()); + + Emit(0xce400000 | Rd(vd) | Rn(vn) | Rm(vm) | Ra(va)); +} + +void Assembler::sm3tt1a(const VRegister& vd, const VRegister& vn, const VRegister& vm, int index) { + VIXL_ASSERT(CPUHas(CPUFeatures::kNEON)); + VIXL_ASSERT(CPUHas(CPUFeatures::kSM3)); + VIXL_ASSERT(vd.Is4S() && vn.Is4S() && vm.Is4S()); + VIXL_ASSERT(IsUint2(index)); + + Instr i = static_cast(index) << 12; + Emit(0xce408000 | Rd(vd) | Rn(vn) | Rm(vm) | i); +} + +void Assembler::sm3tt1b(const VRegister& vd, const VRegister& vn, const VRegister& vm, int index) { + VIXL_ASSERT(CPUHas(CPUFeatures::kNEON)); + VIXL_ASSERT(CPUHas(CPUFeatures::kSM3)); + VIXL_ASSERT(vd.Is4S() && vn.Is4S() && vm.Is4S()); + VIXL_ASSERT(IsUint2(index)); + + Instr i = static_cast(index) << 12; + Emit(0xce408400 | Rd(vd) | Rn(vn) | Rm(vm) | i); +} + +void Assembler::sm3tt2a(const VRegister& vd, const VRegister& vn, const VRegister& vm, int index) { + VIXL_ASSERT(CPUHas(CPUFeatures::kNEON)); + VIXL_ASSERT(CPUHas(CPUFeatures::kSM3)); + VIXL_ASSERT(vd.Is4S() && vn.Is4S() && vm.Is4S()); + VIXL_ASSERT(IsUint2(index)); + + Instr i = static_cast(index) << 12; + Emit(0xce408800 | Rd(vd) | Rn(vn) | Rm(vm) | i); +} + +void Assembler::sm3tt2b(const VRegister& vd, const VRegister& vn, const VRegister& vm, int index) { + VIXL_ASSERT(CPUHas(CPUFeatures::kNEON)); + VIXL_ASSERT(CPUHas(CPUFeatures::kSM3)); + VIXL_ASSERT(vd.Is4S() && vn.Is4S() && vm.Is4S()); + VIXL_ASSERT(IsUint2(index)); + + Instr i = static_cast(index) << 12; + Emit(0xce408c00 | Rd(vd) | Rn(vn) | Rm(vm) | i); +} + // Note: // For all ToImm instructions below, a difference in case // for the same letter indicates a negated bit. @@ -6005,15 +6293,13 @@ void Assembler::AddSub(const Register& rd, rn, operand.ToExtendedRegister(), S, - static_cast(AddSubExtendedFixed) | static_cast(op)); + AddSubExtendedFixed | op); } else { - DataProcShiftedRegister(rd, rn, operand, S, - static_cast(AddSubShiftedFixed) | static_cast(op)); + DataProcShiftedRegister(rd, rn, operand, S, AddSubShiftedFixed | op); } } else { VIXL_ASSERT(operand.IsExtendedRegister()); - DataProcExtendedRegister(rd, rn, operand, S, - static_cast(AddSubExtendedFixed) | static_cast(op)); + DataProcExtendedRegister(rd, rn, operand, S, AddSubExtendedFixed | op); } } @@ -6079,7 +6365,7 @@ void Assembler::Logical(const Register& rd, } else { VIXL_ASSERT(operand.IsShiftedRegister()); VIXL_ASSERT(operand.GetRegister().GetSizeInBits() == rd.GetSizeInBits()); - Instr dp_op = static_cast(op) | static_cast(LogicalShiftedFixed); + Instr dp_op = static_cast(op | LogicalShiftedFixed); DataProcShiftedRegister(rd, rn, operand, LeaveFlags, dp_op); } } @@ -6108,14 +6394,11 @@ void Assembler::ConditionalCompare(const Register& rn, if (operand.IsImmediate()) { int64_t immediate = operand.GetImmediate(); VIXL_ASSERT(IsImmConditionalCompare(immediate)); - ccmpop = static_cast(ConditionalCompareImmediateFixed) | - static_cast(op) | + ccmpop = ConditionalCompareImmediateFixed | op | ImmCondCmp(static_cast(immediate)); } else { VIXL_ASSERT(operand.IsShiftedRegister() && (operand.GetShiftAmount() == 0)); - ccmpop = static_cast(ConditionalCompareRegisterFixed) | - static_cast(op) | - Rm(operand.GetRegister()); + ccmpop = ConditionalCompareRegisterFixed | op | Rm(operand.GetRegister()); } Emit(SF(rn) | ccmpop | Cond(cond) | Rn(rn) | Nzcv(nzcv)); } diff --git a/3rdparty/vixl/src/aarch64/cpu-features-auditor-aarch64.cc b/3rdparty/vixl/src/aarch64/cpu-features-auditor-aarch64.cc index 563ee078d2..66d29f0ecc 100644 --- a/3rdparty/vixl/src/aarch64/cpu-features-auditor-aarch64.cc +++ b/3rdparty/vixl/src/aarch64/cpu-features-auditor-aarch64.cc @@ -24,12 +24,13 @@ // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +#include "cpu-features-auditor-aarch64.h" + #include "cpu-features.h" #include "globals-vixl.h" #include "utils-vixl.h" -#include "decoder-aarch64.h" -#include "cpu-features-auditor-aarch64.h" +#include "decoder-aarch64.h" namespace vixl { namespace aarch64 { @@ -246,16 +247,41 @@ void CPUFeaturesAuditor::VisitConditionalSelect(const Instruction* instr) { void CPUFeaturesAuditor::VisitCrypto2RegSHA(const Instruction* instr) { RecordInstructionFeaturesScope scope(this); + if (form_hash_ == "sha256su0_vv_cryptosha2"_h) { + scope.Record(CPUFeatures::kNEON, CPUFeatures::kSHA2); + } else { + scope.Record(CPUFeatures::kNEON, CPUFeatures::kSHA1); + } USE(instr); } void CPUFeaturesAuditor::VisitCrypto3RegSHA(const Instruction* instr) { RecordInstructionFeaturesScope scope(this); + switch (form_hash_) { + case "sha1c_qsv_cryptosha3"_h: + case "sha1m_qsv_cryptosha3"_h: + case "sha1p_qsv_cryptosha3"_h: + case "sha1su0_vvv_cryptosha3"_h: + scope.Record(CPUFeatures::kNEON, CPUFeatures::kSHA1); + break; + case "sha256h_qqv_cryptosha3"_h: + case "sha256h2_qqv_cryptosha3"_h: + case "sha256su1_vvv_cryptosha3"_h: + scope.Record(CPUFeatures::kNEON, CPUFeatures::kSHA2); + break; + } USE(instr); } void CPUFeaturesAuditor::VisitCryptoAES(const Instruction* instr) { RecordInstructionFeaturesScope scope(this); + scope.Record(CPUFeatures::kNEON, CPUFeatures::kAES); + USE(instr); +} + +void CPUFeaturesAuditor::VisitCryptoSM3(const Instruction* instr) { + RecordInstructionFeaturesScope scope(this); + scope.Record(CPUFeatures::kNEON, CPUFeatures::kSM3); USE(instr); } @@ -735,6 +761,12 @@ void CPUFeaturesAuditor::VisitNEON3Different(const Instruction* instr) { RecordInstructionFeaturesScope scope(this); // All of these instructions require NEON. scope.Record(CPUFeatures::kNEON); + if (form_hash_ == "pmull_asimddiff_l"_h) { + if (instr->GetNEONSize() == 3) { + // Source is 1D or 2D, destination is 1Q. + scope.Record(CPUFeatures::kPmull1Q); + } + } USE(instr); } @@ -1269,91 +1301,93 @@ VIXL_SIMPLE_SVE_VISITOR_LIST(VIXL_DEFINE_SIMPLE_SVE_VISITOR) void CPUFeaturesAuditor::VisitSystem(const Instruction* instr) { RecordInstructionFeaturesScope scope(this); - if (instr->Mask(SystemHintFMask) == SystemHintFixed) { - CPUFeatures required; - switch (instr->GetInstructionBits()) { - case PACIA1716: - case PACIB1716: - case AUTIA1716: - case AUTIB1716: - case PACIAZ: - case PACIASP: - case PACIBZ: - case PACIBSP: - case AUTIAZ: - case AUTIASP: - case AUTIBZ: - case AUTIBSP: - case XPACLRI: - required.Combine(CPUFeatures::kPAuth); - break; - default: - switch (instr->GetImmHint()) { - case ESB: - required.Combine(CPUFeatures::kRAS); - break; - case BTI: - case BTI_j: - case BTI_c: - case BTI_jc: - required.Combine(CPUFeatures::kBTI); - break; - default: - break; - } - break; - } - // These are all HINT instructions, and behave as NOPs if the corresponding - // features are not implemented, so we record the corresponding features - // only if they are available. - if (available_.Has(required)) scope.Record(required); - } else if (instr->Mask(SystemSysMask) == SYS) { - switch (instr->GetSysOp()) { - // DC instruction variants. - case CGVAC: - case CGDVAC: - case CGVAP: - case CGDVAP: - case CIGVAC: - case CIGDVAC: - case GVA: - case GZVA: - scope.Record(CPUFeatures::kMTE); - break; - case CVAP: - scope.Record(CPUFeatures::kDCPoP); - break; - case CVADP: - scope.Record(CPUFeatures::kDCCVADP); - break; - case IVAU: - case CVAC: - case CVAU: - case CIVAC: - case ZVA: - // No special CPU features. - break; - } - } else if (instr->Mask(SystemPStateFMask) == SystemPStateFixed) { - switch (instr->Mask(SystemPStateMask)) { - case CFINV: - scope.Record(CPUFeatures::kFlagM); - break; - case AXFLAG: - case XAFLAG: - scope.Record(CPUFeatures::kAXFlag); - break; - } - } else if (instr->Mask(SystemSysRegFMask) == SystemSysRegFixed) { - if (instr->Mask(SystemSysRegMask) == MRS) { + CPUFeatures required; + switch (form_hash_) { + case "pacib1716_hi_hints"_h: + case "pacia1716_hi_hints"_h: + case "pacibsp_hi_hints"_h: + case "paciasp_hi_hints"_h: + case "pacibz_hi_hints"_h: + case "paciaz_hi_hints"_h: + case "autib1716_hi_hints"_h: + case "autia1716_hi_hints"_h: + case "autibsp_hi_hints"_h: + case "autiasp_hi_hints"_h: + case "autibz_hi_hints"_h: + case "autiaz_hi_hints"_h: + case "xpaclri_hi_hints"_h: + required.Combine(CPUFeatures::kPAuth); + break; + case "esb_hi_hints"_h: + required.Combine(CPUFeatures::kRAS); + break; + case "bti_hb_hints"_h: + required.Combine(CPUFeatures::kBTI); + break; + } + + // The instructions above are all HINTs and behave as NOPs if the + // corresponding features are not implemented, so we record the corresponding + // features only if they are available. + if (available_.Has(required)) scope.Record(required); + + switch (form_hash_) { + case "cfinv_m_pstate"_h: + scope.Record(CPUFeatures::kFlagM); + break; + case "axflag_m_pstate"_h: + case "xaflag_m_pstate"_h: + scope.Record(CPUFeatures::kAXFlag); + break; + case "mrs_rs_systemmove"_h: switch (instr->GetImmSystemRegister()) { case RNDR: case RNDRRS: scope.Record(CPUFeatures::kRNG); break; } - } + break; + case "sys_cr_systeminstrs"_h: + switch (instr->GetSysOp()) { + // DC instruction variants. + case CGVAC: + case CGDVAC: + case CGVAP: + case CGDVAP: + case CIGVAC: + case CIGDVAC: + case GVA: + case GZVA: + scope.Record(CPUFeatures::kMTE); + break; + case CVAP: + scope.Record(CPUFeatures::kDCPoP); + break; + case CVADP: + scope.Record(CPUFeatures::kDCCVADP); + break; + case IVAU: + case CVAC: + case CVAU: + case CIVAC: + case ZVA: + // No special CPU features. + break; + case GCSPUSHM: + case GCSSS1: + scope.Record(CPUFeatures::kGCS); + break; + } + break; + case "sysl_rc_systeminstrs"_h: + switch (instr->GetSysOp()) { + case GCSPOPM: + case GCSSS2: + scope.Record(CPUFeatures::kGCS); + break; + } + break; } } @@ -1407,9 +1441,9 @@ void CPUFeaturesAuditor::VisitUnimplemented(const Instruction* instr) { void CPUFeaturesAuditor::Visit(Metadata* metadata, const Instruction* instr) { VIXL_ASSERT(metadata->count("form") > 0); const std::string& form = (*metadata)["form"]; - uint32_t form_hash = Hash(form.c_str()); + form_hash_ = Hash(form.c_str()); const FormToVisitorFnMap* fv = CPUFeaturesAuditor::GetFormToVisitorFnMap(); - FormToVisitorFnMap::const_iterator it = fv->find(form_hash); + FormToVisitorFnMap::const_iterator it = fv->find(form_hash_); if (it == fv->end()) { RecordInstructionFeaturesScope scope(this); std::map features = { @@ -1826,10 +1860,26 @@ void CPUFeaturesAuditor::Visit(Metadata* metadata, const Instruction* instr) { {"umax_64u_minmax_imm"_h, CPUFeatures::kCSSC}, {"umin_32u_minmax_imm"_h, CPUFeatures::kCSSC}, {"umin_64u_minmax_imm"_h, CPUFeatures::kCSSC}, + {"bcax_vvv16_crypto4"_h, + CPUFeatures(CPUFeatures::kNEON, CPUFeatures::kSHA3)}, + {"eor3_vvv16_crypto4"_h, + CPUFeatures(CPUFeatures::kNEON, CPUFeatures::kSHA3)}, + {"rax1_vvv2_cryptosha512_3"_h, + CPUFeatures(CPUFeatures::kNEON, CPUFeatures::kSHA3)}, + {"xar_vvv2_crypto3_imm6"_h, + CPUFeatures(CPUFeatures::kNEON, CPUFeatures::kSHA3)}, + {"sha512h_qqv_cryptosha512_3"_h, + CPUFeatures(CPUFeatures::kNEON, CPUFeatures::kSHA512)}, + {"sha512h2_qqv_cryptosha512_3"_h, + CPUFeatures(CPUFeatures::kNEON, CPUFeatures::kSHA512)}, + {"sha512su0_vv2_cryptosha512_2"_h, + CPUFeatures(CPUFeatures::kNEON, CPUFeatures::kSHA512)}, + {"sha512su1_vvv2_cryptosha512_3"_h, + CPUFeatures(CPUFeatures::kNEON, CPUFeatures::kSHA512)}, }; - if (features.count(form_hash) > 0) { - scope.Record(features[form_hash]); + if (features.count(form_hash_) > 0) { + scope.Record(features[form_hash_]); } } else { (it->second)(this, instr); diff --git a/3rdparty/vixl/src/aarch64/decoder-aarch64.cc b/3rdparty/vixl/src/aarch64/decoder-aarch64.cc index dc56633aa5..4ff02c114d 100644 --- a/3rdparty/vixl/src/aarch64/decoder-aarch64.cc +++ b/3rdparty/vixl/src/aarch64/decoder-aarch64.cc @@ -24,12 +24,13 @@ // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +#include "decoder-aarch64.h" + #include #include "../globals-vixl.h" #include "../utils-vixl.h" -#include "decoder-aarch64.h" #include "decoder-constants-aarch64.h" namespace vixl { diff --git a/3rdparty/vixl/src/aarch64/disasm-aarch64.cc b/3rdparty/vixl/src/aarch64/disasm-aarch64.cc index 3592752c7c..ec4dfc9edb 100644 --- a/3rdparty/vixl/src/aarch64/disasm-aarch64.cc +++ b/3rdparty/vixl/src/aarch64/disasm-aarch64.cc @@ -24,12 +24,12 @@ // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +#include "disasm-aarch64.h" + #include #include #include -#include "disasm-aarch64.h" - namespace vixl { namespace aarch64 { @@ -330,6 +330,7 @@ const Disassembler::FormToVisitorFnMap *Disassembler::GetFormToVisitorFnMap() { {"frsqrte_asisdmisc_r"_h, &Disassembler::DisassembleNEONFPScalar2RegMisc}, {"scvtf_asisdmisc_r"_h, &Disassembler::DisassembleNEONFPScalar2RegMisc}, {"ucvtf_asisdmisc_r"_h, &Disassembler::DisassembleNEONFPScalar2RegMisc}, + {"pmull_asimddiff_l"_h, &Disassembler::DisassembleNEONPolynomialMul}, {"adclb_z_zzz"_h, &Disassembler::DisassembleSVEAddSubCarry}, {"adclt_z_zzz"_h, &Disassembler::DisassembleSVEAddSubCarry}, {"addhnb_z_zz"_h, &Disassembler::DisassembleSVEAddSubHigh}, @@ -752,6 +753,14 @@ const Disassembler::FormToVisitorFnMap *Disassembler::GetFormToVisitorFnMap() { {"umax_64u_minmax_imm"_h, &Disassembler::DisassembleMinMaxImm}, {"umin_32u_minmax_imm"_h, &Disassembler::DisassembleMinMaxImm}, {"umin_64u_minmax_imm"_h, &Disassembler::DisassembleMinMaxImm}, + {"bcax_vvv16_crypto4"_h, &Disassembler::DisassembleNEON4Same}, + {"eor3_vvv16_crypto4"_h, &Disassembler::DisassembleNEON4Same}, + {"xar_vvv2_crypto3_imm6"_h, &Disassembler::DisassembleNEONXar}, + {"rax1_vvv2_cryptosha512_3"_h, &Disassembler::DisassembleNEONRax1}, + {"sha512h2_qqv_cryptosha512_3"_h, &Disassembler::DisassembleSHA512}, + {"sha512h_qqv_cryptosha512_3"_h, &Disassembler::DisassembleSHA512}, + {"sha512su0_vv2_cryptosha512_2"_h, &Disassembler::DisassembleSHA512}, + {"sha512su1_vvv2_cryptosha512_3"_h, &Disassembler::DisassembleSHA512}, }; return &form_to_visitor; } // NOLINT(readability/fn_size) @@ -2017,7 +2026,7 @@ void Disassembler::DisassembleNoArgs(const Instruction *instr) { void Disassembler::VisitSystem(const Instruction *instr) { const char *mnemonic = mnemonic_.c_str(); - const char *form = "(System)"; + const char *form = ""; const char *suffix = NULL; switch (form_hash_) { @@ -2046,6 +2055,10 @@ void Disassembler::VisitSystem(const Instruction *instr) { break; } break; + case "chkfeat_hf_hints"_h: + mnemonic = "chkfeat"; + form = "x16"; + break; case "hint_hm_hints"_h: form = "'IH"; break; @@ -2066,9 +2079,6 @@ void Disassembler::VisitSystem(const Instruction *instr) { break; } case Hash("sys_cr_systeminstrs"): { - mnemonic = "dc"; - suffix = ", 'Xt"; - const std::map dcop = { {IVAU, "ivau"}, {CVAC, "cvac"}, @@ -2091,17 +2101,36 @@ void Disassembler::VisitSystem(const Instruction *instr) { if (dcop.count(sysop)) { if (sysop == IVAU) { mnemonic = "ic"; + } else { + mnemonic = "dc"; } form = dcop.at(sysop); + suffix = ", 'Xt"; + } else if (sysop == GCSSS1) { + mnemonic = "gcsss1"; + form = "'Xt"; + } else if (sysop == GCSPUSHM) { + mnemonic = "gcspushm"; + form = "'Xt"; } else { mnemonic = "sys"; form = "'G1, 'Kn, 'Km, 'G2"; - if (instr->GetRt() == 31) { - suffix = NULL; + if (instr->GetRt() < 31) { + suffix = ", 'Xt"; } - break; } + break; } + case "sysl_rc_systeminstrs"_h: + uint32_t sysop = instr->GetSysOp(); + if (sysop == GCSPOPM) { + mnemonic = "gcspopm"; + form = (instr->GetRt() == 31) ? "" : "'Xt"; + } else if (sysop == GCSSS2) { + mnemonic = "gcsss2"; + form = "'Xt"; + } + break; } Format(instr, mnemonic, form, suffix); } @@ -2147,17 +2176,64 @@ void Disassembler::VisitException(const Instruction *instr) { void Disassembler::VisitCrypto2RegSHA(const Instruction *instr) { - VisitUnimplemented(instr); + const char *form = "'Vd.4s, 'Vn.4s"; + if (form_hash_ == "sha1h_ss_cryptosha2"_h) { + form = "'Sd, 'Sn"; + } + FormatWithDecodedMnemonic(instr, form); } void Disassembler::VisitCrypto3RegSHA(const Instruction *instr) { - VisitUnimplemented(instr); + const char *form = "'Qd, 'Sn, 'Vm.4s"; + switch (form_hash_) { + case "sha1su0_vvv_cryptosha3"_h: + case "sha256su1_vvv_cryptosha3"_h: + form = "'Vd.4s, 'Vn.4s, 'Vm.4s"; + break; + case "sha256h_qqv_cryptosha3"_h: + case "sha256h2_qqv_cryptosha3"_h: + form = "'Qd, 'Qn, 'Vm.4s"; + break; + } + FormatWithDecodedMnemonic(instr, form); } void Disassembler::VisitCryptoAES(const Instruction *instr) { - VisitUnimplemented(instr); + FormatWithDecodedMnemonic(instr, "'Vd.16b, 'Vn.16b"); +} + +void Disassembler::VisitCryptoSM3(const Instruction *instr) { + const char *form = "'Vd.4s, 'Vn.4s, 'Vm."; + const char *suffix = "4s"; + + switch (form_hash_) { + case "sm3ss1_vvv4_crypto4"_h: + suffix = "4s, 'Va.4s"; + break; + case "sm3tt1a_vvv4_crypto3_imm2"_h: + case "sm3tt1b_vvv4_crypto3_imm2"_h: + case "sm3tt2a_vvv4_crypto3_imm2"_h: + case "sm3tt2b_vvv_crypto3_imm2"_h: + suffix = "s['u1312]"; + break; + } + + FormatWithDecodedMnemonic(instr, form, suffix); +} + +void Disassembler::DisassembleSHA512(const Instruction *instr) { + const char *form = "'Qd, 'Qn, 'Vm.2d"; + const char *suffix = NULL; + switch (form_hash_) { + case "sha512su1_vvv2_cryptosha512_3"_h: + suffix = ", 'Vm.2d"; + VIXL_FALLTHROUGH(); + case "sha512su0_vv2_cryptosha512_2"_h: + form = "'Vd.2d, 'Vn.2d"; + } + FormatWithDecodedMnemonic(instr, form, suffix); } void Disassembler::DisassembleNEON2RegAddlp(const Instruction *instr) { @@ -2373,13 +2449,19 @@ void Disassembler::VisitNEON3SameFP16(const Instruction *instr) { } void Disassembler::VisitNEON3SameExtra(const Instruction *instr) { - static const NEONFormatMap map_usdot = {{30}, {NF_8B, NF_16B}}; + static const NEONFormatMap map_dot = + {{23, 22, 30}, {NF_UNDEF, NF_UNDEF, NF_UNDEF, NF_UNDEF, NF_2S, NF_4S}}; + static const NEONFormatMap map_fc = + {{23, 22, 30}, + {NF_UNDEF, NF_UNDEF, NF_4H, NF_8H, NF_2S, NF_4S, NF_UNDEF, NF_2D}}; + static const NEONFormatMap map_rdm = + {{23, 22, 30}, {NF_UNDEF, NF_UNDEF, NF_4H, NF_8H, NF_2S, NF_4S}}; const char *mnemonic = mnemonic_.c_str(); const char *form = "'Vd.%s, 'Vn.%s, 'Vm.%s"; const char *suffix = NULL; - NEONFormatDecoder nfd(instr); + NEONFormatDecoder nfd(instr, &map_fc); switch (form_hash_) { case "fcmla_asimdsame2_c"_h: @@ -2392,17 +2474,28 @@ void Disassembler::VisitNEON3SameExtra(const Instruction *instr) { case "sdot_asimdsame2_d"_h: case "udot_asimdsame2_d"_h: case "usdot_asimdsame2_d"_h: - nfd.SetFormatMap(1, &map_usdot); - nfd.SetFormatMap(2, &map_usdot); + nfd.SetFormatMaps(nfd.LogicalFormatMap()); + nfd.SetFormatMap(0, &map_dot); break; default: - // sqrdml[as]h - nothing to do. + nfd.SetFormatMaps(&map_rdm); break; } Format(instr, mnemonic, nfd.Substitute(form), suffix); } +void Disassembler::DisassembleNEON4Same(const Instruction *instr) { + FormatWithDecodedMnemonic(instr, "'Vd.16b, 'Vn.16b, 'Vm.16b, 'Va.16b"); +} + +void Disassembler::DisassembleNEONXar(const Instruction *instr) { + FormatWithDecodedMnemonic(instr, "'Vd.2d, 'Vn.2d, 'Vm.2d, #'u1510"); +} + +void Disassembler::DisassembleNEONRax1(const Instruction *instr) { + FormatWithDecodedMnemonic(instr, "'Vd.2d, 'Vn.2d, 'Vm.2d"); +} void Disassembler::VisitNEON3Different(const Instruction *instr) { const char *mnemonic = mnemonic_.c_str(); @@ -2425,11 +2518,6 @@ void Disassembler::VisitNEON3Different(const Instruction *instr) { nfd.SetFormatMaps(nfd.LongIntegerFormatMap()); nfd.SetFormatMap(0, nfd.IntegerFormatMap()); break; - case "pmull_asimddiff_l"_h: - if (nfd.GetVectorFormat(0) != kFormat8H) { - mnemonic = NULL; - } - break; case "sqdmlal_asimddiff_l"_h: case "sqdmlsl_asimddiff_l"_h: case "sqdmull_asimddiff_l"_h: @@ -2441,6 +2529,22 @@ void Disassembler::VisitNEON3Different(const Instruction *instr) { Format(instr, nfd.Mnemonic(mnemonic), nfd.Substitute(form)); } +void Disassembler::DisassembleNEONPolynomialMul(const Instruction *instr) { + const char *mnemonic = instr->ExtractBit(30) ? "pmull2" : "pmull"; + const char *form = NULL; + int size = instr->ExtractBits(23, 22); + if (size == 0) { + // Bits 30:27 of the instruction are x001, where x is the Q bit. Map + // this to "8" and "16" by adding 7. + form = "'Vd.8h, 'Vn.'u3127+7b, 'Vm.'u3127+7b"; + } else if (size == 3) { + form = "'Vd.1q, 'Vn.'?30:21d, 'Vm.'?30:21d"; + } else { + mnemonic = NULL; + } + Format(instr, mnemonic, form); +} + void Disassembler::DisassembleNEONFPAcrossLanes(const Instruction *instr) { const char *mnemonic = mnemonic_.c_str(); const char *form = "'Sd, 'Vn.4s"; @@ -3298,6 +3402,8 @@ void Disassembler::VisitNEONScalar3Same(const Instruction *instr) { break; case "sqdmulh_asisdsame_only"_h: case "sqrdmulh_asisdsame_only"_h: + case "sqrdmlah_asisdsame2_only"_h: + case "sqrdmlsh_asisdsame2_only"_h: if ((vform == kFormatB) || (vform == kFormatD)) { mnemonic = NULL; } @@ -3916,8 +4022,7 @@ static bool SVEMoveMaskPreferred(uint64_t value, int lane_bytes_log2) { } // Check 0x0000pq00_0000pq00 or 0xffffpq00_ffffpq00. - uint64_t rotvalue = RotateRight(value, 32, 64); - if (value == rotvalue) { + if (AllWordsMatch(value)) { generic_value &= 0xffffffff; if ((generic_value == 0xffff) || (generic_value == UINT32_MAX)) { return false; @@ -3925,8 +4030,7 @@ static bool SVEMoveMaskPreferred(uint64_t value, int lane_bytes_log2) { } // Check 0xpq00pq00_pq00pq00. - rotvalue = RotateRight(value, 16, 64); - if (value == rotvalue) { + if (AllHalfwordsMatch(value)) { return false; } } else { @@ -3940,8 +4044,7 @@ static bool SVEMoveMaskPreferred(uint64_t value, int lane_bytes_log2) { } // Check 0x000000pq_000000pq or 0xffffffpq_ffffffpq. - uint64_t rotvalue = RotateRight(value, 32, 64); - if (value == rotvalue) { + if (AllWordsMatch(value)) { generic_value &= 0xffffffff; if ((generic_value == 0xff) || (generic_value == UINT32_MAX)) { return false; @@ -3949,8 +4052,7 @@ static bool SVEMoveMaskPreferred(uint64_t value, int lane_bytes_log2) { } // Check 0x00pq00pq_00pq00pq or 0xffpqffpq_ffpqffpq. - rotvalue = RotateRight(value, 16, 64); - if (value == rotvalue) { + if (AllHalfwordsMatch(value)) { generic_value &= 0xffff; if ((generic_value == 0xff) || (generic_value == UINT16_MAX)) { return false; @@ -3958,8 +4060,7 @@ static bool SVEMoveMaskPreferred(uint64_t value, int lane_bytes_log2) { } // Check 0xpqpqpqpq_pqpqpqpq. - rotvalue = RotateRight(value, 8, 64); - if (value == rotvalue) { + if (AllBytesMatch(value)) { return false; } } diff --git a/3rdparty/vixl/src/aarch64/instructions-aarch64.cc b/3rdparty/vixl/src/aarch64/instructions-aarch64.cc index a2d0547219..2ac3bcaca0 100644 --- a/3rdparty/vixl/src/aarch64/instructions-aarch64.cc +++ b/3rdparty/vixl/src/aarch64/instructions-aarch64.cc @@ -25,6 +25,7 @@ // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "instructions-aarch64.h" + #include "assembler-aarch64.h" namespace vixl { @@ -1010,6 +1011,8 @@ VectorFormat VectorFormatHalfWidth(VectorFormat vform) { return kFormat4H; case kFormat2D: return kFormat2S; + case kFormat1Q: + return kFormat1D; case kFormatH: return kFormatB; case kFormatS: @@ -1094,6 +1097,8 @@ VectorFormat VectorFormatHalfWidthDoubleLanes(VectorFormat vform) { return kFormat2S; case kFormat2D: return kFormat4S; + case kFormat1Q: + return kFormat2D; case kFormatVnH: return kFormatVnB; case kFormatVnS: @@ -1245,6 +1250,7 @@ unsigned RegisterSizeInBitsFromFormat(VectorFormat vform) { case kFormat8H: case kFormat4S: case kFormat2D: + case kFormat1Q: return kQRegSize; default: VIXL_UNREACHABLE(); @@ -1282,6 +1288,7 @@ unsigned LaneSizeInBitsFromFormat(VectorFormat vform) { case kFormat2D: case kFormatVnD: return 64; + case kFormat1Q: case kFormatVnQ: return 128; case kFormatVnO: @@ -1347,6 +1354,7 @@ int LaneCountFromFormat(VectorFormat vform) { case kFormat2D: return 2; case kFormat1D: + case kFormat1Q: case kFormatB: case kFormatH: case kFormatS: diff --git a/3rdparty/vixl/src/aarch64/logic-aarch64.cc b/3rdparty/vixl/src/aarch64/logic-aarch64.cc index 11229ad658..246ffe9c58 100644 --- a/3rdparty/vixl/src/aarch64/logic-aarch64.cc +++ b/3rdparty/vixl/src/aarch64/logic-aarch64.cc @@ -36,33 +36,33 @@ namespace aarch64 { using vixl::internal::SimFloat16; template -bool IsFloat64() { +constexpr bool IsFloat64() { return false; } template <> -bool IsFloat64() { +constexpr bool IsFloat64() { return true; } template -bool IsFloat32() { +constexpr bool IsFloat32() { return false; } template <> -bool IsFloat32() { +constexpr bool IsFloat32() { return true; } template -bool IsFloat16() { +constexpr bool IsFloat16() { return false; } template <> -bool IsFloat16() { +constexpr bool IsFloat16() { return true; } template <> -bool IsFloat16() { +constexpr bool IsFloat16() { return true; } @@ -168,11 +168,12 @@ SimFloat16 Simulator::UFixedToFloat16(uint64_t src, uint64_t Simulator::GenerateRandomTag(uint16_t exclude) { - uint64_t rtag = nrand48(rand_state_) >> 28; + // Generate a 4 bit integer from a 48bit random number + uint64_t rtag = rand_gen_() >> 44; VIXL_ASSERT(IsUint4(rtag)); if (exclude == 0) { - exclude = nrand48(rand_state_) >> 27; + exclude = static_cast(rand_gen_() >> 44); } // TODO: implement this to better match the specification, which calls for a @@ -182,24 +183,28 @@ uint64_t Simulator::GenerateRandomTag(uint16_t exclude) { } -void Simulator::ld1(VectorFormat vform, LogicVRegister dst, uint64_t addr) { +bool Simulator::ld1(VectorFormat vform, LogicVRegister dst, uint64_t addr) { dst.ClearForWrite(vform); for (int i = 0; i < LaneCountFromFormat(vform); i++) { - LoadLane(dst, vform, i, addr); + if (!LoadLane(dst, vform, i, addr)) { + return false; + } addr += LaneSizeInBytesFromFormat(vform); } + return true; } -void Simulator::ld1(VectorFormat vform, +bool Simulator::ld1(VectorFormat vform, LogicVRegister dst, int index, uint64_t addr) { - LoadLane(dst, vform, index, addr); + dst.ClearForWrite(vform); + return LoadLane(dst, vform, index, addr); } -void Simulator::ld1r(VectorFormat vform, +bool Simulator::ld1r(VectorFormat vform, VectorFormat unpack_vform, LogicVRegister dst, uint64_t addr, @@ -208,20 +213,25 @@ void Simulator::ld1r(VectorFormat vform, dst.ClearForWrite(vform); for (int i = 0; i < LaneCountFromFormat(vform); i++) { if (is_signed) { - LoadIntToLane(dst, vform, unpack_size, i, addr); + if (!LoadIntToLane(dst, vform, unpack_size, i, addr)) { + return false; + } } else { - LoadUintToLane(dst, vform, unpack_size, i, addr); + if (!LoadUintToLane(dst, vform, unpack_size, i, addr)) { + return false; + } } } + return true; } -void Simulator::ld1r(VectorFormat vform, LogicVRegister dst, uint64_t addr) { - ld1r(vform, vform, dst, addr); +bool Simulator::ld1r(VectorFormat vform, LogicVRegister dst, uint64_t addr) { + return ld1r(vform, vform, dst, addr); } -void Simulator::ld2(VectorFormat vform, +bool Simulator::ld2(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, uint64_t addr1) { @@ -230,15 +240,17 @@ void Simulator::ld2(VectorFormat vform, int esize = LaneSizeInBytesFromFormat(vform); uint64_t addr2 = addr1 + esize; for (int i = 0; i < LaneCountFromFormat(vform); i++) { - LoadLane(dst1, vform, i, addr1); - LoadLane(dst2, vform, i, addr2); + if (!LoadLane(dst1, vform, i, addr1) || !LoadLane(dst2, vform, i, addr2)) { + return false; + } addr1 += 2 * esize; addr2 += 2 * esize; } + return true; } -void Simulator::ld2(VectorFormat vform, +bool Simulator::ld2(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, int index, @@ -246,12 +258,12 @@ void Simulator::ld2(VectorFormat vform, dst1.ClearForWrite(vform); dst2.ClearForWrite(vform); uint64_t addr2 = addr1 + LaneSizeInBytesFromFormat(vform); - LoadLane(dst1, vform, index, addr1); - LoadLane(dst2, vform, index, addr2); + return (LoadLane(dst1, vform, index, addr1) && + LoadLane(dst2, vform, index, addr2)); } -void Simulator::ld2r(VectorFormat vform, +bool Simulator::ld2r(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, uint64_t addr) { @@ -259,13 +271,15 @@ void Simulator::ld2r(VectorFormat vform, dst2.ClearForWrite(vform); uint64_t addr2 = addr + LaneSizeInBytesFromFormat(vform); for (int i = 0; i < LaneCountFromFormat(vform); i++) { - LoadLane(dst1, vform, i, addr); - LoadLane(dst2, vform, i, addr2); + if (!LoadLane(dst1, vform, i, addr) || !LoadLane(dst2, vform, i, addr2)) { + return false; + } } + return true; } -void Simulator::ld3(VectorFormat vform, +bool Simulator::ld3(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, LogicVRegister dst3, @@ -277,17 +291,19 @@ void Simulator::ld3(VectorFormat vform, uint64_t addr2 = addr1 + esize; uint64_t addr3 = addr2 + esize; for (int i = 0; i < LaneCountFromFormat(vform); i++) { - LoadLane(dst1, vform, i, addr1); - LoadLane(dst2, vform, i, addr2); - LoadLane(dst3, vform, i, addr3); + if (!LoadLane(dst1, vform, i, addr1) || !LoadLane(dst2, vform, i, addr2) || + !LoadLane(dst3, vform, i, addr3)) { + return false; + } addr1 += 3 * esize; addr2 += 3 * esize; addr3 += 3 * esize; } + return true; } -void Simulator::ld3(VectorFormat vform, +bool Simulator::ld3(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, LogicVRegister dst3, @@ -298,13 +314,13 @@ void Simulator::ld3(VectorFormat vform, dst3.ClearForWrite(vform); uint64_t addr2 = addr1 + LaneSizeInBytesFromFormat(vform); uint64_t addr3 = addr2 + LaneSizeInBytesFromFormat(vform); - LoadLane(dst1, vform, index, addr1); - LoadLane(dst2, vform, index, addr2); - LoadLane(dst3, vform, index, addr3); + return (LoadLane(dst1, vform, index, addr1) && + LoadLane(dst2, vform, index, addr2) && + LoadLane(dst3, vform, index, addr3)); } -void Simulator::ld3r(VectorFormat vform, +bool Simulator::ld3r(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, LogicVRegister dst3, @@ -315,14 +331,16 @@ void Simulator::ld3r(VectorFormat vform, uint64_t addr2 = addr + LaneSizeInBytesFromFormat(vform); uint64_t addr3 = addr2 + LaneSizeInBytesFromFormat(vform); for (int i = 0; i < LaneCountFromFormat(vform); i++) { - LoadLane(dst1, vform, i, addr); - LoadLane(dst2, vform, i, addr2); - LoadLane(dst3, vform, i, addr3); + if (!LoadLane(dst1, vform, i, addr) || !LoadLane(dst2, vform, i, addr2) || + !LoadLane(dst3, vform, i, addr3)) { + return false; + } } + return true; } -void Simulator::ld4(VectorFormat vform, +bool Simulator::ld4(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, LogicVRegister dst3, @@ -337,19 +355,20 @@ void Simulator::ld4(VectorFormat vform, uint64_t addr3 = addr2 + esize; uint64_t addr4 = addr3 + esize; for (int i = 0; i < LaneCountFromFormat(vform); i++) { - LoadLane(dst1, vform, i, addr1); - LoadLane(dst2, vform, i, addr2); - LoadLane(dst3, vform, i, addr3); - LoadLane(dst4, vform, i, addr4); + if (!LoadLane(dst1, vform, i, addr1) || !LoadLane(dst2, vform, i, addr2) || + !LoadLane(dst3, vform, i, addr3) || !LoadLane(dst4, vform, i, addr4)) { + return false; + } addr1 += 4 * esize; addr2 += 4 * esize; addr3 += 4 * esize; addr4 += 4 * esize; } + return true; } -void Simulator::ld4(VectorFormat vform, +bool Simulator::ld4(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, LogicVRegister dst3, @@ -363,14 +382,14 @@ void Simulator::ld4(VectorFormat vform, uint64_t addr2 = addr1 + LaneSizeInBytesFromFormat(vform); uint64_t addr3 = addr2 + LaneSizeInBytesFromFormat(vform); uint64_t addr4 = addr3 + LaneSizeInBytesFromFormat(vform); - LoadLane(dst1, vform, index, addr1); - LoadLane(dst2, vform, index, addr2); - LoadLane(dst3, vform, index, addr3); - LoadLane(dst4, vform, index, addr4); + return (LoadLane(dst1, vform, index, addr1) && + LoadLane(dst2, vform, index, addr2) && + LoadLane(dst3, vform, index, addr3) && + LoadLane(dst4, vform, index, addr4)); } -void Simulator::ld4r(VectorFormat vform, +bool Simulator::ld4r(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, LogicVRegister dst3, @@ -384,57 +403,61 @@ void Simulator::ld4r(VectorFormat vform, uint64_t addr3 = addr2 + LaneSizeInBytesFromFormat(vform); uint64_t addr4 = addr3 + LaneSizeInBytesFromFormat(vform); for (int i = 0; i < LaneCountFromFormat(vform); i++) { - LoadLane(dst1, vform, i, addr); - LoadLane(dst2, vform, i, addr2); - LoadLane(dst3, vform, i, addr3); - LoadLane(dst4, vform, i, addr4); + if (!LoadLane(dst1, vform, i, addr) || !LoadLane(dst2, vform, i, addr2) || + !LoadLane(dst3, vform, i, addr3) || !LoadLane(dst4, vform, i, addr4)) { + return false; + } } + return true; } -void Simulator::st1(VectorFormat vform, LogicVRegister src, uint64_t addr) { +bool Simulator::st1(VectorFormat vform, LogicVRegister src, uint64_t addr) { for (int i = 0; i < LaneCountFromFormat(vform); i++) { - StoreLane(src, vform, i, addr); + if (!StoreLane(src, vform, i, addr)) return false; addr += LaneSizeInBytesFromFormat(vform); } + return true; } -void Simulator::st1(VectorFormat vform, +bool Simulator::st1(VectorFormat vform, LogicVRegister src, int index, uint64_t addr) { - StoreLane(src, vform, index, addr); + return StoreLane(src, vform, index, addr); } -void Simulator::st2(VectorFormat vform, +bool Simulator::st2(VectorFormat vform, LogicVRegister src, LogicVRegister src2, uint64_t addr) { int esize = LaneSizeInBytesFromFormat(vform); uint64_t addr2 = addr + esize; for (int i = 0; i < LaneCountFromFormat(vform); i++) { - StoreLane(src, vform, i, addr); - StoreLane(src2, vform, i, addr2); + if (!StoreLane(src, vform, i, addr) || !StoreLane(src2, vform, i, addr2)) { + return false; + } addr += 2 * esize; addr2 += 2 * esize; } + return true; } -void Simulator::st2(VectorFormat vform, +bool Simulator::st2(VectorFormat vform, LogicVRegister src, LogicVRegister src2, int index, uint64_t addr) { int esize = LaneSizeInBytesFromFormat(vform); - StoreLane(src, vform, index, addr); - StoreLane(src2, vform, index, addr + 1 * esize); + return (StoreLane(src, vform, index, addr) && + StoreLane(src2, vform, index, addr + 1 * esize)); } -void Simulator::st3(VectorFormat vform, +bool Simulator::st3(VectorFormat vform, LogicVRegister src, LogicVRegister src2, LogicVRegister src3, @@ -443,30 +466,32 @@ void Simulator::st3(VectorFormat vform, uint64_t addr2 = addr + esize; uint64_t addr3 = addr2 + esize; for (int i = 0; i < LaneCountFromFormat(vform); i++) { - StoreLane(src, vform, i, addr); - StoreLane(src2, vform, i, addr2); - StoreLane(src3, vform, i, addr3); + if (!StoreLane(src, vform, i, addr) || !StoreLane(src2, vform, i, addr2) || + !StoreLane(src3, vform, i, addr3)) { + return false; + } addr += 3 * esize; addr2 += 3 * esize; addr3 += 3 * esize; } + return true; } -void Simulator::st3(VectorFormat vform, +bool Simulator::st3(VectorFormat vform, LogicVRegister src, LogicVRegister src2, LogicVRegister src3, int index, uint64_t addr) { int esize = LaneSizeInBytesFromFormat(vform); - StoreLane(src, vform, index, addr); - StoreLane(src2, vform, index, addr + 1 * esize); - StoreLane(src3, vform, index, addr + 2 * esize); + return (StoreLane(src, vform, index, addr) && + StoreLane(src2, vform, index, addr + 1 * esize) && + StoreLane(src3, vform, index, addr + 2 * esize)); } -void Simulator::st4(VectorFormat vform, +bool Simulator::st4(VectorFormat vform, LogicVRegister src, LogicVRegister src2, LogicVRegister src3, @@ -477,19 +502,21 @@ void Simulator::st4(VectorFormat vform, uint64_t addr3 = addr2 + esize; uint64_t addr4 = addr3 + esize; for (int i = 0; i < LaneCountFromFormat(vform); i++) { - StoreLane(src, vform, i, addr); - StoreLane(src2, vform, i, addr2); - StoreLane(src3, vform, i, addr3); - StoreLane(src4, vform, i, addr4); + if (!StoreLane(src, vform, i, addr) || !StoreLane(src2, vform, i, addr2) || + !StoreLane(src3, vform, i, addr3) || + !StoreLane(src4, vform, i, addr4)) { + return false; + } addr += 4 * esize; addr2 += 4 * esize; addr3 += 4 * esize; addr4 += 4 * esize; } + return true; } -void Simulator::st4(VectorFormat vform, +bool Simulator::st4(VectorFormat vform, LogicVRegister src, LogicVRegister src2, LogicVRegister src3, @@ -497,10 +524,10 @@ void Simulator::st4(VectorFormat vform, int index, uint64_t addr) { int esize = LaneSizeInBytesFromFormat(vform); - StoreLane(src, vform, index, addr); - StoreLane(src2, vform, index, addr + 1 * esize); - StoreLane(src3, vform, index, addr + 2 * esize); - StoreLane(src4, vform, index, addr + 3 * esize); + return (StoreLane(src, vform, index, addr) && + StoreLane(src2, vform, index, addr + 1 * esize) && + StoreLane(src3, vform, index, addr + 2 * esize) && + StoreLane(src4, vform, index, addr + 3 * esize)); } @@ -895,23 +922,12 @@ LogicVRegister Simulator::sqrdmlsh(VectorFormat vform, return sqrdmlsh(vform, dst, src1, dup_element(indexform, temp, src2, index)); } - uint64_t Simulator::PolynomialMult(uint64_t op1, uint64_t op2, int lane_size_in_bits) const { - VIXL_ASSERT(static_cast(lane_size_in_bits) <= kSRegSize); - VIXL_ASSERT(IsUintN(lane_size_in_bits, op1)); - VIXL_ASSERT(IsUintN(lane_size_in_bits, op2)); - uint64_t result = 0; - for (int i = 0; i < lane_size_in_bits; ++i) { - if ((op1 >> i) & 1) { - result = result ^ (op2 << i); - } - } - return result; + return PolynomialMult128(op1, op2, lane_size_in_bits).second; } - LogicVRegister Simulator::pmul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, @@ -933,14 +949,16 @@ LogicVRegister Simulator::pmull(VectorFormat vform, const LogicVRegister& src1, const LogicVRegister& src2) { dst.ClearForWrite(vform); - VectorFormat vform_src = VectorFormatHalfWidth(vform); - for (int i = 0; i < LaneCountFromFormat(vform); i++) { + + // Process the elements in reverse to avoid problems when the destination + // register is the same as a source. + for (int i = LaneCountFromFormat(vform) - 1; i >= 0; i--) { dst.SetUint(vform, i, - PolynomialMult(src1.Uint(vform_src, i), - src2.Uint(vform_src, i), - LaneSizeInBitsFromFormat(vform_src))); + PolynomialMult128(src1.Uint(vform_src, i), + src2.Uint(vform_src, i), + LaneSizeInBitsFromFormat(vform_src))); } return dst; @@ -951,16 +969,18 @@ LogicVRegister Simulator::pmull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) { - VectorFormat vform_src = VectorFormatHalfWidthDoubleLanes(vform); dst.ClearForWrite(vform); + VectorFormat vform_src = VectorFormatHalfWidthDoubleLanes(vform); + int lane_count = LaneCountFromFormat(vform); for (int i = 0; i < lane_count; i++) { dst.SetUint(vform, i, - PolynomialMult(src1.Uint(vform_src, lane_count + i), - src2.Uint(vform_src, lane_count + i), - LaneSizeInBitsFromFormat(vform_src))); + PolynomialMult128(src1.Uint(vform_src, lane_count + i), + src2.Uint(vform_src, lane_count + i), + LaneSizeInBitsFromFormat(vform_src))); } + return dst; } @@ -2257,7 +2277,10 @@ LogicVRegister Simulator::extractnarrow(VectorFormat dstform, } } - if (!upperhalf) { + if (upperhalf) { + // Clear any bits beyond a Q register. + dst.ClearForWrite(kFormat16B); + } else { dst.ClearForWrite(dstform); } return dst; @@ -2491,6 +2514,7 @@ LogicVRegister Simulator::ror(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int rotation) { + dst.ClearForWrite(vform); int width = LaneSizeInBitsFromFormat(vform); for (int i = 0; i < LaneCountFromFormat(vform); i++) { uint64_t value = src.Uint(vform, i); @@ -2499,6 +2523,14 @@ LogicVRegister Simulator::ror(VectorFormat vform, return dst; } +LogicVRegister Simulator::rol(VectorFormat vform, + LogicVRegister dst, + const LogicVRegister& src, + int rotation) { + int ror_equivalent = LaneSizeInBitsFromFormat(vform) - rotation; + return ror(vform, dst, src, ror_equivalent); +} + LogicVRegister Simulator::ext(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, @@ -2507,10 +2539,10 @@ LogicVRegister Simulator::ext(VectorFormat vform, uint8_t result[kZRegMaxSizeInBytes] = {}; int lane_count = LaneCountFromFormat(vform); for (int i = 0; i < lane_count - index; ++i) { - result[i] = src1.Uint(vform, i + index); + result[i] = static_cast(src1.Uint(vform, i + index)); } for (int i = 0; i < index; ++i) { - result[lane_count - index + i] = src2.Uint(vform, i); + result[lane_count - index + i] = static_cast(src2.Uint(vform, i)); } dst.ClearForWrite(vform); for (int i = 0; i < lane_count; ++i) { @@ -2707,7 +2739,7 @@ LogicVRegister Simulator::fcmla(VectorFormat vform, int index, int rot) { if (LaneSizeInBitsFromFormat(vform) == kHRegSize) { - VIXL_UNIMPLEMENTED(); + fcmla(vform, dst, src1, src2, dst, index, rot); } else if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { fcmla(vform, dst, src1, src2, dst, index, rot); } else { @@ -4153,7 +4185,7 @@ LogicVRegister Simulator::sqrdmlash_d(VectorFormat vform, // Arithmetic shift the whole value right by `esize - 1` bits. accum.second = (accum.first << 1) | (accum.second >> (esize - 1)); - accum.first = -(accum.first >> (esize - 1)); + accum.first = UnsignedNegate(accum.first >> (esize - 1)); // Perform saturation. bool is_pos = (accum.first == 0) ? true : false; @@ -4531,7 +4563,7 @@ T Simulator::FPMulx(T op1, T op2) { if ((IsInf(op1) && (op2 == 0.0)) || (IsInf(op2) && (op1 == 0.0))) { // inf * 0.0 returns +/-2.0. T two = 2.0; - return copysign(1.0, op1) * copysign(1.0, op2) * two; + return copysign(T(1.0), op1) * copysign(T(1.0), op2) * two; } return FPMul(op1, op2); } @@ -4541,8 +4573,8 @@ template T Simulator::FPMulAdd(T a, T op1, T op2) { T result = FPProcessNaNs3(a, op1, op2); - T sign_a = copysign(1.0, a); - T sign_prod = copysign(1.0, op1) * copysign(1.0, op2); + T sign_a = copysign(T(1.0), a); + T sign_prod = copysign(T(1.0), op1) * copysign(T(1.0), op2); bool isinf_prod = IsInf(op1) || IsInf(op2); bool operation_generates_nan = (IsInf(op1) && (op2 == 0.0)) || // inf * 0.0 @@ -4568,7 +4600,7 @@ T Simulator::FPMulAdd(T a, T op1, T op2) { // Work around broken fma implementations for exact zero results: The sign of // exact 0.0 results is positive unless both a and op1 * op2 are negative. if (((op1 == 0.0) || (op2 == 0.0)) && (a == 0.0)) { - return ((sign_a < T(0.0)) && (sign_prod < T(0.0))) ? -0.0 : 0.0; + return ((sign_a < T(0.0)) && (sign_prod < T(0.0))) ? T(-0.0) : T(0.0); } result = FusedMultiplyAdd(op1, op2, a); @@ -4577,7 +4609,7 @@ T Simulator::FPMulAdd(T a, T op1, T op2) { // Work around broken fma implementations for rounded zero results: If a is // 0.0, the sign of the result is the sign of op1 * op2 before rounding. if ((a == 0.0) && (result == 0.0)) { - return copysign(0.0, sign_prod); + return copysign(T(0.0), sign_prod); } return result; @@ -4639,9 +4671,9 @@ T Simulator::FPMax(T a, T b) { template T Simulator::FPMaxNM(T a, T b) { if (IsQuietNaN(a) && !IsQuietNaN(b)) { - a = kFP64NegativeInfinity; + a = T(kFP64NegativeInfinity); } else if (!IsQuietNaN(a) && IsQuietNaN(b)) { - b = kFP64NegativeInfinity; + b = T(kFP64NegativeInfinity); } T result = FPProcessNaNs(a, b); @@ -4666,9 +4698,9 @@ T Simulator::FPMin(T a, T b) { template T Simulator::FPMinNM(T a, T b) { if (IsQuietNaN(a) && !IsQuietNaN(b)) { - a = kFP64PositiveInfinity; + a = T(kFP64PositiveInfinity); } else if (!IsQuietNaN(a) && IsQuietNaN(b)) { - b = kFP64PositiveInfinity; + b = T(kFP64PositiveInfinity); } T result = FPProcessNaNs(a, b); @@ -4683,8 +4715,8 @@ T Simulator::FPRecipStepFused(T op1, T op2) { return two; } else if (IsInf(op1) || IsInf(op2)) { // Return +inf if signs match, otherwise -inf. - return ((op1 >= 0.0) == (op2 >= 0.0)) ? kFP64PositiveInfinity - : kFP64NegativeInfinity; + return ((op1 >= 0.0) == (op2 >= 0.0)) ? T(kFP64PositiveInfinity) + : T(kFP64NegativeInfinity); } else { return FusedMultiplyAdd(op1, op2, two); } @@ -4713,8 +4745,8 @@ T Simulator::FPRSqrtStepFused(T op1, T op2) { return one_point_five; } else if (IsInf(op1) || IsInf(op2)) { // Return +inf if signs match, otherwise -inf. - return ((op1 >= 0.0) == (op2 >= 0.0)) ? kFP64PositiveInfinity - : kFP64NegativeInfinity; + return ((op1 >= 0.0) == (op2 >= 0.0)) ? T(kFP64PositiveInfinity) + : T(kFP64NegativeInfinity); } else { // The multiply-add-halve operation must be fully fused, so avoid interim // rounding by checking which operand can be losslessly divided by two @@ -4743,7 +4775,7 @@ int32_t Simulator::FPToFixedJS(double value) { (value == kFP64NegativeInfinity)) { // +/- zero and infinity all return zero, however -0 and +/- Infinity also // unset the Z-flag. - result = 0.0; + result = 0; if ((value != 0.0) || std::signbit(value)) { Z = 0; } @@ -5528,38 +5560,40 @@ LogicVRegister Simulator::fsqrt(VectorFormat vform, } -#define DEFINE_NEON_FP_PAIR_OP(FNP, FN, OP) \ - LogicVRegister Simulator::FNP(VectorFormat vform, \ - LogicVRegister dst, \ - const LogicVRegister& src1, \ - const LogicVRegister& src2) { \ - SimVRegister temp1, temp2; \ - uzp1(vform, temp1, src1, src2); \ - uzp2(vform, temp2, src1, src2); \ - FN(vform, dst, temp1, temp2); \ - if (IsSVEFormat(vform)) { \ - interleave_top_bottom(vform, dst, dst); \ - } \ - return dst; \ - } \ - \ - LogicVRegister Simulator::FNP(VectorFormat vform, \ - LogicVRegister dst, \ - const LogicVRegister& src) { \ - if (vform == kFormatH) { \ - SimFloat16 result(OP(SimFloat16(RawbitsToFloat16(src.Uint(vform, 0))), \ - SimFloat16(RawbitsToFloat16(src.Uint(vform, 1))))); \ - dst.SetUint(vform, 0, Float16ToRawbits(result)); \ - } else if (vform == kFormatS) { \ - float result = OP(src.Float(0), src.Float(1)); \ - dst.SetFloat(0, result); \ - } else { \ - VIXL_ASSERT(vform == kFormatD); \ - double result = OP(src.Float(0), src.Float(1)); \ - dst.SetFloat(0, result); \ - } \ - dst.ClearForWrite(vform); \ - return dst; \ +#define DEFINE_NEON_FP_PAIR_OP(FNP, FN, OP) \ + LogicVRegister Simulator::FNP(VectorFormat vform, \ + LogicVRegister dst, \ + const LogicVRegister& src1, \ + const LogicVRegister& src2) { \ + SimVRegister temp1, temp2; \ + uzp1(vform, temp1, src1, src2); \ + uzp2(vform, temp2, src1, src2); \ + FN(vform, dst, temp1, temp2); \ + if (IsSVEFormat(vform)) { \ + interleave_top_bottom(vform, dst, dst); \ + } \ + return dst; \ + } \ + \ + LogicVRegister Simulator::FNP(VectorFormat vform, \ + LogicVRegister dst, \ + const LogicVRegister& src) { \ + if (vform == kFormatH) { \ + SimFloat16 result(OP(SimFloat16(RawbitsToFloat16( \ + static_cast(src.Uint(vform, 0)))), \ + SimFloat16(RawbitsToFloat16( \ + static_cast(src.Uint(vform, 1)))))); \ + dst.SetUint(vform, 0, Float16ToRawbits(result)); \ + } else if (vform == kFormatS) { \ + float result = OP(src.Float(0), src.Float(1)); \ + dst.SetFloat(0, result); \ + } else { \ + VIXL_ASSERT(vform == kFormatD); \ + double result = OP(src.Float(0), src.Float(1)); \ + dst.SetFloat(0, result); \ + } \ + dst.ClearForWrite(vform); \ + return dst; \ } NEON_FPPAIRWISE_LIST(DEFINE_NEON_FP_PAIR_OP) #undef DEFINE_NEON_FP_PAIR_OP @@ -5801,7 +5835,8 @@ LogicVRegister Simulator::frint(VectorFormat vform, } else if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { for (int i = 0; i < LaneCountFromFormat(vform); i++) { float input = src.Float(i); - float rounded = FPRoundInt(input, rounding_mode, frint_mode); + float rounded = + static_cast(FPRoundInt(input, rounding_mode, frint_mode)); if (inexact_exception && !IsNaN(input) && (input != rounded)) { FPProcessException(); @@ -5963,6 +5998,7 @@ LogicVRegister Simulator::fcvtu(VectorFormat vform, LogicVRegister Simulator::fcvtl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) { + dst.ClearForWrite(vform); if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { for (int i = LaneCountFromFormat(vform) - 1; i >= 0; i--) { // TODO: Full support for SimFloat16 in SimRegister(s). @@ -5983,6 +6019,7 @@ LogicVRegister Simulator::fcvtl(VectorFormat vform, LogicVRegister Simulator::fcvtl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) { + dst.ClearForWrite(vform); int lane_count = LaneCountFromFormat(vform); if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { for (int i = 0; i < lane_count; i++) { @@ -6028,6 +6065,7 @@ LogicVRegister Simulator::fcvtn(VectorFormat vform, LogicVRegister Simulator::fcvtn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) { + dst.ClearForWrite(vform); int lane_count = LaneCountFromFormat(vform) / 2; if (LaneSizeInBitsFromFormat(vform) == kHRegSize) { for (int i = lane_count - 1; i >= 0; i--) { @@ -6071,6 +6109,7 @@ LogicVRegister Simulator::fcvtxn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) { VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kSRegSize); + dst.ClearForWrite(vform); int lane_count = LaneCountFromFormat(vform) / 2; for (int i = lane_count - 1; i >= 0; i--) { dst.SetFloat(i + lane_count, @@ -6107,9 +6146,9 @@ T Simulator::FPRecipSqrtEstimate(T op) { return FPProcessNaN(op); } else if (op == 0.0) { if (copysign(1.0, op) < 0.0) { - return kFP64NegativeInfinity; + return T(kFP64NegativeInfinity); } else { - return kFP64PositiveInfinity; + return T(kFP64PositiveInfinity); } } else if (copysign(1.0, op) < 0.0) { FPProcessException(); @@ -6120,11 +6159,11 @@ T Simulator::FPRecipSqrtEstimate(T op) { uint64_t fraction; int exp, result_exp; - if (IsFloat16()) { + if constexpr (IsFloat16()) { exp = Float16Exp(op); fraction = Float16Mantissa(op); fraction <<= 42; - } else if (IsFloat32()) { + } else if constexpr (IsFloat32()) { exp = FloatExp(op); fraction = FloatMantissa(op); fraction <<= 29; @@ -6149,9 +6188,9 @@ T Simulator::FPRecipSqrtEstimate(T op) { scaled = DoublePack(0, 1021, Bits(fraction, 51, 44) << 44); } - if (IsFloat16()) { + if constexpr (IsFloat16()) { result_exp = (44 - exp) / 2; - } else if (IsFloat32()) { + } else if constexpr (IsFloat32()) { result_exp = (380 - exp) / 2; } else { VIXL_ASSERT(IsFloat64()); @@ -6160,11 +6199,11 @@ T Simulator::FPRecipSqrtEstimate(T op) { uint64_t estimate = DoubleToRawbits(recip_sqrt_estimate(scaled)); - if (IsFloat16()) { + if constexpr (IsFloat16()) { uint16_t exp_bits = static_cast(Bits(result_exp, 4, 0)); uint16_t est_bits = static_cast(Bits(estimate, 51, 42)); return Float16Pack(0, exp_bits, est_bits); - } else if (IsFloat32()) { + } else if constexpr (IsFloat32()) { uint32_t exp_bits = static_cast(Bits(result_exp, 7, 0)); uint32_t est_bits = static_cast(Bits(estimate, 51, 29)); return FloatPack(0, exp_bits, est_bits); @@ -6204,9 +6243,9 @@ template T Simulator::FPRecipEstimate(T op, FPRounding rounding) { uint32_t sign; - if (IsFloat16()) { + if constexpr (IsFloat16()) { sign = Float16Sign(op); - } else if (IsFloat32()) { + } else if constexpr (IsFloat32()) { sign = FloatSign(op); } else { VIXL_ASSERT(IsFloat64()); @@ -6216,10 +6255,10 @@ T Simulator::FPRecipEstimate(T op, FPRounding rounding) { if (IsNaN(op)) { return FPProcessNaN(op); } else if (IsInf(op)) { - return (sign == 1) ? -0.0 : 0.0; + return (sign == 1) ? T(-0.0) : T(0.0); } else if (op == 0.0) { FPProcessException(); // FPExc_DivideByZero exception. - return (sign == 1) ? kFP64NegativeInfinity : kFP64PositiveInfinity; + return (sign == 1) ? T(kFP64NegativeInfinity) : T(kFP64PositiveInfinity); } else if ((IsFloat16() && (std::fabs(op) < std::pow(2.0, -16.0))) || (IsFloat32() && (std::fabs(op) < std::pow(2.0, -128.0))) || (IsFloat64() && (std::fabs(op) < std::pow(2.0, -1024.0)))) { @@ -6242,12 +6281,12 @@ T Simulator::FPRecipEstimate(T op, FPRounding rounding) { } FPProcessException(); // FPExc_Overflow and FPExc_Inexact. if (overflow_to_inf) { - return (sign == 1) ? kFP64NegativeInfinity : kFP64PositiveInfinity; + return (sign == 1) ? T(kFP64NegativeInfinity) : T(kFP64PositiveInfinity); } else { // Return FPMaxNormal(sign). - if (IsFloat16()) { + if constexpr (IsFloat16()) { return Float16Pack(sign, 0x1f, 0x3ff); - } else if (IsFloat32()) { + } else if constexpr (IsFloat32()) { return FloatPack(sign, 0xfe, 0x07fffff); } else { VIXL_ASSERT(IsFloat64()); @@ -6258,12 +6297,12 @@ T Simulator::FPRecipEstimate(T op, FPRounding rounding) { uint64_t fraction; int exp, result_exp; - if (IsFloat16()) { + if constexpr (IsFloat16()) { sign = Float16Sign(op); exp = Float16Exp(op); fraction = Float16Mantissa(op); fraction <<= 42; - } else if (IsFloat32()) { + } else if constexpr (IsFloat32()) { sign = FloatSign(op); exp = FloatExp(op); fraction = FloatMantissa(op); @@ -6286,9 +6325,9 @@ T Simulator::FPRecipEstimate(T op, FPRounding rounding) { double scaled = DoublePack(0, 1022, Bits(fraction, 51, 44) << 44); - if (IsFloat16()) { + if constexpr (IsFloat16()) { result_exp = (29 - exp); // In range 29-30 = -1 to 29+1 = 30. - } else if (IsFloat32()) { + } else if constexpr (IsFloat32()) { result_exp = (253 - exp); // In range 253-254 = -1 to 253+1 = 254. } else { VIXL_ASSERT(IsFloat64()); @@ -6304,11 +6343,11 @@ T Simulator::FPRecipEstimate(T op, FPRounding rounding) { fraction = (UINT64_C(1) << 50) | Bits(fraction, 51, 2); result_exp = 0; } - if (IsFloat16()) { + if constexpr (IsFloat16()) { uint16_t exp_bits = static_cast(Bits(result_exp, 4, 0)); uint16_t frac_bits = static_cast(Bits(fraction, 51, 42)); return Float16Pack(sign, exp_bits, frac_bits); - } else if (IsFloat32()) { + } else if constexpr (IsFloat32()) { uint32_t exp_bits = static_cast(Bits(result_exp, 7, 0)); uint32_t frac_bits = static_cast(Bits(fraction, 51, 29)); return FloatPack(sign, exp_bits, frac_bits); @@ -6454,12 +6493,12 @@ LogicVRegister Simulator::frecpx(VectorFormat vform, } else { int exp; uint32_t sign; - if (IsFloat16()) { + if constexpr (IsFloat16()) { sign = Float16Sign(op); exp = Float16Exp(op); exp = (exp == 0) ? (0x1F - 1) : static_cast(Bits(~exp, 4, 0)); result = Float16Pack(sign, exp, 0); - } else if (IsFloat32()) { + } else if constexpr (IsFloat32()) { sign = FloatSign(op); exp = FloatExp(op); exp = (exp == 0) ? (0xFF - 1) : static_cast(Bits(~exp, 7, 0)); @@ -6763,18 +6802,21 @@ LogicVRegister Simulator::fexpa(VectorFormat vform, if (lane_size == kHRegSize) { index_highbit = 4; - VIXL_ASSERT(ArrayLength(fexpa_coeff16) == (1U << (index_highbit + 1))); + VIXL_ASSERT(ArrayLength(fexpa_coeff16) == + (uint64_t{1} << (index_highbit + 1))); fexpa_coeff = fexpa_coeff16; op_highbit = 9; op_shift = 10; } else if (lane_size == kSRegSize) { - VIXL_ASSERT(ArrayLength(fexpa_coeff32) == (1U << (index_highbit + 1))); + VIXL_ASSERT(ArrayLength(fexpa_coeff32) == + (uint64_t{1} << (index_highbit + 1))); fexpa_coeff = fexpa_coeff32; op_highbit = 13; op_shift = 23; } else { VIXL_ASSERT(lane_size == kDRegSize); - VIXL_ASSERT(ArrayLength(fexpa_coeff64) == (1U << (index_highbit + 1))); + VIXL_ASSERT(ArrayLength(fexpa_coeff64) == + (uint64_t{1} << (index_highbit + 1))); fexpa_coeff = fexpa_coeff64; op_highbit = 16; op_shift = 52; @@ -7271,7 +7313,9 @@ void Simulator::SVEStructuredStoreHelper(VectorFormat vform, for (int r = 0; r < reg_count; r++) { uint64_t element_address = addr.GetElementAddress(i, r); - StoreLane(zt[r], unpack_vform, i << unpack_shift, element_address); + if (!StoreLane(zt[r], unpack_vform, i << unpack_shift, element_address)) { + return; + } } } @@ -7295,7 +7339,7 @@ void Simulator::SVEStructuredStoreHelper(VectorFormat vform, } } -void Simulator::SVEStructuredLoadHelper(VectorFormat vform, +bool Simulator::SVEStructuredLoadHelper(VectorFormat vform, const LogicPRegister& pg, unsigned zt_code, const LogicSVEAddressVector& addr, @@ -7330,9 +7374,13 @@ void Simulator::SVEStructuredLoadHelper(VectorFormat vform, } if (is_signed) { - LoadIntToLane(zt[r], vform, msize_in_bytes, i, element_address); + if (!LoadIntToLane(zt[r], vform, msize_in_bytes, i, element_address)) { + return false; + } } else { - LoadUintToLane(zt[r], vform, msize_in_bytes, i, element_address); + if (!LoadUintToLane(zt[r], vform, msize_in_bytes, i, element_address)) { + return false; + } } } } @@ -7351,6 +7399,7 @@ void Simulator::SVEStructuredLoadHelper(VectorFormat vform, "<-", addr); } + return true; } LogicPRegister Simulator::brka(LogicPRegister pd, @@ -7445,7 +7494,7 @@ void Simulator::SVEFaultTolerantLoadHelper(VectorFormat vform, // Non-faulting loads are allowed to fail arbitrarily. To stress user // code, fail a random element in roughly one in eight full-vector loads. - uint32_t rnd = static_cast(jrand48(rand_state_)); + uint32_t rnd = static_cast(rand_gen_()); int fake_fault_at_lane = rnd % (LaneCountFromFormat(vform) * 8); for (int i = 0; i < LaneCountFromFormat(vform); i++) { @@ -7458,7 +7507,9 @@ void Simulator::SVEFaultTolerantLoadHelper(VectorFormat vform, // First-faulting loads always load the first active element, regardless // of FFR. The result will be discarded if its FFR lane is inactive, but // it could still generate a fault. - value = MemReadUint(msize_in_bytes, element_address); + VIXL_DEFINE_OR_RETURN(mem_result, + MemReadUint(msize_in_bytes, element_address)); + value = mem_result; // All subsequent elements have non-fault semantics. type = kSVENonFaultLoad; @@ -7470,7 +7521,9 @@ void Simulator::SVEFaultTolerantLoadHelper(VectorFormat vform, bool can_read = (i < fake_fault_at_lane) && CanReadMemory(element_address, msize_in_bytes); if (can_read) { - value = MemReadUint(msize_in_bytes, element_address); + VIXL_DEFINE_OR_RETURN(mem_result, + MemReadUint(msize_in_bytes, element_address)); + value = mem_result; } else { // Propagate the fault to the end of FFR. for (int j = i; j < LaneCountFromFormat(vform); j++) { @@ -7848,6 +7901,582 @@ LogicVRegister Simulator::fmatmul(VectorFormat vform, return dst; } +template <> +uint64_t CryptoOp<"choose"_h>(uint64_t x, uint64_t y, uint64_t z) { + return ((y ^ z) & x) ^ z; +} + +template <> +uint64_t CryptoOp<"majority"_h>(uint64_t x, uint64_t y, uint64_t z) { + return (x & y) | ((x | y) & z); +} + +template <> +uint64_t CryptoOp<"parity"_h>(uint64_t x, uint64_t y, uint64_t z) { + return x ^ y ^ z; +} + +template +static uint64_t SHASigma(uint64_t x) { + return static_cast(RotateRight(x, A, sizeof(T) * kBitsPerByte) ^ + RotateRight(x, B, sizeof(T) * kBitsPerByte) ^ + RotateRight(x, C, sizeof(T) * kBitsPerByte)); +} + +LogicVRegister Simulator::sha2h(LogicVRegister srcdst, + const LogicVRegister& src1, + const LogicVRegister& src2, + bool part1) { + uint64_t x[4] = {}; + uint64_t y[4] = {}; + if (part1) { + // Switch input order based on which part is being handled. + srcdst.UintArray(kFormat4S, x); + src1.UintArray(kFormat4S, y); + } else { + src1.UintArray(kFormat4S, x); + srcdst.UintArray(kFormat4S, y); + } + + for (unsigned i = 0; i < ArrayLength(x); i++) { + uint64_t chs = CryptoOp<"choose"_h>(y[0], y[1], y[2]); + uint64_t maj = CryptoOp<"majority"_h>(x[0], x[1], x[2]); + + uint64_t w = src2.Uint(kFormat4S, i); + uint64_t t = y[3] + SHASigma(y[0]) + chs + w; + + x[3] += t; + y[3] = t + SHASigma(x[0]) + maj; + + // y:x = ROL(y:x, 32) + SHARotateEltsLeftOne(x); + SHARotateEltsLeftOne(y); + std::swap(x[0], y[0]); + } + + srcdst.SetUintArray(kFormat4S, part1 ? x : y); + return srcdst; +} + +template +static uint64_t SHASURotate(uint64_t x) { + return RotateRight(x, A, sizeof(T) * kBitsPerByte) ^ + RotateRight(x, B, sizeof(T) * kBitsPerByte) ^ + ((x & ~static_cast(0)) >> C); +} + +LogicVRegister Simulator::sha2su0(LogicVRegister srcdst, + const LogicVRegister& src1) { + uint64_t w[4] = {}; + uint64_t result[4]; + srcdst.UintArray(kFormat4S, w); + uint64_t x = src1.Uint(kFormat4S, 0); + + result[0] = SHASURotate(w[1]) + w[0]; + result[1] = SHASURotate(w[2]) + w[1]; + result[2] = SHASURotate(w[3]) + w[2]; + result[3] = SHASURotate(x) + w[3]; + + srcdst.SetUintArray(kFormat4S, result); + return srcdst; +} + +LogicVRegister Simulator::sha2su1(LogicVRegister srcdst, + const LogicVRegister& src1, + const LogicVRegister& src2) { + uint64_t w[4] = {}; + uint64_t x[4] = {}; + uint64_t y[4] = {}; + uint64_t result[4]; + srcdst.UintArray(kFormat4S, w); + src1.UintArray(kFormat4S, x); + src2.UintArray(kFormat4S, y); + + result[0] = SHASURotate(y[2]) + w[0] + x[1]; + result[1] = SHASURotate(y[3]) + w[1] + x[2]; + result[2] = SHASURotate(result[0]) + w[2] + x[3]; + result[3] = SHASURotate(result[1]) + w[3] + y[0]; + + srcdst.SetUintArray(kFormat4S, result); + return srcdst; +} + +LogicVRegister Simulator::sha512h(LogicVRegister srcdst, + const LogicVRegister& src1, + const LogicVRegister& src2) { + uint64_t w[2] = {}; + uint64_t x[2] = {}; + uint64_t y[2] = {}; + uint64_t result[2] = {}; + srcdst.UintArray(kFormat2D, w); + src1.UintArray(kFormat2D, x); + src2.UintArray(kFormat2D, y); + + result[1] = (y[1] & x[0]) ^ (~y[1] & x[1]); + result[1] += SHASigma(y[1]) + w[1]; + + uint64_t tmp = result[1] + y[0]; + + result[0] = (tmp & y[1]) ^ (~tmp & x[0]); + result[0] += SHASigma(tmp) + w[0]; + + srcdst.SetUintArray(kFormat2D, result); + return srcdst; +} + +LogicVRegister Simulator::sha512h2(LogicVRegister srcdst, + const LogicVRegister& src1, + const LogicVRegister& src2) { + uint64_t w[2] = {}; + uint64_t x[2] = {}; + uint64_t y[2] = {}; + uint64_t result[2] = {}; + srcdst.UintArray(kFormat2D, w); + src1.UintArray(kFormat2D, x); + src2.UintArray(kFormat2D, y); + + result[1] = (x[0] & y[1]) ^ (x[0] & y[0]) ^ (y[1] & y[0]); + result[1] += SHASigma(y[0]) + w[1]; + + result[0] = (result[1] & y[0]) ^ (result[1] & y[1]) ^ (y[1] & y[0]); + result[0] += SHASigma(result[1]) + w[0]; + + srcdst.SetUintArray(kFormat2D, result); + return srcdst; +} + +LogicVRegister Simulator::sha512su0(LogicVRegister srcdst, + const LogicVRegister& src1) { + uint64_t w[2] = {}; + uint64_t x[2] = {}; + uint64_t result[2] = {}; + srcdst.UintArray(kFormat2D, w); + src1.UintArray(kFormat2D, x); + + result[0] = SHASURotate(w[1]) + w[0]; + result[1] = SHASURotate(x[0]) + w[1]; + + srcdst.SetUintArray(kFormat2D, result); + return srcdst; +} + +LogicVRegister Simulator::sha512su1(LogicVRegister srcdst, + const LogicVRegister& src1, + const LogicVRegister& src2) { + uint64_t w[2] = {}; + uint64_t x[2] = {}; + uint64_t y[2] = {}; + uint64_t result[2] = {}; + srcdst.UintArray(kFormat2D, w); + src1.UintArray(kFormat2D, x); + src2.UintArray(kFormat2D, y); + + result[1] = w[1] + SHASURotate(x[1]) + y[1]; + result[0] = w[0] + SHASURotate(x[0]) + y[0]; + + srcdst.SetUintArray(kFormat2D, result); + return srcdst; +} + +static uint8_t GalMul(int table, uint64_t x) { + // Galois multiplication lookup tables. + static const uint8_t ffmul02[256] = { + 0x00, 0x02, 0x04, 0x06, 0x08, 0x0a, 0x0c, 0x0e, 0x10, 0x12, 0x14, 0x16, + 0x18, 0x1a, 0x1c, 0x1e, 0x20, 0x22, 0x24, 0x26, 0x28, 0x2a, 0x2c, 0x2e, + 0x30, 0x32, 0x34, 0x36, 0x38, 0x3a, 0x3c, 0x3e, 0x40, 0x42, 0x44, 0x46, + 0x48, 0x4a, 0x4c, 0x4e, 0x50, 0x52, 0x54, 0x56, 0x58, 0x5a, 0x5c, 0x5e, + 0x60, 0x62, 0x64, 0x66, 0x68, 0x6a, 0x6c, 0x6e, 0x70, 0x72, 0x74, 0x76, + 0x78, 0x7a, 0x7c, 0x7e, 0x80, 0x82, 0x84, 0x86, 0x88, 0x8a, 0x8c, 0x8e, + 0x90, 0x92, 0x94, 0x96, 0x98, 0x9a, 0x9c, 0x9e, 0xa0, 0xa2, 0xa4, 0xa6, + 0xa8, 0xaa, 0xac, 0xae, 0xb0, 0xb2, 0xb4, 0xb6, 0xb8, 0xba, 0xbc, 0xbe, + 0xc0, 0xc2, 0xc4, 0xc6, 0xc8, 0xca, 0xcc, 0xce, 0xd0, 0xd2, 0xd4, 0xd6, + 0xd8, 0xda, 0xdc, 0xde, 0xe0, 0xe2, 0xe4, 0xe6, 0xe8, 0xea, 0xec, 0xee, + 0xf0, 0xf2, 0xf4, 0xf6, 0xf8, 0xfa, 0xfc, 0xfe, 0x1b, 0x19, 0x1f, 0x1d, + 0x13, 0x11, 0x17, 0x15, 0x0b, 0x09, 0x0f, 0x0d, 0x03, 0x01, 0x07, 0x05, + 0x3b, 0x39, 0x3f, 0x3d, 0x33, 0x31, 0x37, 0x35, 0x2b, 0x29, 0x2f, 0x2d, + 0x23, 0x21, 0x27, 0x25, 0x5b, 0x59, 0x5f, 0x5d, 0x53, 0x51, 0x57, 0x55, + 0x4b, 0x49, 0x4f, 0x4d, 0x43, 0x41, 0x47, 0x45, 0x7b, 0x79, 0x7f, 0x7d, + 0x73, 0x71, 0x77, 0x75, 0x6b, 0x69, 0x6f, 0x6d, 0x63, 0x61, 0x67, 0x65, + 0x9b, 0x99, 0x9f, 0x9d, 0x93, 0x91, 0x97, 0x95, 0x8b, 0x89, 0x8f, 0x8d, + 0x83, 0x81, 0x87, 0x85, 0xbb, 0xb9, 0xbf, 0xbd, 0xb3, 0xb1, 0xb7, 0xb5, + 0xab, 0xa9, 0xaf, 0xad, 0xa3, 0xa1, 0xa7, 0xa5, 0xdb, 0xd9, 0xdf, 0xdd, + 0xd3, 0xd1, 0xd7, 0xd5, 0xcb, 0xc9, 0xcf, 0xcd, 0xc3, 0xc1, 0xc7, 0xc5, + 0xfb, 0xf9, 0xff, 0xfd, 0xf3, 0xf1, 0xf7, 0xf5, 0xeb, 0xe9, 0xef, 0xed, + 0xe3, 0xe1, 0xe7, 0xe5, + }; + + static const uint8_t ffmul03[256] = { + 0x00, 0x03, 0x06, 0x05, 0x0c, 0x0f, 0x0a, 0x09, 0x18, 0x1b, 0x1e, 0x1d, + 0x14, 0x17, 0x12, 0x11, 0x30, 0x33, 0x36, 0x35, 0x3c, 0x3f, 0x3a, 0x39, + 0x28, 0x2b, 0x2e, 0x2d, 0x24, 0x27, 0x22, 0x21, 0x60, 0x63, 0x66, 0x65, + 0x6c, 0x6f, 0x6a, 0x69, 0x78, 0x7b, 0x7e, 0x7d, 0x74, 0x77, 0x72, 0x71, + 0x50, 0x53, 0x56, 0x55, 0x5c, 0x5f, 0x5a, 0x59, 0x48, 0x4b, 0x4e, 0x4d, + 0x44, 0x47, 0x42, 0x41, 0xc0, 0xc3, 0xc6, 0xc5, 0xcc, 0xcf, 0xca, 0xc9, + 0xd8, 0xdb, 0xde, 0xdd, 0xd4, 0xd7, 0xd2, 0xd1, 0xf0, 0xf3, 0xf6, 0xf5, + 0xfc, 0xff, 0xfa, 0xf9, 0xe8, 0xeb, 0xee, 0xed, 0xe4, 0xe7, 0xe2, 0xe1, + 0xa0, 0xa3, 0xa6, 0xa5, 0xac, 0xaf, 0xaa, 0xa9, 0xb8, 0xbb, 0xbe, 0xbd, + 0xb4, 0xb7, 0xb2, 0xb1, 0x90, 0x93, 0x96, 0x95, 0x9c, 0x9f, 0x9a, 0x99, + 0x88, 0x8b, 0x8e, 0x8d, 0x84, 0x87, 0x82, 0x81, 0x9b, 0x98, 0x9d, 0x9e, + 0x97, 0x94, 0x91, 0x92, 0x83, 0x80, 0x85, 0x86, 0x8f, 0x8c, 0x89, 0x8a, + 0xab, 0xa8, 0xad, 0xae, 0xa7, 0xa4, 0xa1, 0xa2, 0xb3, 0xb0, 0xb5, 0xb6, + 0xbf, 0xbc, 0xb9, 0xba, 0xfb, 0xf8, 0xfd, 0xfe, 0xf7, 0xf4, 0xf1, 0xf2, + 0xe3, 0xe0, 0xe5, 0xe6, 0xef, 0xec, 0xe9, 0xea, 0xcb, 0xc8, 0xcd, 0xce, + 0xc7, 0xc4, 0xc1, 0xc2, 0xd3, 0xd0, 0xd5, 0xd6, 0xdf, 0xdc, 0xd9, 0xda, + 0x5b, 0x58, 0x5d, 0x5e, 0x57, 0x54, 0x51, 0x52, 0x43, 0x40, 0x45, 0x46, + 0x4f, 0x4c, 0x49, 0x4a, 0x6b, 0x68, 0x6d, 0x6e, 0x67, 0x64, 0x61, 0x62, + 0x73, 0x70, 0x75, 0x76, 0x7f, 0x7c, 0x79, 0x7a, 0x3b, 0x38, 0x3d, 0x3e, + 0x37, 0x34, 0x31, 0x32, 0x23, 0x20, 0x25, 0x26, 0x2f, 0x2c, 0x29, 0x2a, + 0x0b, 0x08, 0x0d, 0x0e, 0x07, 0x04, 0x01, 0x02, 0x13, 0x10, 0x15, 0x16, + 0x1f, 0x1c, 0x19, 0x1a, + }; + + static const uint8_t ffmul09[256] = { + 0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f, 0x48, 0x41, 0x5a, 0x53, + 0x6c, 0x65, 0x7e, 0x77, 0x90, 0x99, 0x82, 0x8b, 0xb4, 0xbd, 0xa6, 0xaf, + 0xd8, 0xd1, 0xca, 0xc3, 0xfc, 0xf5, 0xee, 0xe7, 0x3b, 0x32, 0x29, 0x20, + 0x1f, 0x16, 0x0d, 0x04, 0x73, 0x7a, 0x61, 0x68, 0x57, 0x5e, 0x45, 0x4c, + 0xab, 0xa2, 0xb9, 0xb0, 0x8f, 0x86, 0x9d, 0x94, 0xe3, 0xea, 0xf1, 0xf8, + 0xc7, 0xce, 0xd5, 0xdc, 0x76, 0x7f, 0x64, 0x6d, 0x52, 0x5b, 0x40, 0x49, + 0x3e, 0x37, 0x2c, 0x25, 0x1a, 0x13, 0x08, 0x01, 0xe6, 0xef, 0xf4, 0xfd, + 0xc2, 0xcb, 0xd0, 0xd9, 0xae, 0xa7, 0xbc, 0xb5, 0x8a, 0x83, 0x98, 0x91, + 0x4d, 0x44, 0x5f, 0x56, 0x69, 0x60, 0x7b, 0x72, 0x05, 0x0c, 0x17, 0x1e, + 0x21, 0x28, 0x33, 0x3a, 0xdd, 0xd4, 0xcf, 0xc6, 0xf9, 0xf0, 0xeb, 0xe2, + 0x95, 0x9c, 0x87, 0x8e, 0xb1, 0xb8, 0xa3, 0xaa, 0xec, 0xe5, 0xfe, 0xf7, + 0xc8, 0xc1, 0xda, 0xd3, 0xa4, 0xad, 0xb6, 0xbf, 0x80, 0x89, 0x92, 0x9b, + 0x7c, 0x75, 0x6e, 0x67, 0x58, 0x51, 0x4a, 0x43, 0x34, 0x3d, 0x26, 0x2f, + 0x10, 0x19, 0x02, 0x0b, 0xd7, 0xde, 0xc5, 0xcc, 0xf3, 0xfa, 0xe1, 0xe8, + 0x9f, 0x96, 0x8d, 0x84, 0xbb, 0xb2, 0xa9, 0xa0, 0x47, 0x4e, 0x55, 0x5c, + 0x63, 0x6a, 0x71, 0x78, 0x0f, 0x06, 0x1d, 0x14, 0x2b, 0x22, 0x39, 0x30, + 0x9a, 0x93, 0x88, 0x81, 0xbe, 0xb7, 0xac, 0xa5, 0xd2, 0xdb, 0xc0, 0xc9, + 0xf6, 0xff, 0xe4, 0xed, 0x0a, 0x03, 0x18, 0x11, 0x2e, 0x27, 0x3c, 0x35, + 0x42, 0x4b, 0x50, 0x59, 0x66, 0x6f, 0x74, 0x7d, 0xa1, 0xa8, 0xb3, 0xba, + 0x85, 0x8c, 0x97, 0x9e, 0xe9, 0xe0, 0xfb, 0xf2, 0xcd, 0xc4, 0xdf, 0xd6, + 0x31, 0x38, 0x23, 0x2a, 0x15, 0x1c, 0x07, 0x0e, 0x79, 0x70, 0x6b, 0x62, + 0x5d, 0x54, 0x4f, 0x46, + }; + + static const uint8_t ffmul0b[256] = { + 0x00, 0x0b, 0x16, 0x1d, 0x2c, 0x27, 0x3a, 0x31, 0x58, 0x53, 0x4e, 0x45, + 0x74, 0x7f, 0x62, 0x69, 0xb0, 0xbb, 0xa6, 0xad, 0x9c, 0x97, 0x8a, 0x81, + 0xe8, 0xe3, 0xfe, 0xf5, 0xc4, 0xcf, 0xd2, 0xd9, 0x7b, 0x70, 0x6d, 0x66, + 0x57, 0x5c, 0x41, 0x4a, 0x23, 0x28, 0x35, 0x3e, 0x0f, 0x04, 0x19, 0x12, + 0xcb, 0xc0, 0xdd, 0xd6, 0xe7, 0xec, 0xf1, 0xfa, 0x93, 0x98, 0x85, 0x8e, + 0xbf, 0xb4, 0xa9, 0xa2, 0xf6, 0xfd, 0xe0, 0xeb, 0xda, 0xd1, 0xcc, 0xc7, + 0xae, 0xa5, 0xb8, 0xb3, 0x82, 0x89, 0x94, 0x9f, 0x46, 0x4d, 0x50, 0x5b, + 0x6a, 0x61, 0x7c, 0x77, 0x1e, 0x15, 0x08, 0x03, 0x32, 0x39, 0x24, 0x2f, + 0x8d, 0x86, 0x9b, 0x90, 0xa1, 0xaa, 0xb7, 0xbc, 0xd5, 0xde, 0xc3, 0xc8, + 0xf9, 0xf2, 0xef, 0xe4, 0x3d, 0x36, 0x2b, 0x20, 0x11, 0x1a, 0x07, 0x0c, + 0x65, 0x6e, 0x73, 0x78, 0x49, 0x42, 0x5f, 0x54, 0xf7, 0xfc, 0xe1, 0xea, + 0xdb, 0xd0, 0xcd, 0xc6, 0xaf, 0xa4, 0xb9, 0xb2, 0x83, 0x88, 0x95, 0x9e, + 0x47, 0x4c, 0x51, 0x5a, 0x6b, 0x60, 0x7d, 0x76, 0x1f, 0x14, 0x09, 0x02, + 0x33, 0x38, 0x25, 0x2e, 0x8c, 0x87, 0x9a, 0x91, 0xa0, 0xab, 0xb6, 0xbd, + 0xd4, 0xdf, 0xc2, 0xc9, 0xf8, 0xf3, 0xee, 0xe5, 0x3c, 0x37, 0x2a, 0x21, + 0x10, 0x1b, 0x06, 0x0d, 0x64, 0x6f, 0x72, 0x79, 0x48, 0x43, 0x5e, 0x55, + 0x01, 0x0a, 0x17, 0x1c, 0x2d, 0x26, 0x3b, 0x30, 0x59, 0x52, 0x4f, 0x44, + 0x75, 0x7e, 0x63, 0x68, 0xb1, 0xba, 0xa7, 0xac, 0x9d, 0x96, 0x8b, 0x80, + 0xe9, 0xe2, 0xff, 0xf4, 0xc5, 0xce, 0xd3, 0xd8, 0x7a, 0x71, 0x6c, 0x67, + 0x56, 0x5d, 0x40, 0x4b, 0x22, 0x29, 0x34, 0x3f, 0x0e, 0x05, 0x18, 0x13, + 0xca, 0xc1, 0xdc, 0xd7, 0xe6, 0xed, 0xf0, 0xfb, 0x92, 0x99, 0x84, 0x8f, + 0xbe, 0xb5, 0xa8, 0xa3, + }; + + static const uint8_t ffmul0d[256] = { + 0x00, 0x0d, 0x1a, 0x17, 0x34, 0x39, 0x2e, 0x23, 0x68, 0x65, 0x72, 0x7f, + 0x5c, 0x51, 0x46, 0x4b, 0xd0, 0xdd, 0xca, 0xc7, 0xe4, 0xe9, 0xfe, 0xf3, + 0xb8, 0xb5, 0xa2, 0xaf, 0x8c, 0x81, 0x96, 0x9b, 0xbb, 0xb6, 0xa1, 0xac, + 0x8f, 0x82, 0x95, 0x98, 0xd3, 0xde, 0xc9, 0xc4, 0xe7, 0xea, 0xfd, 0xf0, + 0x6b, 0x66, 0x71, 0x7c, 0x5f, 0x52, 0x45, 0x48, 0x03, 0x0e, 0x19, 0x14, + 0x37, 0x3a, 0x2d, 0x20, 0x6d, 0x60, 0x77, 0x7a, 0x59, 0x54, 0x43, 0x4e, + 0x05, 0x08, 0x1f, 0x12, 0x31, 0x3c, 0x2b, 0x26, 0xbd, 0xb0, 0xa7, 0xaa, + 0x89, 0x84, 0x93, 0x9e, 0xd5, 0xd8, 0xcf, 0xc2, 0xe1, 0xec, 0xfb, 0xf6, + 0xd6, 0xdb, 0xcc, 0xc1, 0xe2, 0xef, 0xf8, 0xf5, 0xbe, 0xb3, 0xa4, 0xa9, + 0x8a, 0x87, 0x90, 0x9d, 0x06, 0x0b, 0x1c, 0x11, 0x32, 0x3f, 0x28, 0x25, + 0x6e, 0x63, 0x74, 0x79, 0x5a, 0x57, 0x40, 0x4d, 0xda, 0xd7, 0xc0, 0xcd, + 0xee, 0xe3, 0xf4, 0xf9, 0xb2, 0xbf, 0xa8, 0xa5, 0x86, 0x8b, 0x9c, 0x91, + 0x0a, 0x07, 0x10, 0x1d, 0x3e, 0x33, 0x24, 0x29, 0x62, 0x6f, 0x78, 0x75, + 0x56, 0x5b, 0x4c, 0x41, 0x61, 0x6c, 0x7b, 0x76, 0x55, 0x58, 0x4f, 0x42, + 0x09, 0x04, 0x13, 0x1e, 0x3d, 0x30, 0x27, 0x2a, 0xb1, 0xbc, 0xab, 0xa6, + 0x85, 0x88, 0x9f, 0x92, 0xd9, 0xd4, 0xc3, 0xce, 0xed, 0xe0, 0xf7, 0xfa, + 0xb7, 0xba, 0xad, 0xa0, 0x83, 0x8e, 0x99, 0x94, 0xdf, 0xd2, 0xc5, 0xc8, + 0xeb, 0xe6, 0xf1, 0xfc, 0x67, 0x6a, 0x7d, 0x70, 0x53, 0x5e, 0x49, 0x44, + 0x0f, 0x02, 0x15, 0x18, 0x3b, 0x36, 0x21, 0x2c, 0x0c, 0x01, 0x16, 0x1b, + 0x38, 0x35, 0x22, 0x2f, 0x64, 0x69, 0x7e, 0x73, 0x50, 0x5d, 0x4a, 0x47, + 0xdc, 0xd1, 0xc6, 0xcb, 0xe8, 0xe5, 0xf2, 0xff, 0xb4, 0xb9, 0xae, 0xa3, + 0x80, 0x8d, 0x9a, 0x97, + }; + + static const uint8_t ffmul0e[256] = { + 0x00, 0x0e, 0x1c, 0x12, 0x38, 0x36, 0x24, 0x2a, 0x70, 0x7e, 0x6c, 0x62, + 0x48, 0x46, 0x54, 0x5a, 0xe0, 0xee, 0xfc, 0xf2, 0xd8, 0xd6, 0xc4, 0xca, + 0x90, 0x9e, 0x8c, 0x82, 0xa8, 0xa6, 0xb4, 0xba, 0xdb, 0xd5, 0xc7, 0xc9, + 0xe3, 0xed, 0xff, 0xf1, 0xab, 0xa5, 0xb7, 0xb9, 0x93, 0x9d, 0x8f, 0x81, + 0x3b, 0x35, 0x27, 0x29, 0x03, 0x0d, 0x1f, 0x11, 0x4b, 0x45, 0x57, 0x59, + 0x73, 0x7d, 0x6f, 0x61, 0xad, 0xa3, 0xb1, 0xbf, 0x95, 0x9b, 0x89, 0x87, + 0xdd, 0xd3, 0xc1, 0xcf, 0xe5, 0xeb, 0xf9, 0xf7, 0x4d, 0x43, 0x51, 0x5f, + 0x75, 0x7b, 0x69, 0x67, 0x3d, 0x33, 0x21, 0x2f, 0x05, 0x0b, 0x19, 0x17, + 0x76, 0x78, 0x6a, 0x64, 0x4e, 0x40, 0x52, 0x5c, 0x06, 0x08, 0x1a, 0x14, + 0x3e, 0x30, 0x22, 0x2c, 0x96, 0x98, 0x8a, 0x84, 0xae, 0xa0, 0xb2, 0xbc, + 0xe6, 0xe8, 0xfa, 0xf4, 0xde, 0xd0, 0xc2, 0xcc, 0x41, 0x4f, 0x5d, 0x53, + 0x79, 0x77, 0x65, 0x6b, 0x31, 0x3f, 0x2d, 0x23, 0x09, 0x07, 0x15, 0x1b, + 0xa1, 0xaf, 0xbd, 0xb3, 0x99, 0x97, 0x85, 0x8b, 0xd1, 0xdf, 0xcd, 0xc3, + 0xe9, 0xe7, 0xf5, 0xfb, 0x9a, 0x94, 0x86, 0x88, 0xa2, 0xac, 0xbe, 0xb0, + 0xea, 0xe4, 0xf6, 0xf8, 0xd2, 0xdc, 0xce, 0xc0, 0x7a, 0x74, 0x66, 0x68, + 0x42, 0x4c, 0x5e, 0x50, 0x0a, 0x04, 0x16, 0x18, 0x32, 0x3c, 0x2e, 0x20, + 0xec, 0xe2, 0xf0, 0xfe, 0xd4, 0xda, 0xc8, 0xc6, 0x9c, 0x92, 0x80, 0x8e, + 0xa4, 0xaa, 0xb8, 0xb6, 0x0c, 0x02, 0x10, 0x1e, 0x34, 0x3a, 0x28, 0x26, + 0x7c, 0x72, 0x60, 0x6e, 0x44, 0x4a, 0x58, 0x56, 0x37, 0x39, 0x2b, 0x25, + 0x0f, 0x01, 0x13, 0x1d, 0x47, 0x49, 0x5b, 0x55, 0x7f, 0x71, 0x63, 0x6d, + 0xd7, 0xd9, 0xcb, 0xc5, 0xef, 0xe1, 0xf3, 0xfd, 0xa7, 0xa9, 0xbb, 0xb5, + 0x9f, 0x91, 0x83, 0x8d, + }; + + x &= 255; + switch (table) { + case 0x2: + return ffmul02[x]; + case 0x3: + return ffmul03[x]; + case 0x9: + return ffmul09[x]; + case 0xb: + return ffmul0b[x]; + case 0xd: + return ffmul0d[x]; + case 0xe: + return ffmul0e[x]; + case 0: + // Case 0 indicates no table lookup, used for some forward mix stages. + return static_cast(x); + default: + VIXL_UNREACHABLE(); + return static_cast(x); + } +} + + +static uint8_t AESMixInner(uint64_t* x, int stage, bool inverse) { + VIXL_ASSERT(IsUint2(stage)); + + int imc_gm[7] = {0xb, 0xd, 0x9, 0xe}; + int mc_gm[7] = {0x3, 0x0, 0x0, 0x2}; + + int* gm = inverse ? imc_gm : mc_gm; + int index = 3 - stage; + + uint8_t result = 0; + for (int i = 0; i < 4; i++) { + result ^= GalMul(gm[(index + i) % 4], x[i]); + } + return result; +} + + +LogicVRegister Simulator::aesmix(LogicVRegister dst, + const LogicVRegister& src, + bool inverse) { + uint64_t in[16] = {}; + src.UintArray(kFormat16B, in); + dst.ClearForWrite(kFormat16B); + + for (int c = 0; c < 16; c++) { + int cmod4 = c % 4; + int d = c - cmod4; + VIXL_ASSERT((d == 0) || (d == 4) || (d == 8) || (d == 12)); + dst.SetUint(kFormat16B, c, AESMixInner(&in[d], cmod4, inverse)); + } + + return dst; +} + +LogicVRegister Simulator::aes(LogicVRegister dst, + const LogicVRegister& src, + bool decrypt) { + dst.ClearForWrite(kFormat16B); + + // (Inverse) shift rows. + uint8_t shift[] = {0, 5, 10, 15, 4, 9, 14, 3, 8, 13, 2, 7, 12, 1, 6, 11}; + uint8_t shift_inv[] = {0, 13, 10, 7, 4, 1, 14, 11, 8, 5, 2, 15, 12, 9, 6, 3}; + for (int i = 0; i < LaneCountFromFormat(kFormat16B); i++) { + uint8_t index = decrypt ? shift_inv[i] : shift[i]; + dst.SetUint(kFormat16B, i, src.Uint(kFormat16B, index)); + } + + // (Inverse) substitute bytes. + static const uint8_t gf2[256] = { + 0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, 0x30, 0x01, 0x67, 0x2b, + 0xfe, 0xd7, 0xab, 0x76, 0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, + 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0, 0xb7, 0xfd, 0x93, 0x26, + 0x36, 0x3f, 0xf7, 0xcc, 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15, + 0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a, 0x07, 0x12, 0x80, 0xe2, + 0xeb, 0x27, 0xb2, 0x75, 0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, + 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84, 0x53, 0xd1, 0x00, 0xed, + 0x20, 0xfc, 0xb1, 0x5b, 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf, + 0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, 0x45, 0xf9, 0x02, 0x7f, + 0x50, 0x3c, 0x9f, 0xa8, 0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5, + 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2, 0xcd, 0x0c, 0x13, 0xec, + 0x5f, 0x97, 0x44, 0x17, 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73, + 0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, 0x46, 0xee, 0xb8, 0x14, + 0xde, 0x5e, 0x0b, 0xdb, 0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, + 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79, 0xe7, 0xc8, 0x37, 0x6d, + 0x8d, 0xd5, 0x4e, 0xa9, 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08, + 0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, 0xe8, 0xdd, 0x74, 0x1f, + 0x4b, 0xbd, 0x8b, 0x8a, 0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, + 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e, 0xe1, 0xf8, 0x98, 0x11, + 0x69, 0xd9, 0x8e, 0x94, 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf, + 0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, 0x41, 0x99, 0x2d, 0x0f, + 0xb0, 0x54, 0xbb, 0x16, + }; + static const uint8_t gf2_inv[256] = { + 0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38, 0xbf, 0x40, 0xa3, 0x9e, + 0x81, 0xf3, 0xd7, 0xfb, 0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87, + 0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb, 0x54, 0x7b, 0x94, 0x32, + 0xa6, 0xc2, 0x23, 0x3d, 0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e, + 0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2, 0x76, 0x5b, 0xa2, 0x49, + 0x6d, 0x8b, 0xd1, 0x25, 0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16, + 0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92, 0x6c, 0x70, 0x48, 0x50, + 0xfd, 0xed, 0xb9, 0xda, 0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84, + 0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a, 0xf7, 0xe4, 0x58, 0x05, + 0xb8, 0xb3, 0x45, 0x06, 0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02, + 0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b, 0x3a, 0x91, 0x11, 0x41, + 0x4f, 0x67, 0xdc, 0xea, 0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73, + 0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85, 0xe2, 0xf9, 0x37, 0xe8, + 0x1c, 0x75, 0xdf, 0x6e, 0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89, + 0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b, 0xfc, 0x56, 0x3e, 0x4b, + 0xc6, 0xd2, 0x79, 0x20, 0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4, + 0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31, 0xb1, 0x12, 0x10, 0x59, + 0x27, 0x80, 0xec, 0x5f, 0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d, + 0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef, 0xa0, 0xe0, 0x3b, 0x4d, + 0xae, 0x2a, 0xf5, 0xb0, 0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61, + 0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26, 0xe1, 0x69, 0x14, 0x63, + 0x55, 0x21, 0x0c, 0x7d, + }; + + for (int i = 0; i < LaneCountFromFormat(kFormat16B); i++) { + const uint8_t* table = decrypt ? gf2_inv : gf2; + dst.SetUint(kFormat16B, i, table[dst.Uint(kFormat16B, i)]); + } + return dst; +} + +LogicVRegister Simulator::sm3partw1(LogicVRegister srcdst, + const LogicVRegister& src1, + const LogicVRegister& src2) { + using namespace std::placeholders; + auto ROL = std::bind(RotateLeft, _1, _2, kSRegSize); + + SimVRegister temp; + + ext(kFormat16B, temp, src2, temp, 4); + rol(kFormat4S, temp, temp, 15); + eor(kFormat4S, temp, temp, src1); + LogicVRegister r = eor(kFormat4S, temp, temp, srcdst); + + uint64_t result[4] = {}; + r.UintArray(kFormat4S, result); + for (int i = 0; i < 4; i++) { + if (i == 3) { + // result[3] already contains srcdst[3] ^ src1[3] from the operations + // above. + result[i] ^= ROL(result[0], 15); + } + result[i] ^= ROL(result[i], 15) ^ ROL(result[i], 23); + } + srcdst.SetUintArray(kFormat4S, result); + return srcdst; +} + +LogicVRegister Simulator::sm3partw2(LogicVRegister srcdst, + const LogicVRegister& src1, + const LogicVRegister& src2) { + using namespace std::placeholders; + auto ROL = std::bind(RotateLeft, _1, _2, kSRegSize); + + SimVRegister temp; + VectorFormat vf = kFormat4S; + + rol(vf, temp, src2, 7); + LogicVRegister r = eor(vf, temp, temp, src1); + eor(vf, srcdst, temp, srcdst); + + uint64_t tmp2 = ROL(r.Uint(vf, 0), 15); + tmp2 ^= ROL(tmp2, 15) ^ ROL(tmp2, 23); + srcdst.SetUint(vf, 3, srcdst.Uint(vf, 3) ^ tmp2); + return srcdst; +} + +LogicVRegister Simulator::sm3ss1(LogicVRegister dst, + const LogicVRegister& src1, + const LogicVRegister& src2, + const LogicVRegister& src3) { + using namespace std::placeholders; + auto ROL = std::bind(RotateLeft, _1, _2, kSRegSize); + + VectorFormat vf = kFormat4S; + uint64_t result = ROL(src1.Uint(vf, 3), 12); + result += src2.Uint(vf, 3) + src3.Uint(vf, 3); + dst.Clear(); + dst.SetUint(vf, 3, ROL(result, 7)); + return dst; +} + +LogicVRegister Simulator::sm3tt1(LogicVRegister srcdst, + const LogicVRegister& src1, + const LogicVRegister& src2, + int index, + bool is_a) { + VectorFormat vf = kFormat4S; + using namespace std::placeholders; + auto ROL = std::bind(RotateLeft, _1, _2, kSRegSize); + auto sd = std::bind(&LogicVRegister::Uint, srcdst, vf, _1); + + VIXL_ASSERT(IsUint2(index)); + + uint64_t wjprime = src2.Uint(vf, index); + uint64_t ss2 = src1.Uint(vf, 3) ^ ROL(sd(3), 12); + + uint64_t tt1; + if (is_a) { + tt1 = CryptoOp<"parity"_h>(sd(1), sd(2), sd(3)); + } else { + tt1 = CryptoOp<"majority"_h>(sd(1), sd(2), sd(3)); + } + tt1 += sd(0) + ss2 + wjprime; + + ext(kFormat16B, srcdst, srcdst, srcdst, 4); + srcdst.SetUint(vf, 1, ROL(sd(1), 9)); + srcdst.SetUint(vf, 3, tt1); + return srcdst; +} + +LogicVRegister Simulator::sm3tt2(LogicVRegister srcdst, + const LogicVRegister& src1, + const LogicVRegister& src2, + int index, + bool is_a) { + VectorFormat vf = kFormat4S; + using namespace std::placeholders; + auto ROL = std::bind(RotateLeft, _1, _2, kSRegSize); + auto sd = std::bind(&LogicVRegister::Uint, srcdst, vf, _1); + + VIXL_ASSERT(IsUint2(index)); + + uint64_t wj = src2.Uint(vf, index); + + uint64_t tt2; + if (is_a) { + tt2 = CryptoOp<"parity"_h>(sd(1), sd(2), sd(3)); + } else { + tt2 = CryptoOp<"choose"_h>(sd(3), sd(2), sd(1)); + } + tt2 += sd(0) + src1.Uint(vf, 3) + wj; + + ext(kFormat16B, srcdst, srcdst, srcdst, 4); + srcdst.SetUint(vf, 1, ROL(sd(1), 19)); + tt2 ^= ROL(tt2, 9) ^ ROL(tt2, 17); + srcdst.SetUint(vf, 3, tt2); + return srcdst; +} + } // namespace aarch64 } // namespace vixl diff --git a/3rdparty/vixl/src/aarch64/macro-assembler-aarch64.cc b/3rdparty/vixl/src/aarch64/macro-assembler-aarch64.cc index cee9218d2d..af90a4237f 100644 --- a/3rdparty/vixl/src/aarch64/macro-assembler-aarch64.cc +++ b/3rdparty/vixl/src/aarch64/macro-assembler-aarch64.cc @@ -24,10 +24,10 @@ // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -#include - #include "macro-assembler-aarch64.h" +#include + namespace vixl { namespace aarch64 { @@ -194,9 +194,8 @@ void VeneerPool::Reset() { void VeneerPool::Release() { if (--monitor_ == 0) { - VIXL_ASSERT(IsEmpty() || - masm_->GetCursorOffset() < - unresolved_branches_.GetFirstLimit()); + VIXL_ASSERT(IsEmpty() || masm_->GetCursorOffset() < + unresolved_branches_.GetFirstLimit()); } } @@ -313,6 +312,48 @@ void VeneerPool::Emit(EmitOption option, size_t amount) { } +MacroAssembler::MacroAssembler(PositionIndependentCodeOption pic) + : Assembler(pic), +#ifdef VIXL_DEBUG + allow_macro_instructions_(true), +#endif + generate_simulator_code_(VIXL_AARCH64_GENERATE_SIMULATOR_CODE), + sp_(sp), + tmp_list_(ip0, ip1), + v_tmp_list_(d31), + p_tmp_list_(CPURegList::Empty(CPURegister::kPRegister)), + current_scratch_scope_(NULL), + literal_pool_(this), + veneer_pool_(this), + recommended_checkpoint_(Pool::kNoCheckpointRequired), + fp_nan_propagation_(NoFPMacroNaNPropagationSelected) { + checkpoint_ = GetNextCheckPoint(); +#ifndef VIXL_DEBUG + USE(allow_macro_instructions_); +#endif +} + + +MacroAssembler::MacroAssembler(size_t capacity, + PositionIndependentCodeOption pic) + : Assembler(capacity, pic), +#ifdef VIXL_DEBUG + allow_macro_instructions_(true), +#endif + generate_simulator_code_(VIXL_AARCH64_GENERATE_SIMULATOR_CODE), + sp_(sp), + tmp_list_(ip0, ip1), + v_tmp_list_(d31), + p_tmp_list_(CPURegList::Empty(CPURegister::kPRegister)), + current_scratch_scope_(NULL), + literal_pool_(this), + veneer_pool_(this), + recommended_checkpoint_(Pool::kNoCheckpointRequired), + fp_nan_propagation_(NoFPMacroNaNPropagationSelected) { + checkpoint_ = GetNextCheckPoint(); +} + + MacroAssembler::MacroAssembler(byte* buffer, size_t capacity, PositionIndependentCodeOption pic) @@ -363,7 +404,7 @@ void MacroAssembler::FinalizeCode(FinalizeOption option) { void MacroAssembler::CheckEmitFor(size_t amount) { CheckEmitPoolsFor(amount); - VIXL_ASSERT(GetBuffer()->HasSpaceFor(amount)); + GetBuffer()->EnsureSpaceFor(amount); } @@ -1108,11 +1149,14 @@ void MacroAssembler::Ccmp(const Register& rn, StatusFlags nzcv, Condition cond) { VIXL_ASSERT(allow_macro_instructions_); - if (operand.IsImmediate() && (operand.GetImmediate() < 0)) { - ConditionalCompareMacro(rn, -operand.GetImmediate(), nzcv, cond, CCMN); - } else { - ConditionalCompareMacro(rn, operand, nzcv, cond, CCMP); + if (operand.IsImmediate()) { + int64_t imm = operand.GetImmediate(); + if ((imm < 0) && CanBeNegated(imm)) { + ConditionalCompareMacro(rn, -imm, nzcv, cond, CCMN); + return; + } } + ConditionalCompareMacro(rn, operand, nzcv, cond, CCMP); } @@ -1121,11 +1165,14 @@ void MacroAssembler::Ccmn(const Register& rn, StatusFlags nzcv, Condition cond) { VIXL_ASSERT(allow_macro_instructions_); - if (operand.IsImmediate() && (operand.GetImmediate() < 0)) { - ConditionalCompareMacro(rn, -operand.GetImmediate(), nzcv, cond, CCMP); - } else { - ConditionalCompareMacro(rn, operand, nzcv, cond, CCMN); + if (operand.IsImmediate()) { + int64_t imm = operand.GetImmediate(); + if ((imm < 0) && CanBeNegated(imm)) { + ConditionalCompareMacro(rn, -imm, nzcv, cond, CCMP); + return; + } } + ConditionalCompareMacro(rn, operand, nzcv, cond, CCMN); } @@ -1359,8 +1406,7 @@ void MacroAssembler::Add(const Register& rd, VIXL_ASSERT(allow_macro_instructions_); if (operand.IsImmediate()) { int64_t imm = operand.GetImmediate(); - if ((imm < 0) && (imm != std::numeric_limits::min()) && - IsImmAddSub(-imm)) { + if ((imm < 0) && CanBeNegated(imm) && IsImmAddSub(-imm)) { AddSubMacro(rd, rn, -imm, S, SUB); return; } @@ -1447,8 +1493,7 @@ void MacroAssembler::Sub(const Register& rd, VIXL_ASSERT(allow_macro_instructions_); if (operand.IsImmediate()) { int64_t imm = operand.GetImmediate(); - if ((imm < 0) && (imm != std::numeric_limits::min()) && - IsImmAddSub(-imm)) { + if ((imm < 0) && CanBeNegated(imm) && IsImmAddSub(-imm)) { AddSubMacro(rd, rn, -imm, S, ADD); return; } @@ -1609,7 +1654,7 @@ void MacroAssembler::Fmov(VRegister vd, Float16 imm) { void MacroAssembler::Neg(const Register& rd, const Operand& operand) { VIXL_ASSERT(allow_macro_instructions_); - if (operand.IsImmediate()) { + if (operand.IsImmediate() && CanBeNegated(operand.GetImmediate())) { Mov(rd, -operand.GetImmediate()); } else { Sub(rd, AppropriateZeroRegFor(rd), operand); @@ -1925,6 +1970,22 @@ void MacroAssembler::Setf16(const Register& wn) { setf16(wn); } +void MacroAssembler::Chkfeat(const Register& xdn) { + VIXL_ASSERT(allow_macro_instructions_); + MacroEmissionCheckScope guard(this); + if (xdn.Is(x16)) { + chkfeat(xdn); + } else { + UseScratchRegisterScope temps(this); + if (temps.TryAcquire(x16)) { + Mov(x16, xdn); + chkfeat(x16); + Mov(xdn, x16); + } else { + VIXL_ABORT(); + } + } +} #define DEFINE_FUNCTION(FN, REGTYPE, REG, OP) \ void MacroAssembler::FN(const REGTYPE REG, const MemOperand& addr) { \ diff --git a/3rdparty/vixl/src/aarch64/operands-aarch64.cc b/3rdparty/vixl/src/aarch64/operands-aarch64.cc index e01d19074a..d1bd81c5f3 100644 --- a/3rdparty/vixl/src/aarch64/operands-aarch64.cc +++ b/3rdparty/vixl/src/aarch64/operands-aarch64.cc @@ -465,5 +465,5 @@ bool GenericOperand::Equals(const GenericOperand& other) const { } return false; } -} -} // namespace vixl::aarch64 +} // namespace aarch64 +} // namespace vixl diff --git a/3rdparty/vixl/src/aarch64/pointer-auth-aarch64.cc b/3rdparty/vixl/src/aarch64/pointer-auth-aarch64.cc index 55cf4ca592..6bc3751d5b 100644 --- a/3rdparty/vixl/src/aarch64/pointer-auth-aarch64.cc +++ b/3rdparty/vixl/src/aarch64/pointer-auth-aarch64.cc @@ -26,10 +26,10 @@ #ifdef VIXL_INCLUDE_SIMULATOR_AARCH64 -#include "simulator-aarch64.h" - #include "utils-vixl.h" +#include "simulator-aarch64.h" + namespace vixl { namespace aarch64 { @@ -151,7 +151,7 @@ uint64_t Simulator::AuthPAC(uint64_t ptr, uint64_t pac = ComputePAC(original_ptr, context, key); - uint64_t error_code = 1 << key.number; + uint64_t error_code = uint64_t{1} << key.number; if ((pac & pac_mask) == (ptr & pac_mask)) { return original_ptr; } else { diff --git a/3rdparty/vixl/src/aarch64/registers-aarch64.cc b/3rdparty/vixl/src/aarch64/registers-aarch64.cc index 90201a6031..3df7831319 100644 --- a/3rdparty/vixl/src/aarch64/registers-aarch64.cc +++ b/3rdparty/vixl/src/aarch64/registers-aarch64.cc @@ -24,11 +24,11 @@ // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +#include "registers-aarch64.h" + #include #include -#include "registers-aarch64.h" - namespace vixl { namespace aarch64 { @@ -153,7 +153,8 @@ VIXL_CPUREG_COERCION_LIST(VIXL_DEFINE_CPUREG_COERCION) V(2, S) \ V(4, S) \ V(1, D) \ - V(2, D) + V(2, D) \ + V(1, Q) #define VIXL_DEFINE_CPUREG_NEON_COERCION(LANES, LANE_TYPE) \ VRegister VRegister::V##LANES##LANE_TYPE() const { \ VIXL_ASSERT(IsVRegister()); \ @@ -317,5 +318,5 @@ bool AreSameLaneSize(const CPURegister& reg1, !reg4.IsValid() || (reg4.GetLaneSizeInBits() == reg1.GetLaneSizeInBits()); return match; } -} -} // namespace vixl::aarch64 +} // namespace aarch64 +} // namespace vixl diff --git a/3rdparty/vixl/src/code-buffer-vixl.cc b/3rdparty/vixl/src/code-buffer-vixl.cc index 42a3866c8d..2cfe8b71d3 100644 --- a/3rdparty/vixl/src/code-buffer-vixl.cc +++ b/3rdparty/vixl/src/code-buffer-vixl.cc @@ -24,14 +24,51 @@ // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +#ifdef VIXL_CODE_BUFFER_MMAP +extern "C" { +#include +} +#endif + #include "code-buffer-vixl.h" #include "utils-vixl.h" namespace vixl { +CodeBuffer::CodeBuffer(size_t capacity) + : buffer_(NULL), + managed_(true), + cursor_(NULL), + dirty_(false), + capacity_(capacity) { + if (capacity_ == 0) { + return; + } +#ifdef VIXL_CODE_BUFFER_MALLOC + buffer_ = reinterpret_cast(malloc(capacity_)); +#elif defined(VIXL_CODE_BUFFER_MMAP) + buffer_ = reinterpret_cast(mmap(NULL, + capacity, + PROT_READ | PROT_WRITE, + MAP_PRIVATE | MAP_ANONYMOUS, + -1, + 0)); +#else +#error Unknown code buffer allocator. +#endif + VIXL_CHECK(buffer_ != NULL); + // Aarch64 instructions must be word aligned, we assert the default allocator + // always returns word align memory. + VIXL_ASSERT(IsWordAligned(buffer_)); + + cursor_ = buffer_; +} + + CodeBuffer::CodeBuffer(byte* buffer, size_t capacity) : buffer_(reinterpret_cast(buffer)), + managed_(false), cursor_(reinterpret_cast(buffer)), dirty_(false), capacity_(capacity) { @@ -41,6 +78,39 @@ CodeBuffer::CodeBuffer(byte* buffer, size_t capacity) CodeBuffer::~CodeBuffer() VIXL_NEGATIVE_TESTING_ALLOW_EXCEPTION { VIXL_ASSERT(!IsDirty()); + if (managed_) { +#ifdef VIXL_CODE_BUFFER_MALLOC + free(buffer_); +#elif defined(VIXL_CODE_BUFFER_MMAP) + munmap(buffer_, capacity_); +#else +#error Unknown code buffer allocator. +#endif + } +} + + +void CodeBuffer::SetExecutable() { +#ifdef VIXL_CODE_BUFFER_MMAP + int ret = mprotect(buffer_, capacity_, PROT_READ | PROT_EXEC); + VIXL_CHECK(ret == 0); +#else + // This requires page-aligned memory blocks, which we can only guarantee with + // mmap. + VIXL_UNIMPLEMENTED(); +#endif +} + + +void CodeBuffer::SetWritable() { +#ifdef VIXL_CODE_BUFFER_MMAP + int ret = mprotect(buffer_, capacity_, PROT_READ | PROT_WRITE); + VIXL_CHECK(ret == 0); +#else + // This requires page-aligned memory blocks, which we can only guarantee with + // mmap. + VIXL_UNIMPLEMENTED(); +#endif } @@ -78,16 +148,42 @@ void CodeBuffer::Align() { } void CodeBuffer::EmitZeroedBytes(int n) { - VIXL_ASSERT(HasSpaceFor(n)); + EnsureSpaceFor(n); dirty_ = true; memset(cursor_, 0, n); cursor_ += n; } void CodeBuffer::Reset() { +#ifdef VIXL_DEBUG + if (managed_) { + // Fill with zeros (there is no useful value common to A32 and T32). + memset(buffer_, 0, capacity_); + } +#endif cursor_ = buffer_; SetClean(); } +void CodeBuffer::Grow(size_t new_capacity) { + VIXL_ASSERT(managed_); + VIXL_ASSERT(new_capacity > capacity_); + ptrdiff_t cursor_offset = GetCursorOffset(); +#ifdef VIXL_CODE_BUFFER_MALLOC + buffer_ = static_cast(realloc(buffer_, new_capacity)); + VIXL_CHECK(buffer_ != NULL); +#elif defined(VIXL_CODE_BUFFER_MMAP) + buffer_ = static_cast( + mremap(buffer_, capacity_, new_capacity, MREMAP_MAYMOVE)); + VIXL_CHECK(buffer_ != MAP_FAILED); +#else +#error Unknown code buffer allocator. +#endif + + cursor_ = buffer_ + cursor_offset; + capacity_ = new_capacity; +} + + } // namespace vixl diff --git a/3rdparty/vixl/src/compiler-intrinsics-vixl.cc b/3rdparty/vixl/src/compiler-intrinsics-vixl.cc index f6234fa6bf..b8ed1b21a5 100644 --- a/3rdparty/vixl/src/compiler-intrinsics-vixl.cc +++ b/3rdparty/vixl/src/compiler-intrinsics-vixl.cc @@ -25,6 +25,7 @@ // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "compiler-intrinsics-vixl.h" + #include "utils-vixl.h" namespace vixl { diff --git a/3rdparty/vixl/src/cpu-features.cc b/3rdparty/vixl/src/cpu-features.cc index 08db3f44b9..e1bd0f15d4 100644 --- a/3rdparty/vixl/src/cpu-features.cc +++ b/3rdparty/vixl/src/cpu-features.cc @@ -24,9 +24,10 @@ // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +#include "cpu-features.h" + #include -#include "cpu-features.h" #include "globals-vixl.h" #include "utils-vixl.h" diff --git a/3rdparty/vixl/vixl.vcxproj b/3rdparty/vixl/vixl.vcxproj index aaa48905c2..90ca615829 100644 --- a/3rdparty/vixl/vixl.vcxproj +++ b/3rdparty/vixl/vixl.vcxproj @@ -48,6 +48,7 @@ + diff --git a/3rdparty/vixl/vixl.vcxproj.filters b/3rdparty/vixl/vixl.vcxproj.filters index e19bd6cf17..1f01277166 100644 --- a/3rdparty/vixl/vixl.vcxproj.filters +++ b/3rdparty/vixl/vixl.vcxproj.filters @@ -45,6 +45,9 @@ aarch64 + + aarch64 +