mirror of https://github.com/PCSX2/pcsx2.git
The PLZCW bug was quickly found :p Re-enabled the recompiler with the fix.
git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@675 a6443dda-0b58-4228-96e9-037be469359c
This commit is contained in:
ramapcsx2
Gregory Hainaut
parent
9c9d67b3d8
commit
8594b87177
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@ -54,142 +54,142 @@ REC_FUNC_DEL( PSLLH, _Rd_ );
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REC_FUNC_DEL( PSLLW, _Rd_ );
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#else
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// fixme: Recompiled PLZCW breaks God of War, also see BSCPropagate::rpropMMI() if re-eanbling this (rama)
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void recPLZCW()
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{
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recCall( Interp::PLZCW, _Rd_ );
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int regd = -1;
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int regs = 0;
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//int regd = -1;
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//int regs = 0;
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if ( ! _Rd_ ) return;
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//if ( ! _Rd_ ) return;
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if( GPR_IS_CONST1(_Rs_) ) {
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_eeOnWriteReg(_Rd_, 0);
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_deleteEEreg(_Rd_, 0);
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GPR_SET_CONST(_Rd_);
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//if( GPR_IS_CONST1(_Rs_) ) {
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// _eeOnWriteReg(_Rd_, 0);
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// _deleteEEreg(_Rd_, 0);
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// GPR_SET_CONST(_Rd_);
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for(regs = 0; regs < 2; ++regs) {
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u32 val = g_cpuConstRegs[_Rs_].UL[regs];
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// for(regs = 0; regs < 2; ++regs) {
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// u32 val = g_cpuConstRegs[_Rs_].UL[regs];
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if( val != 0 ) {
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u32 setbit = val&0x80000000;
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g_cpuConstRegs[_Rd_].UL[regs] = 0;
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val <<= 1;
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// if( val != 0 ) {
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// u32 setbit = val&0x80000000;
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// g_cpuConstRegs[_Rd_].UL[regs] = 0;
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// val <<= 1;
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while((val & 0x80000000) == setbit) {
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g_cpuConstRegs[_Rd_].UL[regs]++;
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val <<= 1;
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}
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}
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else {
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g_cpuConstRegs[_Rd_].UL[regs] = 31;
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}
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}
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return;
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}
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// while((val & 0x80000000) == setbit) {
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// g_cpuConstRegs[_Rd_].UL[regs]++;
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// val <<= 1;
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// }
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// }
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// else {
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// g_cpuConstRegs[_Rd_].UL[regs] = 31;
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// }
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// }
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// return;
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//}
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_eeOnWriteReg(_Rd_, 0);
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//_eeOnWriteReg(_Rd_, 0);
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if( (regs = _checkXMMreg(XMMTYPE_GPRREG, _Rs_, MODE_READ)) >= 0 ) {
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SSE2_MOVD_XMM_to_R(EAX, regs);
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regs |= MEM_XMMTAG;
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}
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else if( (regs = _checkMMXreg(MMX_GPR+_Rs_, MODE_READ)) >= 0 ) {
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MOVD32MMXtoR(EAX, regs);
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SetMMXstate();
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regs |= MEM_MMXTAG;
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}
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else {
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MOV32MtoR(EAX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
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regs = 0;
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}
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//if( (regs = _checkXMMreg(XMMTYPE_GPRREG, _Rs_, MODE_READ)) >= 0 ) {
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// SSE2_MOVD_XMM_to_R(EAX, regs);
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// regs |= MEM_XMMTAG;
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//}
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//else if( (regs = _checkMMXreg(MMX_GPR+_Rs_, MODE_READ)) >= 0 ) {
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// MOVD32MMXtoR(EAX, regs);
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// SetMMXstate();
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// regs |= MEM_MMXTAG;
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//}
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//else {
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// MOV32MtoR(EAX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
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// regs = 0;
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//}
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if( EEINST_ISLIVE1(_Rd_) )
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_deleteEEreg(_Rd_, 0);
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else {
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if( (regd = _checkMMXreg(MMX_GPR+_Rd_, MODE_WRITE)) < 0 )
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_deleteEEreg(_Rd_, 0);
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}
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//if( EEINST_ISLIVE1(_Rd_) )
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// _deleteEEreg(_Rd_, 0);
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//else {
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// if( (regd = _checkMMXreg(MMX_GPR+_Rd_, MODE_WRITE)) < 0 )
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// _deleteEEreg(_Rd_, 0);
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//}
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// first word
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//// first word
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//TEST32RtoR(EAX, EAX);
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//j8Ptr[0] = JNZ8(0);
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TEST32ItoR(EAX, 0x80000000);
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j8Ptr[0] = JZ8(0);
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NOT32R(EAX);
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x86SetJ8(j8Ptr[0]);
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//// zero, so put 31
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//if( EEINST_ISLIVE1(_Rd_) || regd < 0 ) {
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// MOV32ItoM((uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], 31);
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//}
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//else {
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// SetMMXstate();
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// PCMPEQDRtoR(regd, regd);
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// PSRLQItoR(regd, 59);
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//}
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//j8Ptr[1] = JMP8(0);
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//x86SetJ8(j8Ptr[0]);
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TEST32RtoR(EAX, EAX);
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j8Ptr[0] = JNZ8(0);
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//TEST32ItoR(EAX, 0x80000000);
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//j8Ptr[0] = JZ8(0);
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//NOT32R(EAX);
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//x86SetJ8(j8Ptr[0]);
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// zero, so put 31
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if( EEINST_ISLIVE1(_Rd_) || regd < 0 ) {
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MOV32ItoM((uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], 31);
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}
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else {
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SetMMXstate();
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PCMPEQDRtoR(regd, regd);
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PSRLQItoR(regd, 59);
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}
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//// not zero
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//x86SetJ8(j8Ptr[0]);
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//BSRRtoR(EAX, EAX);
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//MOV32ItoR(ECX, 30);
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//SUB32RtoR(ECX, EAX);
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//if( EEINST_ISLIVE1(_Rd_) || regd < 0 ) {
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// MOV32RtoM((uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], ECX);
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//}
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//else {
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// SetMMXstate();
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// MOVD32RtoMMX(regd, ECX);
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//}
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j8Ptr[1] = JMP8(0);
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x86SetJ8(j8Ptr[0]);
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//x86SetJ8(j8Ptr[1]);
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// not zero
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x86SetJ8(j8Ptr[0]);
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BSRRtoR(EAX, EAX);
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MOV32ItoR(ECX, 30);
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SUB32RtoR(ECX, EAX);
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if( EEINST_ISLIVE1(_Rd_) || regd < 0 ) {
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MOV32RtoM((uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], ECX);
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}
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else {
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SetMMXstate();
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MOVD32RtoMMX(regd, ECX);
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}
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//// second word
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//if( EEINST_ISLIVE1(_Rd_) ) {
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// if( regs >= 0 && (regs & MEM_XMMTAG) ) {
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// SSE2_PSHUFD_XMM_to_XMM(regs&0xf, regs&0xf, 0x4e);
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// SSE2_MOVD_XMM_to_R(EAX, regs&0xf);
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// SSE2_PSHUFD_XMM_to_XMM(regs&0xf, regs&0xf, 0x4e);
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// }
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// else if( regs >= 0 && (regs & MEM_MMXTAG) ) {
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// PSHUFWRtoR(regs, regs, 0x4e);
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// MOVD32MMXtoR(EAX, regs&0xf);
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// PSHUFWRtoR(regs&0xf, regs&0xf, 0x4e);
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// SetMMXstate();
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// }
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// else MOV32MtoR(EAX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ]);
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x86SetJ8(j8Ptr[1]);
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// TEST32RtoR(EAX, EAX);
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// j8Ptr[0] = JNZ8(0);
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// second word
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if( EEINST_ISLIVE1(_Rd_) ) {
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if( regs >= 0 && (regs & MEM_XMMTAG) ) {
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SSE2_PSHUFD_XMM_to_XMM(regs&0xf, regs&0xf, 0x4e);
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SSE2_MOVD_XMM_to_R(EAX, regs&0xf);
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SSE2_PSHUFD_XMM_to_XMM(regs&0xf, regs&0xf, 0x4e);
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}
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else if( regs >= 0 && (regs & MEM_MMXTAG) ) {
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PSHUFWRtoR(regs, regs, 0x4e);
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MOVD32MMXtoR(EAX, regs&0xf);
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PSHUFWRtoR(regs&0xf, regs&0xf, 0x4e);
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SetMMXstate();
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}
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else MOV32MtoR(EAX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ]);
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// // zero, so put 31
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// MOV32ItoM((uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], 31);
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// j8Ptr[1] = JMP8(0);
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// x86SetJ8(j8Ptr[0]);
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TEST32ItoR(EAX, 0x80000000);
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j8Ptr[0] = JZ8(0);
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NOT32R(EAX);
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x86SetJ8(j8Ptr[0]);
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// TEST32ItoR(EAX, 0x80000000);
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// j8Ptr[0] = JZ8(0);
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// NOT32R(EAX);
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// x86SetJ8(j8Ptr[0]);
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TEST32RtoR(EAX, EAX);
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j8Ptr[0] = JNZ8(0);
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// // not zero
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// x86SetJ8(j8Ptr[0]);
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// BSRRtoR(EAX, EAX);
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// MOV32ItoR(ECX, 30);
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// SUB32RtoR(ECX, EAX);
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// MOV32RtoM((uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], ECX);
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// x86SetJ8(j8Ptr[1]);
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//}
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//else {
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// EEINST_RESETHASLIVE1(_Rd_);
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//}
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// zero, so put 31
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MOV32ItoM((uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], 31);
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j8Ptr[1] = JMP8(0);
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x86SetJ8(j8Ptr[0]);
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//GPR_DEL_CONST(_Rd_);
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// not zero
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x86SetJ8(j8Ptr[0]);
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BSRRtoR(EAX, EAX);
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MOV32ItoR(ECX, 30);
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SUB32RtoR(ECX, EAX);
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MOV32RtoM((uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], ECX);
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x86SetJ8(j8Ptr[1]);
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}
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else {
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EEINST_RESETHASLIVE1(_Rd_);
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}
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GPR_DEL_CONST(_Rd_);
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}
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static u32 PCSX2_ALIGNED16(s_CmpMasks[]) = { 0x0000ffff, 0x0000ffff, 0x0000ffff, 0x0000ffff };
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@ -618,10 +618,9 @@ __forceinline void BSCPropagate::rpropMMI()
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case 1: // maddu
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rpropSetLOHI<MODE_READ|MODE_WRITE, MODE_READ|MODE_WRITE>(_Rd_, _Rs_, _Rt_, EEINST_LIVE1);
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break;
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//fixme : recompiler PLZCW() has been replaced with Interpreter, so fall trough here (rama)
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//case 4: // plzcw
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// rpropSetFast(_Rd_, _Rs_, 0, EEINST_LIVE1);
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// break;
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case 4: // plzcw
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rpropSetFast(_Rd_, _Rs_, 0, EEINST_LIVE1);
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break;
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case 8: rpropMMI0(); break;
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case 9: rpropMMI2(); break;
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