mirror of https://github.com/PCSX2/pcsx2.git
IPU: Folded a few related variables into a struct.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2561 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
arcum42
parent
8ef8958e2d
commit
84194fb892
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@ -46,15 +46,13 @@
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#endif
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static tIPU_DMA g_nDMATransfer(0);
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static tIPU_cmd ipu_cmd;
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// FIXME - g_nIPU0Data and Pointer are not saved in the savestate, which breaks savestates for some
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// FMVs at random (if they get saved during the half frame of a 30fps rate). The fix is complicated
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// since coroutine is such a pita. (air)
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int g_nIPU0Data = 0; // data left to transfer
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u8* g_pIPU0Pointer = NULL;
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int g_nCmdPos[2] = {0}, g_nCmdIndex = 0;
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int ipuCurCmd = 0xffffffff;
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void ReorderBitstream();
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@ -140,6 +138,7 @@ int ipuInit()
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init_g_decoder();
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g_nDMATransfer.reset();
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ipu_fifo.init();
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ipu_cmd.clear();
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return 0;
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}
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@ -165,9 +164,9 @@ void ReportIPU()
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Console.WriteLn("coded_block_pattern = 0x%x.", coded_block_pattern);
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Console.WriteLn("g_decoder = 0x%x.", g_decoder);
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Console.WriteLn("mpeg2_scan_norm = 0x%x, mpeg2_scan_alt = 0x%x.", mpeg2_scan_norm, mpeg2_scan_alt);
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Console.WriteLn("g_nCmdPos = 0x%x.", g_nCmdPos);
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Console.WriteLn("g_nCmdIndex = 0x%x.", g_nCmdIndex);
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Console.WriteLn("ipuCurCmd = 0x%x.", ipuCurCmd);
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Console.WriteLn("g_nCmdPos = 0x%x.", ipu_cmd.pos);
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Console.WriteLn("g_nCmdIndex = 0x%x.", ipu_cmd.index);
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Console.WriteLn("ipuCurCmd = 0x%x.", ipu_cmd.current);
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Console.WriteLn("_readbits = 0x%x.", _readbits);
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Console.WriteLn("temp will equal 0x%x.", readbits - _readbits);
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Console.WriteLn("");
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@ -200,9 +199,10 @@ void SaveStateBase::ipuFreeze()
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Freeze(g_decoder);
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Freeze(mpeg2_scan_norm);
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Freeze(mpeg2_scan_alt);
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Freeze(g_nCmdPos);
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Freeze(g_nCmdIndex);
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Freeze(ipuCurCmd);
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//Freeze(ipu_cmd);
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Freeze(ipu_cmd.pos);
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Freeze(ipu_cmd.index);
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Freeze(ipu_cmd.current);
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Freeze(_readbits);
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@ -219,7 +219,7 @@ void SaveStateBase::ipuFreeze()
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bool ipuCanFreeze()
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{
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return (ipuCurCmd == -1);
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return (ipu_cmd.current == -1);
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}
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__forceinline u32 ipuRead32(u32 mem)
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@ -301,15 +301,11 @@ void ipuSoftReset()
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ipuRegs->ctrl.reset();
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ipuRegs->top = 0;
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ipuCurCmd = 0xffffffff;
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ipu_cmd.clear();
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g_BP.BP = 0;
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g_BP.FP = 0;
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g_BP.bufferhasnew = 0;
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g_nCmdIndex = 0;
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g_nCmdPos[0] = 0;
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g_nCmdPos[1] = 0;
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}
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__forceinline void ipuWrite32(u32 mem, u32 value)
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@ -396,29 +392,7 @@ static __forceinline BOOL ipuIDEC(u32 val)
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{
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tIPU_CMD_IDEC idec(val);
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IPU_LOG("IPU IDEC command.");
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if (idec.FB) IPU_LOG(" Skip %d bits.", idec.FB);
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IPU_LOG(" Quantizer step code=0x%X.", idec.QSC);
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if (idec.DTD == 0)
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IPU_LOG(" Does not decode DT.");
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else
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IPU_LOG(" Decodes DT.");
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if (idec.SGN == 0)
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IPU_LOG(" No bias.");
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else
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IPU_LOG(" Bias=128.");
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if (idec.DTE == 1) IPU_LOG(" Dither Enabled.");
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if (idec.OFM == 0)
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IPU_LOG(" Output format is RGB32.");
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else
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IPU_LOG(" Output format is RGB16.");
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IPU_LOG("");
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idec.log();
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g_BP.BP += idec.FB;//skip FB bits
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//from IPU_CTRL
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ipuRegs->ctrl.PCT = I_TYPE; //Intra DECoding;)
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@ -453,28 +427,8 @@ static __forceinline BOOL ipuBDEC(u32 val)
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{
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tIPU_CMD_BDEC bdec(val);
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IPU_LOG("IPU BDEC(macroblock decode) command %x, num: 0x%x", cpuRegs.pc, s_bdec);
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if (bdec.FB) IPU_LOG(" Skip 0x%X bits.", bdec.FB);
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if (bdec.MBI)
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IPU_LOG(" Intra MB.");
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else
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IPU_LOG(" Non-intra MB.");
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if (bdec.DCR)
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IPU_LOG(" Resets DC prediction value.");
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else
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IPU_LOG(" Doesn't reset DC prediction value.");
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if (bdec.DT)
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IPU_LOG(" Use field DCT.");
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else
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IPU_LOG(" Use frame DCT.");
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IPU_LOG(" Quantizer step=0x%X", bdec.QSC);
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if( IsDebugBuild )
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s_bdec++;
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bdec.log(s_bdec);
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if (IsDebugBuild) s_bdec++;
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g_BP.BP += bdec.FB;//skip FB bits
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g_decoder.coding_type = I_TYPE;
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@ -504,7 +458,7 @@ static __forceinline BOOL ipuBDEC(u32 val)
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static BOOL __fastcall ipuVDEC(u32 val)
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{
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switch (g_nCmdPos[0])
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switch (ipu_cmd.pos[0])
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{
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case 0:
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ipuRegs->cmd.DATA = 0;
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@ -551,7 +505,7 @@ static BOOL __fastcall ipuVDEC(u32 val)
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case 1:
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if (!getBits32((u8*)&ipuRegs->top, 0))
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{
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g_nCmdPos[0] = 1;
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ipu_cmd.pos[0] = 1;
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return FALSE;
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}
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@ -586,7 +540,7 @@ static __forceinline BOOL ipuSETIQ(u32 val)
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if ((val >> 27) & 1)
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{
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g_nCmdPos[0] += getBits((u8*)niq + g_nCmdPos[0], 512 - 8 * g_nCmdPos[0], 1); // 8*8*8
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ipu_cmd.pos[0] += getBits((u8*)niq + ipu_cmd.pos[0], 512 - 8 * ipu_cmd.pos[0], 1); // 8*8*8
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IPU_LOG("Read non-intra quantization matrix from IPU FIFO.");
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for (i = 0; i < 8; i++)
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@ -598,7 +552,7 @@ static __forceinline BOOL ipuSETIQ(u32 val)
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}
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else
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{
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g_nCmdPos[0] += getBits((u8*)iq + 8 * g_nCmdPos[0], 512 - 8 * g_nCmdPos[0], 1);
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ipu_cmd.pos[0] += getBits((u8*)iq + 8 * ipu_cmd.pos[0], 512 - 8 * ipu_cmd.pos[0], 1);
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IPU_LOG("Read intra quantization matrix from IPU FIFO.");
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for (i = 0; i < 8; i++)
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@ -609,14 +563,14 @@ static __forceinline BOOL ipuSETIQ(u32 val)
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}
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}
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return g_nCmdPos[0] == 64;
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return ipu_cmd.pos[0] == 64;
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}
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static __forceinline BOOL ipuSETVQ(u32 val)
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{
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g_nCmdPos[0] += getBits((u8*)vqclut + g_nCmdPos[0], 256 - 8 * g_nCmdPos[0], 1); // 16*2*8
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ipu_cmd.pos[0] += getBits((u8*)vqclut + ipu_cmd.pos[0], 256 - 8 * ipu_cmd.pos[0], 1); // 16*2*8
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if (g_nCmdPos[0] == 32)
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if (ipu_cmd.pos[0] == 32)
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{
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IPU_LOG("IPU SETVQ command.\nRead VQCLUT table from IPU FIFO.");
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IPU_LOG(
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@ -642,7 +596,7 @@ static __forceinline BOOL ipuSETVQ(u32 val)
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vqclut[15] >> 10, (vqclut[15] >> 5) & 0x1F, vqclut[15] & 0x1F);
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}
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return g_nCmdPos[0] == 32;
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return ipu_cmd.pos[0] == 32;
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}
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// IPU Transfers are split into 8Qwords so we need to send ALL the data
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@ -659,14 +613,14 @@ static BOOL __fastcall ipuCSC(u32 val)
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if (csc.DTE) IPU_LOG("Dithering enabled.");
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//Console.WriteLn("CSC");
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for (;g_nCmdIndex < (int)csc.MBC; g_nCmdIndex++)
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for (;ipu_cmd.index < (int)csc.MBC; ipu_cmd.index++)
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{
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if (g_nCmdPos[0] < 3072 / 8)
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if (ipu_cmd.pos[0] < 3072 / 8)
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{
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g_nCmdPos[0] += getBits((u8*) & mb8 + g_nCmdPos[0], 3072 - 8 * g_nCmdPos[0], 1);
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ipu_cmd.pos[0] += getBits((u8*) & mb8 + ipu_cmd.pos[0], 3072 - 8 * ipu_cmd.pos[0], 1);
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if (g_nCmdPos[0] < 3072 / 8) return FALSE;
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if (ipu_cmd.pos[0] < 3072 / 8) return FALSE;
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ipu_csc(&mb8, &rgb32, 0);
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if (csc.OFM) ipu_dither(&rgb32, &rgb16, csc.DTE);
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@ -674,25 +628,25 @@ static BOOL __fastcall ipuCSC(u32 val)
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if (csc.OFM)
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{
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while (g_nCmdPos[1] < 32)
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while (ipu_cmd.pos[1] < 32)
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{
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g_nCmdPos[1] += ipu_fifo.out.write(((u32*) & rgb16) + 4 * g_nCmdPos[1], 32 - g_nCmdPos[1]);
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ipu_cmd.pos[1] += ipu_fifo.out.write(((u32*) & rgb16) + 4 * ipu_cmd.pos[1], 32 - ipu_cmd.pos[1]);
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if (g_nCmdPos[1] <= 0) return FALSE;
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if (ipu_cmd.pos[1] <= 0) return FALSE;
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}
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}
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else
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{
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while (g_nCmdPos[1] < 64)
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while (ipu_cmd.pos[1] < 64)
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{
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g_nCmdPos[1] += ipu_fifo.out.write(((u32*) & rgb32) + 4 * g_nCmdPos[1], 64 - g_nCmdPos[1]);
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ipu_cmd.pos[1] += ipu_fifo.out.write(((u32*) & rgb32) + 4 * ipu_cmd.pos[1], 64 - ipu_cmd.pos[1]);
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if (g_nCmdPos[1] <= 0) return FALSE;
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if (ipu_cmd.pos[1] <= 0) return FALSE;
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}
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}
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g_nCmdPos[0] = 0;
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g_nCmdPos[1] = 0;
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ipu_cmd.pos[0] = 0;
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ipu_cmd.pos[1] = 0;
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}
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return TRUE;
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@ -714,13 +668,13 @@ static BOOL ipuPACK(u32 val)
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IPU_LOG("Number of macroblocks to be converted: %d", csc.MBC);
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for (;g_nCmdIndex < (int)csc.MBC; g_nCmdIndex++)
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for (;ipu_cmd.index < (int)csc.MBC; ipu_cmd.index++)
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{
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if (g_nCmdPos[0] < 512)
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if (ipu_cmd.pos[0] < 512)
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{
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g_nCmdPos[0] += getBits((u8*) & mb8 + g_nCmdPos[0], 512 - 8 * g_nCmdPos[0], 1);
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ipu_cmd.pos[0] += getBits((u8*) & mb8 + ipu_cmd.pos[0], 512 - 8 * ipu_cmd.pos[0], 1);
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if (g_nCmdPos[0] < 64) return FALSE;
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if (ipu_cmd.pos[0] < 64) return FALSE;
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ipu_csc(&mb8, &rgb32, 0);
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ipu_dither(&rgb32, &rgb16, csc.DTE);
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@ -730,19 +684,19 @@ static BOOL ipuPACK(u32 val)
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if (csc.OFM)
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{
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g_nCmdPos[1] += ipu_fifo.out.write(((u32*) & rgb16) + 4 * g_nCmdPos[1], 32 - g_nCmdPos[1]);
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ipu_cmd.pos[1] += ipu_fifo.out.write(((u32*) & rgb16) + 4 * ipu_cmd.pos[1], 32 - ipu_cmd.pos[1]);
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if (g_nCmdPos[1] < 32) return FALSE;
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if (ipu_cmd.pos[1] < 32) return FALSE;
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}
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else
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{
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g_nCmdPos[1] += ipu_fifo.out.write(((u32*)indx4) + 4 * g_nCmdPos[1], 8 - g_nCmdPos[1]);
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ipu_cmd.pos[1] += ipu_fifo.out.write(((u32*)indx4) + 4 * ipu_cmd.pos[1], 8 - ipu_cmd.pos[1]);
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if (g_nCmdPos[1] < 8) return FALSE;
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if (ipu_cmd.pos[1] < 8) return FALSE;
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}
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g_nCmdPos[0] = 0;
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g_nCmdPos[1] = 0;
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ipu_cmd.pos[0] = 0;
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ipu_cmd.pos[1] = 0;
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}
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return TRUE;
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@ -771,7 +725,7 @@ void IPUCMD_WRITE(u32 val)
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ipuRegs->ctrl.ECD = 0;
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ipuRegs->ctrl.SCD = 0; //clear ECD/SCD
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ipuRegs->cmd.DATA = val;
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g_nCmdPos[0] = 0;
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ipu_cmd.pos[0] = 0;
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switch (ipuRegs->cmd.CMD)
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{
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@ -817,8 +771,8 @@ void IPUCMD_WRITE(u32 val)
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break;
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case SCE_IPU_CSC:
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g_nCmdPos[1] = 0;
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g_nCmdIndex = 0;
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ipu_cmd.pos[1] = 0;
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ipu_cmd.index = 0;
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if (ipuCSC(ipuRegs->cmd.DATA))
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{
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@ -828,8 +782,8 @@ void IPUCMD_WRITE(u32 val)
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break;
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case SCE_IPU_PACK:
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g_nCmdPos[1] = 0;
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g_nCmdIndex = 0;
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ipu_cmd.pos[1] = 0;
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ipu_cmd.index = 0;
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if (ipuPACK(ipuRegs->cmd.DATA)) return;
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break;
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@ -842,7 +796,7 @@ void IPUCMD_WRITE(u32 val)
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}
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ipuRegs->topbusy = 0x80000000;
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// have to resort to the thread
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ipuCurCmd = val >> 28;
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ipu_cmd.current = val >> 28;
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ipuRegs->ctrl.BUSY = 1;
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return;
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@ -854,13 +808,13 @@ void IPUCMD_WRITE(u32 val)
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return;
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}
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ipuRegs->topbusy = 0x80000000;
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ipuCurCmd = val >> 28;
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ipu_cmd.current = val >> 28;
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ipuRegs->ctrl.BUSY = 1;
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return;
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}
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// have to resort to the thread
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ipuCurCmd = val >> 28;
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ipu_cmd.current = val >> 28;
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ipuRegs->ctrl.BUSY = 1;
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hwIntcIrq(INTC_IPU);
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}
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@ -869,7 +823,7 @@ void IPUWorker()
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{
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pxAssert(ipuRegs->ctrl.BUSY);
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switch (ipuCurCmd)
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switch (ipu_cmd.current)
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{
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case SCE_IPU_VDEC:
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if (!ipuVDEC(ipuRegs->cmd.DATA))
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@ -936,7 +890,7 @@ void IPUWorker()
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ipuRegs->ctrl.BUSY = 0;
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ipuRegs->topbusy = 0;
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ipuRegs->cmd.BUSY = 0;
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ipuCurCmd = 0xffffffff;
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ipu_cmd.current = 0xffffffff;
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// CHECK!: IPU0dma remains when IDEC is done, so we need to clear it
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if (ipu0dma->qwc > 0 && ipu0dma->chcr.STR) IPU_INT0_FROM();
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@ -954,7 +908,7 @@ void IPUWorker()
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ipuRegs->ctrl.BUSY = 0;
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ipuRegs->topbusy = 0;
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ipuRegs->cmd.BUSY = 0;
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ipuCurCmd = 0xffffffff;
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ipu_cmd.current = 0xffffffff;
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if (ipu0dma->qwc > 0 && ipu0dma->chcr.STR) IPU_INT0_FROM();
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s_routine = NULL;
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@ -968,7 +922,7 @@ void IPUWorker()
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// success
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ipuRegs->ctrl.BUSY = 0;
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ipuCurCmd = 0xffffffff;
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ipu_cmd.current = 0xffffffff;
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}
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/////////////////
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@ -124,6 +124,31 @@ union tIPU_CMD_IDEC
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void set_flags(u32 flags) { _u32 |= flags; }
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void clear_flags(u32 flags) { _u32 &= ~flags; }
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void reset() { _u32 = 0; }
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void log()
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{
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IPU_LOG("IPU IDEC command.");
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if (FB) IPU_LOG(" Skip %d bits.", FB);
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IPU_LOG(" Quantizer step code=0x%X.", QSC);
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||||
if (DTD == 0)
|
||||
IPU_LOG(" Does not decode DT.");
|
||||
else
|
||||
IPU_LOG(" Decodes DT.");
|
||||
|
||||
if (SGN == 0)
|
||||
IPU_LOG(" No bias.");
|
||||
else
|
||||
IPU_LOG(" Bias=128.");
|
||||
|
||||
if (DTE == 1) IPU_LOG(" Dither Enabled.");
|
||||
if (OFM == 0)
|
||||
IPU_LOG(" Output format is RGB32.");
|
||||
else
|
||||
IPU_LOG(" Output format is RGB16.");
|
||||
|
||||
IPU_LOG("");
|
||||
}
|
||||
};
|
||||
|
||||
union tIPU_CMD_BDEC
|
||||
|
|
@ -147,6 +172,28 @@ union tIPU_CMD_BDEC
|
|||
void set_flags(u32 flags) { _u32 |= flags; }
|
||||
void clear_flags(u32 flags) { _u32 &= ~flags; }
|
||||
void reset() { _u32 = 0; }
|
||||
void log(int s_bdec)
|
||||
{
|
||||
IPU_LOG("IPU BDEC(macroblock decode) command %x, num: 0x%x", cpuRegs.pc, s_bdec);
|
||||
if (FB) IPU_LOG(" Skip 0x%X bits.", FB);
|
||||
|
||||
if (MBI)
|
||||
IPU_LOG(" Intra MB.");
|
||||
else
|
||||
IPU_LOG(" Non-intra MB.");
|
||||
|
||||
if (DCR)
|
||||
IPU_LOG(" Resets DC prediction value.");
|
||||
else
|
||||
IPU_LOG(" Doesn't reset DC prediction value.");
|
||||
|
||||
if (DT)
|
||||
IPU_LOG(" Use field DCT.");
|
||||
else
|
||||
IPU_LOG(" Use frame DCT.");
|
||||
|
||||
IPU_LOG(" Quantizer step=0x%X", QSC);
|
||||
}
|
||||
};
|
||||
|
||||
union tIPU_CMD_CSC
|
||||
|
|
@ -221,6 +268,20 @@ struct IPUregisters {
|
|||
|
||||
#define ipuRegs ((IPUregisters*)(PS2MEM_HW+0x2000))
|
||||
|
||||
struct tIPU_cmd
|
||||
{
|
||||
int index;
|
||||
int pos[2];
|
||||
int current;
|
||||
void clear()
|
||||
{
|
||||
memzero(pos);
|
||||
index = 0;
|
||||
current = 0xffffffff;
|
||||
}
|
||||
};
|
||||
|
||||
//extern tIPU_cmd ipu_cmd;
|
||||
extern tIPU_BP g_BP;
|
||||
extern int coded_block_pattern;
|
||||
extern int g_nIPU0Data; // or 0x80000000 whenever transferring
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@
|
|||
|
||||
#include "PrecompiledHeader.h"
|
||||
|
||||
#include "Common.h"
|
||||
#include "IPU.h"
|
||||
#include "yuv2rgb.h"
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue