mirror of https://github.com/PCSX2/pcsx2.git
gsdx: properly check SSE support
1/ Check all "levels" 2/ requires AVX for 64 bits
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8b4da69861
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@ -203,38 +203,42 @@ bool GSUtil::HasCompatibleBits(uint32 spsm, uint32 dpsm)
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bool GSUtil::CheckSSE()
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bool GSUtil::CheckSSE()
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{
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{
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bool status = true;
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Xbyak::util::Cpu cpu;
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Xbyak::util::Cpu cpu;
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struct ISA {
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Xbyak::util::Cpu::Type type;
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Xbyak::util::Cpu::Type type;
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const char* instruction_set = "";
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const char* name;
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};
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#if _M_SSE >= 0x501
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ISA checks[] = {
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type = Xbyak::util::Cpu::tAVX2;
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{Xbyak::util::Cpu::tSSE2, "SSE2"},
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instruction_set = "AVX2";
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#if _M_SSE >= 0x301 || defined(_M_AMD64)
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#elif _M_SSE >= 0x500
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{Xbyak::util::Cpu::tSSSE3, "SSSE3"},
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type = Xbyak::util::Cpu::tAVX;
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instruction_set = "AVX";
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#elif _M_SSE >= 0x402
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type = Xbyak::util::Cpu::tSSE42;
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instruction_set = "SSE4.2";
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#elif _M_SSE >= 0x401
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type = Xbyak::util::Cpu::tSSE41;
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instruction_set = "SSE4.1";
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#elif _M_SSE >= 0x301
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type = Xbyak::util::Cpu::tSSSE3;
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instruction_set = "SSSE3";
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#elif _M_SSE >= 0x200
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type = Xbyak::util::Cpu::tSSE2;
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instruction_set = "SSE2";
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#endif
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#endif
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#if _M_SSE >= 0x401 || defined(_M_AMD64)
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{Xbyak::util::Cpu::tSSE41, "SSE41"},
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#endif
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#if _M_SSE >= 0x402 || defined(_M_AMD64)
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{Xbyak::util::Cpu::tSSE42, "SSE42"},
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#endif
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#if _M_SSE >= 0x500 || defined(_M_AMD64)
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{Xbyak::util::Cpu::tAVX, "AVX1"},
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#endif
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#if _M_SSE >= 0x501
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{Xbyak::util::Cpu::tAVX2, "AVX2"},
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#endif
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};
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if(!cpu.has(type))
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for (size_t i = 0; i < countof(checks); i++) {
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{
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if(!cpu.has(checks[i].type)) {
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fprintf(stderr, "This CPU does not support %s\n", instruction_set);
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fprintf(stderr, "This CPU does not support %s\n", checks[i].name);
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return false;
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status = false;
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}
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}
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}
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return true;
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return status;
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}
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}
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#define OCL_PROGRAM_VERSION 3
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#define OCL_PROGRAM_VERSION 3
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