From 822e2a8166de58ae793ff3a14b21f2d7de0010d3 Mon Sep 17 00:00:00 2001 From: gigaherz Date: Mon, 8 Feb 2010 16:19:01 +0000 Subject: [PATCH] Moved some stuff around, removed some unnecessary code, added some comments. No functional changes. Will need updating the linux build files. git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2576 96395faa-99c1-11dd-bbfe-3dabce05a288 --- pcsx2/CDVD/CdRom.cpp | 4 +- pcsx2/IopDma.cpp | 245 +++++++++++++++---------------------------- pcsx2/IopDma.h | 8 +- pcsx2/IopIrq.cpp | 63 +++++++++++ pcsx2/IopSio2.cpp | 6 +- 5 files changed, 158 insertions(+), 168 deletions(-) create mode 100644 pcsx2/IopIrq.cpp diff --git a/pcsx2/CDVD/CdRom.cpp b/pcsx2/CDVD/CdRom.cpp index fcf8fbc880..b1b8d48db9 100644 --- a/pcsx2/CDVD/CdRom.cpp +++ b/pcsx2/CDVD/CdRom.cpp @@ -935,7 +935,7 @@ void psxDma3(u32 madr, u32 bcr, u32 chcr) { } #ifdef ENABLE_NEW_IOPDMA -s32 cdvdDmaRead(s32 channel, u32* data, u32 wordsLeft, u32* wordsProcessed) +s32 CALLBACK cdvdDmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) { #ifdef ENABLE_NEW_IOPDMA_CDVD // hacked up from the code above @@ -957,7 +957,7 @@ s32 cdvdDmaRead(s32 channel, u32* data, u32 wordsLeft, u32* wordsProcessed) return 0; } -void cdvdDmaInterrupt(s32 channel) +void CALLBACK cdvdDmaInterrupt(s32 channel) { #ifdef ENABLE_NEW_IOPDMA_CDVD cdrInterrupt(); diff --git a/pcsx2/IopDma.cpp b/pcsx2/IopDma.cpp index 8f28589306..a7c9512b3b 100644 --- a/pcsx2/IopDma.cpp +++ b/pcsx2/IopDma.cpp @@ -76,17 +76,7 @@ static void __fastcall psxDmaGeneric(u32 madr, u32 bcr, u32 chcr, u32 spuCore, _ break; } } -#endif -void psxDma2(u32 madr, u32 bcr, u32 chcr) // GPU -{ - HW_DMA2_CHCR &= ~0x01000000; - psxDmaInterrupt(2); -} - -/* psxDma3 is in CdRom.cpp */ - -#ifndef ENABLE_NEW_IOPDMA_SPU2 void psxDma4(u32 madr, u32 bcr, u32 chcr) // SPU2's Core 0 { psxDmaGeneric(madr, bcr, chcr, 0, SPU2writeDMA4Mem, SPU2readDMA4Mem); @@ -99,8 +89,43 @@ int psxDma4Interrupt() iopIntcIrq(9); return 1; } + +void spu2DMA4Irq() +{ + SPU2interruptDMA4(); + HW_DMA4_CHCR &= ~0x01000000; + psxDmaInterrupt(4); +} + +void psxDma7(u32 madr, u32 bcr, u32 chcr) // SPU2's Core 1 +{ + psxDmaGeneric(madr, bcr, chcr, 1, SPU2writeDMA7Mem, SPU2readDMA7Mem); +} + +int psxDma7Interrupt() +{ + HW_DMA7_CHCR &= ~0x01000000; + psxDmaInterrupt2(0); + return 1; + +} + +void spu2DMA7Irq() +{ + SPU2interruptDMA7(); + HW_DMA7_CHCR &= ~0x01000000; + psxDmaInterrupt2(0); +} + #endif +#ifndef DISABLE_PSX_GPU_DMAS +void psxDma2(u32 madr, u32 bcr, u32 chcr) // GPU +{ + HW_DMA2_CHCR &= ~0x01000000; + psxDmaInterrupt(2); +} + void psxDma6(u32 madr, u32 bcr, u32 chcr) { u32 *mem = (u32 *)iopPhysMem(madr); @@ -125,20 +150,6 @@ void psxDma6(u32 madr, u32 bcr, u32 chcr) HW_DMA6_CHCR &= ~0x01000000; psxDmaInterrupt(6); } - -#ifndef ENABLE_NEW_IOPDMA_SPU2 -void psxDma7(u32 madr, u32 bcr, u32 chcr) // SPU2's Core 1 -{ - psxDmaGeneric(madr, bcr, chcr, 1, SPU2writeDMA7Mem, SPU2readDMA7Mem); -} - -int psxDma7Interrupt() -{ - HW_DMA7_CHCR &= ~0x01000000; - psxDmaInterrupt2(0); - return 1; - -} #endif #ifndef ENABLE_NEW_IOPDMA_DEV9 @@ -202,66 +213,6 @@ void psxDma10(u32 madr, u32 bcr, u32 chcr) /* psxDma11 & psxDma 12 are in IopSio2.cpp, along with the appropriate interrupt functions. */ -void dev9Interrupt() -{ - if ((dev9Handler != NULL) && (dev9Handler() != 1)) return; - - iopIntcIrq(13); - hwIntcIrq(INTC_SBUS); -} - -void dev9Irq(int cycles) -{ - PSX_INT(IopEvt_DEV9, cycles); -} - -void usbInterrupt() -{ - if (usbHandler != NULL && (usbHandler() != 1)) return; - - iopIntcIrq(22); - hwIntcIrq(INTC_SBUS); -} - -void usbIrq(int cycles) -{ - PSX_INT(IopEvt_USB, cycles); -} - -void fwIrq() -{ - iopIntcIrq(24); - hwIntcIrq(INTC_SBUS); -} - -#ifndef ENABLE_NEW_IOPDMA_SPU2 -void spu2DMA4Irq() -{ - SPU2interruptDMA4(); - HW_DMA4_CHCR &= ~0x01000000; - psxDmaInterrupt(4); -} - -void spu2DMA7Irq() -{ - SPU2interruptDMA7(); - HW_DMA7_CHCR &= ~0x01000000; - psxDmaInterrupt2(0); -} -#endif - -void spu2Irq() -{ - iopIntcIrq(9); - hwIntcIrq(INTC_SBUS); -} - -void iopIntcIrq(uint irqType) -{ - psxHu32(0x1070) |= 1 << irqType; - iopTestIntc(); -} - ////////////////////////////////////////////////////////////////////////////////////////////// // // Gigaherz's "Improved DMA Handling" Engine WIP... @@ -269,67 +220,17 @@ void iopIntcIrq(uint irqType) #ifdef ENABLE_NEW_IOPDMA -s32 spu2DmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) -{ -#ifdef ENABLE_NEW_IOPDMA_SPU2 - return SPU2dmaRead(channel,data,bytesLeft,bytesProcessed); -#else - return 0; -#endif -} +////////////////////////////////////////////////////////////////////////////////////////////// +// Local Declarations -s32 spu2DmaWrite(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) -{ -#ifdef ENABLE_NEW_IOPDMA_SPU2 - return SPU2dmaWrite(channel,data,bytesLeft,bytesProcessed); -#else - *bytesProcessed=0; - return 0; -#endif -} +// in IopSio2.cpp +extern s32 CALLBACK sio2DmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed); +extern s32 CALLBACK sio2DmaWrite(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed); +extern void CALLBACK sio2DmaInterrupt(s32 channel); -void spu2DmaInterrupt(s32 channel) -{ -#ifdef ENABLE_NEW_IOPDMA_SPU2 - SPU2dmaInterrupt(channel); -#endif -} - -s32 dev9DmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) -{ -#ifdef ENABLE_NEW_IOPDMA_DEV9 - return DEV9dmaRead(channel,data,bytesLeft,bytesProcessed); -#else - *bytesProcessed=0; - return 0; -#endif -} - -s32 dev9DmaWrite(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) -{ -#ifdef ENABLE_NEW_IOPDMA_DEV9 - return DEV9dmaWrite(channel,data,bytesLeft,bytesProcessed); -#else - return 0; -#endif -} - -void dev9DmaInterrupt(s32 channel) -{ -#ifdef ENABLE_NEW_IOPDMA_DEV9 - DEV9dmaInterrupt(channel); -#endif -} - -//typedef s32(* DmaHandler)(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed); -//typedef void (* DmaIHandler)(s32 channel); - -extern s32 sio2DmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed); -extern s32 sio2DmaWrite(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed); -extern void sio2DmaInterrupt(s32 channel); - -s32 errDmaWrite(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed); -s32 errDmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed); +// implemented below +s32 CALLBACK errDmaWrite(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed); +s32 CALLBACK errDmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed); // constants struct DmaHandlerInfo @@ -366,34 +267,46 @@ struct DmaHandlerInfo #define _ER_ 6 #define _ERW 7 +////////////////////////////////////////////////////////////////////////////////////////////// +// Dma channel definitions + const DmaHandlerInfo IopDmaHandlers[DMA_CHANNEL_MAX] = { // First DMAC, same as PS1 - {"Ps1 Mdec", _D__}, //0 - {"Ps1 Mdec", _D__}, //1 + {"Ps1 Mdec in", _D__}, //0 + {"Ps1 Mdec out", _D__}, //1 {"Ps1 Gpu", _D__}, //2 - {"CDVD", _DR_, CHANNEL_BASE1(3), cdvdDmaRead, errDmaWrite, cdvdDmaInterrupt}, //3: CDVD +#ifdef ENABLE_NEW_IOPDMA_CDVD + {"CDVD", _ER_, CHANNEL_BASE1(3), cdvdDmaRead, errDmaWrite, cdvdDmaInterrupt}, //3: CDVD +#else + {"CDVD", _D__}, //3: CDVD +#endif #ifdef ENABLE_NEW_IOPDMA_SPU2 - {"SPU2 Core0", _ERW, CHANNEL_BASE1(4), spu2DmaRead, spu2DmaWrite, spu2DmaInterrupt}, //4: Spu/Spu2 Core0 + {"SPU2 Core0", _ERW, CHANNEL_BASE1(4), SPU2dmaRead, SPU2dmaWrite, SPU2dmaInterrupt}, //4: Spu/Spu2 Core0 #else {"SPU2 Core0", _D__}, //4: Spu/Spu2 Core0 #endif - {"?", _D__}, //5 - {"OT", _D__}, //6: OT? + {"Ps1 PIO", _D__}, //5: PIO + {"Ps1 OTC", _D__}, //6: "reverse clear OT" - PSX GPU related // Second DMAC, new in PS2 IOP #ifdef ENABLE_NEW_IOPDMA_SPU2 - {"SPU2 Core1", _ERW, CHANNEL_BASE2(0), spu2DmaRead, spu2DmaWrite, spu2DmaInterrupt}, //7: Spu2 Core1 + {"SPU2 Core1", _ERW, CHANNEL_BASE2(0), SPU2dmaRead, SPU2dmaWrite, SPU2dmaInterrupt}, //7: Spu2 Core1 #else {"SPU2 Core1", _D__}, //7: Spu2 Core1 #endif #ifdef ENABLE_NEW_IOPDMA_DEV9 - {"Dev9", _ERW, CHANNEL_BASE2(1), dev9DmaRead, dev9DmaWrite, dev9DmaInterrupt}, //8: Dev9 + {"Dev9", _ERW, CHANNEL_BASE2(1), DEV9dmaRead, DEV9dmaWrite, DEV9dmaInterrupt}, //8: Dev9 #else {"Dev9", _D__}, //8: Dev9 #endif - {"Sif0", _DRW},// CHANNEL_BASE2(2), sif0DmaRead, sif0DmaWrite, sif0DmaInterrupt}, //9: SIF0 - {"Sif1", _DRW},// CHANNEL_BASE2(3), sif1DmaRead, sif1DmaWrite, sif1DmaInterrupt}, //10: SIF1 +#ifdef ENABLE_NEW_IOPDMA_SIF + {"Sif0", _ERW, CHANNEL_BASE2(2), sif0DmaRead, sif0DmaWrite, sif0DmaInterrupt}, //9: SIF0 + {"Sif1", _ERW, CHANNEL_BASE2(3), sif1DmaRead, sif1DmaWrite, sif1DmaInterrupt}, //10: SIF1 +#else + {"Sif0", _D__}, //9: SIF0 + {"Sif1", _D__}, //10: SIF1 +#endif #ifdef ENABLE_NEW_IOPDMA_SIO {"Sio2 (writes)", _E_W, CHANNEL_BASE2(4), errDmaRead, sio2DmaWrite, sio2DmaInterrupt}, //11: Sio2 {"Sio2 (reads)", _ER_, CHANNEL_BASE2(5), sio2DmaRead, errDmaWrite, sio2DmaInterrupt}, //12: Sio2 @@ -412,7 +325,9 @@ struct DmaChannelInfo s32 NextUpdate; } IopDmaChannels[DMA_CHANNEL_MAX] = {0}; -// Prototypes. To be implemented later (or in other parts of the emulator) + +////////////////////////////////////////////////////////////////////////////////////////////// +// Tool functions void SetDmaUpdateTarget(u32 delay) { psxCounters[8].CycleT = delay; @@ -428,6 +343,9 @@ void RaiseDmaIrq(u32 channel) psxDmaInterrupt2(channel-7); } +////////////////////////////////////////////////////////////////////////////////////////////// +// IopDmaStart: Called from IopHwWrite to test and possibly start a dma transfer + void IopDmaStart(int channel) { if(!(IopDmaHandlers[channel].DirectionFlags&_E__)) @@ -484,6 +402,9 @@ void IopDmaStart(int channel) } } +////////////////////////////////////////////////////////////////////////////////////////////// +// IopDmaProcessChannel: Called from IopDmaUpdate (below) to process a dma channel + template static void __releaseinline IopDmaProcessChannel(int elapsed, int& MinDelay) { @@ -497,9 +418,9 @@ static void __releaseinline IopDmaProcessChannel(int elapsed, int& MinDelay) if (hh->REG_CHCR()&DMA_CTRL_ACTIVE) { ch->NextUpdate -= elapsed; - if (ch->NextUpdate <= 0) + if (ch->NextUpdate <= 0) // Refresh target passed { - if (ch->ByteCount <= 0) + if (ch->ByteCount <= 0) // No more data left, finish dma { ch->NextUpdate = 0x7fffffff; @@ -507,7 +428,7 @@ static void __releaseinline IopDmaProcessChannel(int elapsed, int& MinDelay) RaiseDmaIrq(channel); hh->Interrupt(channel); } - else + else // let the handlers transfer more data { int chcr = hh->REG_CHCR(); @@ -555,6 +476,9 @@ static void __releaseinline IopDmaProcessChannel(int elapsed, int& MinDelay) } } +////////////////////////////////////////////////////////////////////////////////////////////// +// IopDmaProcessChannel: Called regularly to update the active channels + void IopDmaUpdate(u32 elapsed) { s32 MinDelay=0; @@ -595,7 +519,10 @@ void IopDmaUpdate(u32 elapsed) } } -s32 errDmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) +////////////////////////////////////////////////////////////////////////////////////////////// +// Error functions: dummy functions for unsupported dma "directions" + +s32 CALLBACK errDmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) { Console.Error("ERROR: Tried to read using DMA %d (%s). Ignoring.", channel, IopDmaHandlers[channel]); @@ -603,7 +530,7 @@ s32 errDmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) return 0; } -s32 errDmaWrite(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) +s32 CALLBACK errDmaWrite(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) { Console.Error("ERROR: Tried to write using DMA %d (%s). Ignoring.", channel, IopDmaHandlers[channel]); diff --git a/pcsx2/IopDma.h b/pcsx2/IopDma.h index 84378c5f1d..c2dd2864a4 100644 --- a/pcsx2/IopDma.h +++ b/pcsx2/IopDma.h @@ -22,8 +22,8 @@ #ifdef ENABLE_NEW_IOPDMA -typedef s32(* DmaHandler)(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed); -typedef void (* DmaIHandler)(s32 channel); +typedef s32(CALLBACK * DmaHandler)(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed); +typedef void (CALLBACK * DmaIHandler)(s32 channel); // unused for now class DmaBcrReg @@ -57,8 +57,8 @@ extern void IopDmaStart(int channel); extern void IopDmaUpdate(u32 elapsed); // external dma handlers -extern s32 cdvdDmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed); -extern void cdvdDmaInterrupt(s32 channel); +extern s32 CALLBACK cdvdDmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed); +extern void CALLBACK cdvdDmaInterrupt(s32 channel); //#else #endif diff --git a/pcsx2/IopIrq.cpp b/pcsx2/IopIrq.cpp new file mode 100644 index 0000000000..762adf7322 --- /dev/null +++ b/pcsx2/IopIrq.cpp @@ -0,0 +1,63 @@ +/* PCSX2 - PS2 Emulator for PCs + * Copyright (C) 2002-2009 PCSX2 Dev Team + * + * PCSX2 is free software: you can redistribute it and/or modify it under the terms + * of the GNU Lesser General Public License as published by the Free Software Found- + * ation, either version 3 of the License, or (at your option) any later version. + * + * PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR + * PURPOSE. See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with PCSX2. + * If not, see . + */ + +#include "PrecompiledHeader.h" +#include "IopCommon.h" + +using namespace R3000A; + +void dev9Interrupt() +{ + if ((dev9Handler != NULL) && (dev9Handler() != 1)) return; + + iopIntcIrq(13); + hwIntcIrq(INTC_SBUS); +} + +void dev9Irq(int cycles) +{ + PSX_INT(IopEvt_DEV9, cycles); +} + +void usbInterrupt() +{ + if (usbHandler != NULL && (usbHandler() != 1)) return; + + iopIntcIrq(22); + hwIntcIrq(INTC_SBUS); +} + +void usbIrq(int cycles) +{ + PSX_INT(IopEvt_USB, cycles); +} + +void fwIrq() +{ + iopIntcIrq(24); + hwIntcIrq(INTC_SBUS); +} + +void spu2Irq() +{ + iopIntcIrq(9); + hwIntcIrq(INTC_SBUS); +} + +void iopIntcIrq(uint irqType) +{ + psxHu32(0x1070) |= 1 << irqType; + iopTestIntc(); +} diff --git a/pcsx2/IopSio2.cpp b/pcsx2/IopSio2.cpp index fe479fb59a..5869c49050 100644 --- a/pcsx2/IopSio2.cpp +++ b/pcsx2/IopSio2.cpp @@ -212,7 +212,7 @@ void SaveStateBase::sio2Freeze() ///////////////////////////////////////////////// #ifdef ENABLE_NEW_IOPDMA -s32 sio2DmaRead(s32 channel, u32* tdata, u32 bytesLeft, u32* bytesProcessed) +s32 CALLBACK sio2DmaRead(s32 channel, u32* tdata, u32 bytesLeft, u32* bytesProcessed) { #ifdef ENABLE_NEW_IOPDMA_SIO u8* data = (u8*)tdata; @@ -250,7 +250,7 @@ void sio2DmaSetBs(int bs) sioBs = bs; } -s32 sio2DmaWrite(s32 channel, u32* tdata, u32 bytesLeft, u32* bytesProcessed) +s32 CALLBACK sio2DmaWrite(s32 channel, u32* tdata, u32 bytesLeft, u32* bytesProcessed) { #ifdef ENABLE_NEW_IOPDMA_SIO u8* data = (u8*)tdata; @@ -300,7 +300,7 @@ s32 sio2DmaWrite(s32 channel, u32* tdata, u32 bytesLeft, u32* bytesProcessed) return 0; } -void sio2DmaInterrupt(s32 channel) +void CALLBACK sio2DmaInterrupt(s32 channel) { #ifdef ENABLE_NEW_IOPDMA_SIO switch(channel) // Interrupts should always occur at the end