mirror of https://github.com/PCSX2/pcsx2.git
3rdparty: Update xbyak to 7.06
Might fix a crash on older AMD CPUs apparently.
This commit is contained in:
JordanTheToaster
refractionpcsx2
parent
1ec4c248fb
commit
7d530228e3
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@ -155,7 +155,7 @@ namespace Xbyak {
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enum {
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DEFAULT_MAX_CODE_SIZE = 4096,
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VERSION = 0x7051 /* 0xABCD = A.BC(.D) */
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VERSION = 0x7060 /* 0xABCD = A.BC(.D) */
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};
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#ifndef MIE_INTEGER_TYPE_DEFINED
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@ -1,4 +1,4 @@
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const char *getVersionString() const { return "7.05.1"; }
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const char *getVersionString() const { return "7.06"; }
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void aadd(const Address& addr, const Reg32e ®) { opMR(addr, reg, T_0F38, 0x0FC, T_APX); }
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void aand(const Address& addr, const Reg32e ®) { opMR(addr, reg, T_0F38|T_66, 0x0FC, T_APX|T_66); }
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void adc(const Operand& op, uint32_t imm) { opOI(op, imm, 0x10, 2); }
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@ -91,7 +91,8 @@ namespace Xbyak { namespace util {
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typedef enum {
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SmtLevel = 1,
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CoreLevel = 2
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} IntelCpuTopologyLevel;
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} CpuTopologyLevel;
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typedef CpuTopologyLevel IntelCpuTopologyLevel; // for backward compatibility
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namespace local {
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@ -136,13 +137,12 @@ public:
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private:
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Type type_;
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//system topology
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bool x2APIC_supported_;
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static const size_t maxTopologyLevels = 2;
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uint32_t numCores_[maxTopologyLevels];
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static const uint32_t maxNumberCacheLevels = 10;
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uint32_t dataCacheSize_[maxNumberCacheLevels];
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uint32_t coresSharignDataCache_[maxNumberCacheLevels];
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uint32_t coresSharingDataCache_[maxNumberCacheLevels];
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uint32_t dataCacheLevels_;
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uint32_t avx10version_;
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@ -154,123 +154,200 @@ private:
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{
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return (1U << n) - 1;
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}
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// [EBX:ECX:EDX] == s?
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bool isEqualStr(uint32_t EBX, uint32_t ECX, uint32_t EDX, const char s[12]) const
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{
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return get32bitAsBE(&s[0]) == EBX && get32bitAsBE(&s[4]) == EDX && get32bitAsBE(&s[8]) == ECX;
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}
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uint32_t extractBit(uint32_t val, uint32_t base, uint32_t end) const
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{
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return (val >> base) & ((1u << (end + 1 - base)) - 1);
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}
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void setFamily()
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{
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uint32_t data[4] = {};
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getCpuid(1, data);
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stepping = data[0] & mask(4);
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model = (data[0] >> 4) & mask(4);
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family = (data[0] >> 8) & mask(4);
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// type = (data[0] >> 12) & mask(2);
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extModel = (data[0] >> 16) & mask(4);
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extFamily = (data[0] >> 20) & mask(8);
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stepping = extractBit(data[0], 0, 3);
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model = extractBit(data[0], 4, 7);
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family = extractBit(data[0], 8, 11);
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//type = extractBit(data[0], 12, 13);
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extModel = extractBit(data[0], 16, 19);
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extFamily = extractBit(data[0], 20, 27);
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if (family == 0x0f) {
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displayFamily = family + extFamily;
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} else {
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displayFamily = family;
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}
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if (family == 6 || family == 0x0f) {
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if ((has(tINTEL) && family == 6) || family == 0x0f) {
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displayModel = (extModel << 4) + model;
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} else {
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displayModel = model;
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}
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}
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uint32_t extractBit(uint32_t val, uint32_t base, uint32_t end)
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{
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return (val >> base) & ((1u << (end + 1 - base)) - 1);
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}
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void setNumCores()
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{
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if (!has(tINTEL) && !has(tAMD)) return;
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uint32_t data[4] = {};
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getCpuidEx(0x0, 0, data);
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getCpuid(0x0, data);
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if (data[0] >= 0xB) {
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// Check if "Extended Topology Enumeration" is implemented.
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getCpuidEx(0xB, 0, data);
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if (data[0] != 0 || data[1] != 0) {
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/*
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if leaf 11 exists(x2APIC is supported),
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we use it to get the number of smt cores and cores on socket
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leaf 0xB can be zeroed-out by a hypervisor
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*/
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x2APIC_supported_ = true;
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for (uint32_t i = 0; i < maxTopologyLevels; i++) {
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getCpuidEx(0xB, i, data);
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IntelCpuTopologyLevel level = (IntelCpuTopologyLevel)extractBit(data[2], 8, 15);
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CpuTopologyLevel level = (CpuTopologyLevel)extractBit(data[2], 8, 15);
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if (level == SmtLevel || level == CoreLevel) {
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numCores_[level - 1] = extractBit(data[1], 0, 15);
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}
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}
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/*
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Fallback values in case a hypervisor has 0xB leaf zeroed-out.
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Fallback values in case a hypervisor has the leaf zeroed-out.
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*/
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numCores_[SmtLevel - 1] = local::max_(1u, numCores_[SmtLevel - 1]);
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numCores_[CoreLevel - 1] = local::max_(numCores_[SmtLevel - 1], numCores_[CoreLevel - 1]);
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return;
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}
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}
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// "Extended Topology Enumeration" is not supported.
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if (has(tAMD)) {
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/*
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AMD - Legacy Method
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*/
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int physicalThreadCount = 0;
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getCpuid(0x1, data);
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int logicalProcessorCount = extractBit(data[1], 16, 23);
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int htt = extractBit(data[3], 28, 28); // Hyper-threading technology.
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getCpuid(0x80000000, data);
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uint32_t highestExtendedLeaf = data[0];
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if (highestExtendedLeaf >= 0x80000008) {
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getCpuid(0x80000008, data);
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physicalThreadCount = extractBit(data[2], 0, 7) + 1;
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}
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if (htt == 0) {
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numCores_[SmtLevel - 1] = 1;
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numCores_[CoreLevel - 1] = 1;
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} else if (physicalThreadCount > 1) {
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if ((displayFamily >= 0x17) && (highestExtendedLeaf >= 0x8000001E)) {
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// Zen overreports its core count by a factor of two.
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getCpuid(0x8000001E, data);
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int threadsPerComputeUnit = extractBit(data[1], 8, 15) + 1;
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physicalThreadCount /= threadsPerComputeUnit;
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}
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numCores_[SmtLevel - 1] = logicalProcessorCount / physicalThreadCount;
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numCores_[CoreLevel - 1] = logicalProcessorCount;
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} else {
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numCores_[SmtLevel - 1] = 1;
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numCores_[CoreLevel - 1] = logicalProcessorCount > 1 ? logicalProcessorCount : 2;
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}
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} else {
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/*
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Failed to deremine num of cores without x2APIC support.
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TODO: USE initial APIC ID to determine ncores.
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Intel - Legacy Method
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*/
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numCores_[SmtLevel - 1] = 0;
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numCores_[CoreLevel - 1] = 0;
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int physicalThreadCount = 0;
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getCpuid(0x1, data);
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int logicalProcessorCount = extractBit(data[1], 16, 23);
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int htt = extractBit(data[3], 28, 28); // Hyper-threading technology.
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getCpuid(0, data);
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if (data[0] >= 0x4) {
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getCpuid(0x4, data);
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physicalThreadCount = extractBit(data[0], 26, 31) + 1;
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}
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if (htt == 0) {
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numCores_[SmtLevel - 1] = 1;
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numCores_[CoreLevel - 1] = 1;
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} else if (physicalThreadCount > 1) {
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numCores_[SmtLevel - 1] = logicalProcessorCount / physicalThreadCount;
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numCores_[CoreLevel - 1] = logicalProcessorCount;
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} else {
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numCores_[SmtLevel - 1] = 1;
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numCores_[CoreLevel - 1] = logicalProcessorCount > 0 ? logicalProcessorCount : 1;
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}
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}
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}
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void setCacheHierarchy()
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{
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if (!has(tINTEL) && !has(tAMD)) return;
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// https://github.com/amd/ZenDNN/blob/a08bf9a9efc160a69147cdecfb61cc85cc0d4928/src/cpu/x64/xbyak/xbyak_util.h#L236-L288
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if (has(tAMD)) {
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// There are 3 Data Cache Levels (L1, L2, L3)
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dataCacheLevels_ = 3;
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const uint32_t leaf = 0x8000001D; // for modern AMD CPus
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// Sub leaf value ranges from 0 to 3
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// Sub leaf value 0 refers to L1 Data Cache
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// Sub leaf value 1 refers to L1 Instruction Cache
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// Sub leaf value 2 refers to L2 Cache
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// Sub leaf value 3 refers to L3 Cache
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// For legacy AMD CPU, use leaf 0x80000005 for L1 cache
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// and 0x80000006 for L2 and L3 cache
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int cache_index = 0;
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for (uint32_t sub_leaf = 0; sub_leaf <= dataCacheLevels_; sub_leaf++) {
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// Skip sub_leaf = 1 as it refers to
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// L1 Instruction Cache (not required)
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if (sub_leaf == 1) {
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continue;
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}
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uint32_t data[4] = {};
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getCpuidEx(leaf, sub_leaf, data);
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// Cache Size = Line Size * Partitions * Associativity * Cache Sets
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dataCacheSize_[cache_index] =
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(extractBit(data[1], 22, 31) + 1) // Associativity-1
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* (extractBit(data[1], 12, 21) + 1) // Partitions-1
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* (extractBit(data[1], 0, 11) + 1) // Line Size
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* (data[2] + 1);
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// Calculate the number of cores sharing the current data cache
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int smt_width = numCores_[0];
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int logical_cores = numCores_[1];
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int actual_logical_cores = extractBit(data[0], 14, 25) /* # of cores * # of threads */ + 1;
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if (logical_cores != 0) {
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actual_logical_cores = local::min_(actual_logical_cores, logical_cores);
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if (has(tAMD)) {
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getCpuid(0x80000000, data);
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if (data[0] >= 0x8000001D) {
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// For modern AMD CPUs.
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dataCacheLevels_ = 0;
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for (uint32_t subLeaf = 0; dataCacheLevels_ < maxNumberCacheLevels; subLeaf++) {
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getCpuidEx(0x8000001D, subLeaf, data);
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int cacheType = extractBit(data[0], 0, 4);
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/*
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cacheType
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00h - Null; no more caches
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01h - Data cache
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02h - Instrution cache
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03h - Unified cache
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04h-1Fh - Reserved
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*/
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if (cacheType == 0) break; // No more caches.
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if (cacheType == 0x2) continue; // Skip instruction cache.
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int fullyAssociative = extractBit(data[0], 9, 9);
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int numSharingCache = extractBit(data[0], 14, 25) + 1;
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int cacheNumWays = extractBit(data[1], 22, 31) + 1;
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int cachePhysPartitions = extractBit(data[1], 12, 21) + 1;
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int cacheLineSize = extractBit(data[1], 0, 11) + 1;
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int cacheNumSets = data[2] + 1;
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dataCacheSize_[dataCacheLevels_] =
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cacheLineSize * cachePhysPartitions * cacheNumWays;
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if (fullyAssociative == 0) {
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dataCacheSize_[dataCacheLevels_] *= cacheNumSets;
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}
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coresSharignDataCache_[cache_index] = local::max_(actual_logical_cores / smt_width, 1);
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++cache_index;
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if (subLeaf > 0) {
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numSharingCache = local::min_(numSharingCache, (int)numCores_[1]);
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numSharingCache /= local::max_(1u, coresSharingDataCache_[0]);
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}
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return;
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coresSharingDataCache_[dataCacheLevels_] = numSharingCache;
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dataCacheLevels_ += 1;
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}
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// intel
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coresSharingDataCache_[0] = local::min_(1u, coresSharingDataCache_[0]);
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} else if (data[0] >= 0x80000006) {
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// For legacy AMD CPUs, use leaf 0x80000005 for L1 cache
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// and 0x80000006 for L2 and L3 cache.
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dataCacheLevels_ = 1;
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getCpuid(0x80000005, data);
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int l1dc_size = extractBit(data[2], 24, 31);
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dataCacheSize_[0] = l1dc_size * 1024;
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coresSharingDataCache_[0] = 1;
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getCpuid(0x80000006, data);
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// L2 cache
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int l2_assoc = extractBit(data[2], 12, 15);
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if (l2_assoc > 0) {
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dataCacheLevels_ = 2;
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int l2_size = extractBit(data[2], 16, 31);
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dataCacheSize_[1] = l2_size * 1024;
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coresSharingDataCache_[1] = 1;
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}
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// L3 cache
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int l3_assoc = extractBit(data[3], 12, 15);
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if (l3_assoc > 0) {
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dataCacheLevels_ = 3;
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int l3_size = extractBit(data[3], 18, 31);
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dataCacheSize_[2] = l3_size * 512 * 1024;
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coresSharingDataCache_[2] = numCores_[1];
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}
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}
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} else if (has(tINTEL)) {
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// Use the "Deterministic Cache Parameters" leaf is supported.
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const uint32_t NO_CACHE = 0;
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const uint32_t DATA_CACHE = 1;
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//const uint32_t INSTRUCTION_CACHE = 2;
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const uint32_t UNIFIED_CACHE = 3;
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uint32_t smt_width = 0;
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uint32_t logical_cores = 0;
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uint32_t data[4] = {};
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if (x2APIC_supported_) {
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smt_width = numCores_[0];
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logical_cores = numCores_[1];
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}
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/*
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Assumptions:
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@ -298,11 +375,12 @@ private:
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* (data[2] + 1);
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if (cacheType == DATA_CACHE && smt_width == 0) smt_width = actual_logical_cores;
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assert(smt_width != 0);
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coresSharignDataCache_[dataCacheLevels_] = local::max_(actual_logical_cores / smt_width, 1u);
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coresSharingDataCache_[dataCacheLevels_] = local::max_(actual_logical_cores / smt_width, 1u);
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dataCacheLevels_++;
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}
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}
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}
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}
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public:
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int model;
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@ -313,8 +391,7 @@ public:
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int displayFamily; // family + extFamily
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int displayModel; // model + extModel
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uint32_t getNumCores(IntelCpuTopologyLevel level) const {
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if (!x2APIC_supported_) XBYAK_THROW_RET(ERR_X2APIC_IS_NOT_SUPPORTED, 0)
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uint32_t getNumCores(CpuTopologyLevel level) const {
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switch (level) {
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case SmtLevel: return numCores_[level - 1];
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case CoreLevel: return numCores_[level - 1] / numCores_[SmtLevel - 1];
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@ -326,7 +403,7 @@ public:
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uint32_t getCoresSharingDataCache(uint32_t i) const
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{
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if (i >= dataCacheLevels_) XBYAK_THROW_RET(ERR_BAD_PARAMETER, 0)
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return coresSharignDataCache_[i];
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return coresSharingDataCache_[i];
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}
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uint32_t getDataCacheSize(uint32_t i) const
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{
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@ -337,19 +414,6 @@ public:
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/*
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data[] = { eax, ebx, ecx, edx }
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*/
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static inline void getCpuid(uint32_t eaxIn, uint32_t data[4])
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{
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#ifdef XBYAK_INTEL_CPU_SPECIFIC
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#ifdef _WIN32
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__cpuid(reinterpret_cast<int*>(data), eaxIn);
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#else
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__cpuid(eaxIn, data[0], data[1], data[2], data[3]);
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#endif
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#else
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(void)eaxIn;
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(void)data;
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#endif
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}
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static inline void getCpuidEx(uint32_t eaxIn, uint32_t ecxIn, uint32_t data[4])
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{
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#ifdef XBYAK_INTEL_CPU_SPECIFIC
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@ -364,6 +428,10 @@ public:
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(void)data;
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#endif
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}
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static inline void getCpuid(uint32_t eaxIn, uint32_t data[4])
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{
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getCpuidEx(eaxIn, 0, data);
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}
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static inline uint64_t getXfeature()
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{
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#ifdef XBYAK_INTEL_CPU_SPECIFIC
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@ -485,10 +553,9 @@ public:
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Cpu()
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: type_()
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, x2APIC_supported_(false)
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, numCores_()
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, dataCacheSize_()
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, coresSharignDataCache_()
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, coresSharingDataCache_()
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, dataCacheLevels_(0)
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, avx10version_(0)
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{
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@ -499,9 +566,7 @@ public:
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const uint32_t& EDX = data[3];
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getCpuid(0, data);
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const uint32_t maxNum = EAX;
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static const char intel[] = "ntel";
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static const char amd[] = "cAMD";
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if (ECX == get32bitAsBE(amd)) {
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if (isEqualStr(EBX, ECX, EDX, "AuthenticAMD")) {
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type_ |= tAMD;
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getCpuid(0x80000001, data);
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if (EDX & (1U << 31)) {
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@ -514,8 +579,7 @@ public:
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// Long mode implies support for PREFETCHW on AMD
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type_ |= tPREFETCHW;
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}
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}
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if (ECX == get32bitAsBE(intel)) {
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} else if (isEqualStr(EBX, ECX, EDX, "GenuineIntel")) {
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type_ |= tINTEL;
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}
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