mirror of https://github.com/PCSX2/pcsx2.git
IPU: ARM64 compatibility
This commit is contained in:
Stenzek
Connor McLaughlin
parent
4e0e8cef54
commit
7d098674f2
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@ -1374,6 +1374,7 @@ __fi static bool mpeg2_slice()
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//Cr bias - 8 * 8
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//Cb bias - 8 * 8
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#if defined(_M_X86)
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__m128i zeroreg = _mm_setzero_si128();
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for (uint i = 0; i < (256+64+64) / 32; ++i)
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@ -1388,6 +1389,24 @@ __fi static bool mpeg2_slice()
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s += 32;
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d += 32;
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}
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#elif defined(_M_ARM64)
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uint8x16_t zeroreg = vmovq_n_u8(0);
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for (uint i = 0; i < (256 + 64 + 64) / 32; ++i)
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{
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//*d++ = *s++;
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uint8x16_t woot1 = vld1q_u8((uint8_t*)s);
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uint8x16_t woot2 = vld1q_u8((uint8_t*)s + 16);
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vst1q_u8((uint8_t*)d, vzip1q_u8(woot1, zeroreg));
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vst1q_u8((uint8_t*)d + 16, vzip2q_u8(woot1, zeroreg));
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vst1q_u8((uint8_t*)d + 32, vzip1q_u8(woot2, zeroreg));
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vst1q_u8((uint8_t*)d + 48, vzip2q_u8(woot2, zeroreg));
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s += 32;
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d += 32;
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}
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#else
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#error Unsupported arch
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#endif
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}
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}
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else
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@ -11,11 +11,18 @@
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MULTI_ISA_UNSHARED_START
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void ipu_dither_reference(const macroblock_rgb32 &rgb32, macroblock_rgb16 &rgb16, int dte);
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#if defined(_M_X86)
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void ipu_dither_sse2(const macroblock_rgb32 &rgb32, macroblock_rgb16 &rgb16, int dte);
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#endif
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__ri void ipu_dither(const macroblock_rgb32 &rgb32, macroblock_rgb16 &rgb16, int dte)
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{
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#if defined(_M_X86)
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ipu_dither_sse2(rgb32, rgb16, dte);
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#else
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ipu_dither_reference(rgb32, rgb16, dte);
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#endif
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}
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__ri void ipu_dither_reference(const macroblock_rgb32 &rgb32, macroblock_rgb16 &rgb16, int dte)
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@ -53,6 +60,8 @@ __ri void ipu_dither_reference(const macroblock_rgb32 &rgb32, macroblock_rgb16 &
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}
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}
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#if defined(_M_X86)
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__ri void ipu_dither_sse2(const macroblock_rgb32 &rgb32, macroblock_rgb16 &rgb16, int dte)
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{
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const __m128i alpha_test = _mm_set1_epi16(0x40);
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@ -110,4 +119,6 @@ __ri void ipu_dither_sse2(const macroblock_rgb32 &rgb32, macroblock_rgb16 &rgb16
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}
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}
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#endif
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MULTI_ISA_UNSHARED_END
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@ -168,7 +168,7 @@ static constexpr VLC_ALIGNED16 MVtab MV_10[] = {
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static constexpr DMVtab DMV_2[] = {
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{0, 1}, {0, 1}, {1, 2}, {-1, 2}};
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{0, 1}, {0, 1}, {1, 2}, {(s8)-1, 2}};
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static constexpr VLC_ALIGNED16 CBPtab CBP_7[] = {
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@ -42,6 +42,8 @@ void yuv2rgb_reference(void)
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}
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}
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#if defined(_M_X86)
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// Suikoden Tactics FMV speed results: Reference - ~72fps, SSE2 - ~120fps
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// An AVX2 version is only slightly faster than an SSE2 version (+2-3fps)
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// (or I'm a poor optimiser), though it might be worth attempting again
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@ -134,4 +136,121 @@ __ri void yuv2rgb_sse2()
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}
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}
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#elif defined(_M_ARM64)
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#if defined(_MSC_VER) && !defined(__clang__)
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#include <arm64_neon.h>
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#else
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#include <arm_neon.h>
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#endif
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#define MULHI16(a, b) vshrq_n_s16(vqdmulhq_s16((a), (b)), 1)
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__ri void yuv2rgb_neon()
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{
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const int8x16_t c_bias = vdupq_n_s8(s8(IPU_C_BIAS));
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const uint8x16_t y_bias = vdupq_n_u8(IPU_Y_BIAS);
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const int16x8_t y_mask = vdupq_n_s16(s16(0xFF00));
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// Specifying round off instead of round down as everywhere else
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// implies that this is right
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const int16x8_t round_1bit = vdupq_n_s16(0x0001);
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;
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const int16x8_t y_coefficient = vdupq_n_s16(s16(IPU_Y_COEFF << 2));
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const int16x8_t gcr_coefficient = vdupq_n_s16(s16(u16(IPU_GCR_COEFF) << 2));
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const int16x8_t gcb_coefficient = vdupq_n_s16(s16(u16(IPU_GCB_COEFF) << 2));
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const int16x8_t rcr_coefficient = vdupq_n_s16(s16(IPU_RCR_COEFF << 2));
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const int16x8_t bcb_coefficient = vdupq_n_s16(s16(IPU_BCB_COEFF << 2));
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// Alpha set to 0x80 here. The threshold stuff is done later.
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const uint8x16_t alpha = vreinterpretq_u8_s8(c_bias);
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for (int n = 0; n < 8; ++n)
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{
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// could skip the loadl_epi64 but most SSE instructions require 128-bit
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// alignment so two versions would be needed.
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int8x16_t cb = vcombine_s8(vld1_s8(reinterpret_cast<s8*>(&decoder.mb8.Cb[n][0])), vdup_n_s8(0));
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int8x16_t cr = vcombine_s8(vld1_s8(reinterpret_cast<s8*>(&decoder.mb8.Cr[n][0])), vdup_n_s8(0));
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// (Cb - 128) << 8, (Cr - 128) << 8
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cb = veorq_s8(cb, c_bias);
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cr = veorq_s8(cr, c_bias);
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cb = vzip1q_s8(vdupq_n_s8(0), cb);
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cr = vzip1q_s8(vdupq_n_s8(0), cr);
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int16x8_t rc = MULHI16(vreinterpretq_s16_s8(cr), rcr_coefficient);
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int16x8_t gc = vqaddq_s16(MULHI16(vreinterpretq_s16_s8(cr), gcr_coefficient), MULHI16(vreinterpretq_s16_s8(cb), gcb_coefficient));
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int16x8_t bc = MULHI16(vreinterpretq_s16_s8(cb), bcb_coefficient);
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for (int m = 0; m < 2; ++m)
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{
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uint8x16_t y = vld1q_u8(&decoder.mb8.Y[n * 2 + m][0]);
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y = vqsubq_u8(y, y_bias);
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// Y << 8 for pixels 0, 2, 4, 6, 8, 10, 12, 14
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int16x8_t y_even = vshlq_n_s16(vreinterpretq_s16_u8(y), 8);
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// Y << 8 for pixels 1, 3, 5, 7 ,9, 11, 13, 15
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int16x8_t y_odd = vandq_s16(vreinterpretq_s16_u8(y), y_mask);
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// y_even = _mm_mulhi_epu16(y_even, y_coefficient);
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// y_odd = _mm_mulhi_epu16(y_odd, y_coefficient);
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uint16x4_t a3210 = vget_low_u16(vreinterpretq_u16_s16(y_even));
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uint16x4_t b3210 = vget_low_u16(vreinterpretq_u16_s16(y_coefficient));
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uint32x4_t ab3210 = vmull_u16(a3210, b3210);
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uint32x4_t ab7654 = vmull_high_u16(vreinterpretq_u16_s16(y_even), vreinterpretq_u16_s16(y_coefficient));
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y_even = vreinterpretq_s16_u16(vuzp2q_u16(vreinterpretq_u16_u32(ab3210), vreinterpretq_u16_u32(ab7654)));
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a3210 = vget_low_u16(vreinterpretq_u16_s16(y_odd));
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b3210 = vget_low_u16(vreinterpretq_u16_s16(y_coefficient));
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ab3210 = vmull_u16(a3210, b3210);
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ab7654 = vmull_high_u16(vreinterpretq_u16_s16(y_odd), vreinterpretq_u16_s16(y_coefficient));
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y_odd = vreinterpretq_s16_u16(vuzp2q_u16(vreinterpretq_u16_u32(ab3210), vreinterpretq_u16_u32(ab7654)));
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int16x8_t r_even = vqaddq_s16(rc, y_even);
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int16x8_t r_odd = vqaddq_s16(rc, y_odd);
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int16x8_t g_even = vqaddq_s16(gc, y_even);
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int16x8_t g_odd = vqaddq_s16(gc, y_odd);
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int16x8_t b_even = vqaddq_s16(bc, y_even);
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int16x8_t b_odd = vqaddq_s16(bc, y_odd);
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// round
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r_even = vshrq_n_s16(vaddq_s16(r_even, round_1bit), 1);
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r_odd = vshrq_n_s16(vaddq_s16(r_odd, round_1bit), 1);
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g_even = vshrq_n_s16(vaddq_s16(g_even, round_1bit), 1);
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g_odd = vshrq_n_s16(vaddq_s16(g_odd, round_1bit), 1);
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b_even = vshrq_n_s16(vaddq_s16(b_even, round_1bit), 1);
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b_odd = vshrq_n_s16(vaddq_s16(b_odd, round_1bit), 1);
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// combine even and odd bytes in original order
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uint8x16_t r = vcombine_u8(vqmovun_s16(r_even), vqmovun_s16(r_odd));
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uint8x16_t g = vcombine_u8(vqmovun_s16(g_even), vqmovun_s16(g_odd));
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uint8x16_t b = vcombine_u8(vqmovun_s16(b_even), vqmovun_s16(b_odd));
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r = vzip1q_u8(r, vreinterpretq_u8_u64(vdupq_laneq_u64(vreinterpretq_u64_u8(r), 1)));
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g = vzip1q_u8(g, vreinterpretq_u8_u64(vdupq_laneq_u64(vreinterpretq_u64_u8(g), 1)));
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b = vzip1q_u8(b, vreinterpretq_u8_u64(vdupq_laneq_u64(vreinterpretq_u64_u8(b), 1)));
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// Create RGBA (we could generate A here, but we don't) quads
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uint8x16_t rg_l = vzip1q_u8(r, g);
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uint8x16_t ba_l = vzip1q_u8(b, alpha);
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uint16x8_t rgba_ll = vzip1q_u16(vreinterpretq_u16_u8(rg_l), vreinterpretq_u16_u8(ba_l));
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uint16x8_t rgba_lh = vzip2q_u16(vreinterpretq_u16_u8(rg_l), vreinterpretq_u16_u8(ba_l));
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uint8x16_t rg_h = vzip2q_u8(r, g);
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uint8x16_t ba_h = vzip2q_u8(b, alpha);
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uint16x8_t rgba_hl = vzip1q_u16(vreinterpretq_u16_u8(rg_h), vreinterpretq_u16_u8(ba_h));
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uint16x8_t rgba_hh = vzip2q_u16(vreinterpretq_u16_u8(rg_h), vreinterpretq_u16_u8(ba_h));
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vst1q_u8(reinterpret_cast<u8*>(&decoder.rgb32.c[n * 2 + m][0]), vreinterpretq_u8_u16(rgba_ll));
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vst1q_u8(reinterpret_cast<u8*>(&decoder.rgb32.c[n * 2 + m][4]), vreinterpretq_u8_u16(rgba_lh));
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vst1q_u8(reinterpret_cast<u8*>(&decoder.rgb32.c[n * 2 + m][8]), vreinterpretq_u8_u16(rgba_hl));
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vst1q_u8(reinterpret_cast<u8*>(&decoder.rgb32.c[n * 2 + m][12]), vreinterpretq_u8_u16(rgba_hh));
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}
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}
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}
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#undef MULHI16
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#endif
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MULTI_ISA_UNSHARED_END
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@ -7,5 +7,14 @@
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MULTI_ISA_DEF(extern void yuv2rgb_reference();)
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#if defined(_M_X86)
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#define yuv2rgb yuv2rgb_sse2
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MULTI_ISA_DEF(extern void yuv2rgb_sse2();)
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#elif defined(_M_ARM64)
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#define yuv2rgb yuv2rgb_neon
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MULTI_ISA_DEF(extern void yuv2rgb_neon();)
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#endif
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