mirror of https://github.com/PCSX2/pcsx2.git
Finished mVU macro, and set it on by default.
Basically this means whenever COP2 recs are used, its calling mVU instructions instead of sVU instructions. Note: Theres a very-minor incompatibility problem when using interpreters/sVU for VU0 with mVU Macro. But I'll fix it later (and it probably doesn't effect much). git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1710 96395faa-99c1-11dd-bbfe-3dabce05a288
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@ -61,7 +61,7 @@ extern SessionOverrideFlags g_Session;
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#define CHECK_MULTIGS (Config.Options&PCSX2_GSMULTITHREAD)
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#define CHECK_MICROVU0 (Config.Options&PCSX2_MICROVU0)
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#define CHECK_MICROVU1 (Config.Options&PCSX2_MICROVU1)
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//#define CHECK_MACROVU0 // ifndef = Use sVU for VU macro, ifdef = Use mVU for VU macro
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#define CHECK_MACROVU0 // ifndef = Use sVU for VU macro, ifdef = Use mVU for VU macro
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#define CHECK_EEREC (!g_Session.ForceDisableEErec && Config.Options&PCSX2_EEREC)
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#define CHECK_VU0REC (!g_Session.ForceDisableVU0rec && Config.Options&PCSX2_VU0REC)
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#define CHECK_VU1REC (!g_Session.ForceDisableVU1rec && (Config.Options&PCSX2_VU1REC))
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@ -77,13 +77,37 @@ microVUt(void) mVUallocSFLAGc(int reg, int regT, int fInstance) {
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OR32RtoR(reg, regT);
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}
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// Denormalizes Status Flag
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microVUt(void) mVUallocSFLAGd(uptr memAddr, bool setAllflags) {
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MOV32MtoR(gprF0, memAddr);
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MOV32RtoR(gprF1, gprF0);
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SHR32ItoR(gprF1, 3);
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AND32ItoR(gprF1, 0x18);
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MOV32RtoR(gprF2, gprF0);
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SHL32ItoR(gprF2, 11);
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AND32ItoR(gprF2, 0x1800);
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OR32RtoR (gprF1, gprF2);
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SHL32ItoR(gprF0, 14);
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AND32ItoR(gprF0, 0x3cf0000);
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OR32RtoR (gprF1, gprF0);
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if (setAllflags) {
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MOV32RtoR(gprF0, gprF1);
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MOV32RtoR(gprF2, gprF1);
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MOV32RtoR(gprF3, gprF1);
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}
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}
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microVUt(void) mVUallocMFLAGa(mV, int reg, int fInstance) {
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MOVZX32M16toR(reg, (uptr)&mVU->macFlag[fInstance]);
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}
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microVUt(void) mVUallocMFLAGb(mV, int reg, int fInstance) {
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//AND32ItoR(reg, 0xffff);
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MOV32RtoM((uptr)&mVU->macFlag[fInstance], reg);
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if (fInstance < 4) MOV32RtoM((uptr)&mVU->macFlag[fInstance], reg); // microVU
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else MOV32RtoM((uptr)&mVU->regs->VI[REG_MAC_FLAG].UL, reg); // macroVU
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}
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microVUt(void) mVUallocCFLAGa(mV, int reg, int fInstance) {
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@ -59,8 +59,13 @@ microVUt(void) mVUendProgram(mV, microFlagCycles* mFC, int isEbit) {
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}
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// Save Flag Instances
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#ifdef CHECK_MACROVU0
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getFlagReg(fStatus, fStatus);
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MOV32RtoM((uptr)&mVU->regs->VI[REG_STATUS_FLAG].UL, fStatus);
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#else
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mVUallocSFLAGc(gprT1, gprT2, fStatus);
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MOV32RtoM((uptr)&mVU->regs->VI[REG_STATUS_FLAG].UL, gprT1);
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#endif
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mVUallocMFLAGa(mVU, gprT1, fMac);
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mVUallocCFLAGa(mVU, gprT2, fClip);
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MOV32RtoM((uptr)&mVU->regs->VI[REG_MAC_FLAG].UL, gprT1);
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@ -40,24 +40,15 @@ void mVUdispatcherA(mV) {
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SSE_LDMXCSR((uptr)&g_sseVUMXCSR);
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// Load Regs
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#ifdef CHECK_MACROVU0
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MOV32MtoR(gprF0, (uptr)&mVU->regs->VI[REG_STATUS_FLAG].UL);
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MOV32RtoR(gprF1, gprF0);
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SHR32ItoR(gprF1, 3);
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AND32ItoR(gprF1, 0x18);
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MOV32RtoR(gprF2, gprF0);
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SHL32ItoR(gprF2, 11);
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AND32ItoR(gprF2, 0x1800);
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OR32RtoR (gprF1, gprF2);
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SHL32ItoR(gprF0, 14);
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AND32ItoR(gprF0, 0x3cf0000);
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OR32RtoR (gprF1, gprF0);
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MOV32RtoR(gprF0, gprF1);
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MOV32RtoR(gprF2, gprF1);
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MOV32RtoR(gprF3, gprF1);
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MOV32RtoR(gprF3, gprF0);
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#else
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mVUallocSFLAGd((uptr)&mVU->regs->VI[REG_STATUS_FLAG].UL, 1);
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#endif
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SSE_MOVAPS_M128_to_XMM(xmmT1, (uptr)&mVU->regs->VI[REG_MAC_FLAG].UL);
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SSE_SHUFPS_XMM_to_XMM (xmmT1, xmmT1, 0);
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SSE_MOVAPS_XMM_to_M128((uptr)mVU->macFlag, xmmT1);
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@ -41,19 +41,31 @@ void setupMacroOp(int mode, const char* opName) {
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memset(µVU0.prog.IRinfo.info[0], 0, sizeof(microVU0.prog.IRinfo.info[0]));
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iFlushCall(FLUSH_EVERYTHING);
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microVU0.regAlloc->reset();
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if (mode & 1) { // Q-Reg will be Read
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if (mode & 0x01) { // Q-Reg will be Read
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SSE_MOVSS_M32_to_XMM(xmmPQ, (uptr)µVU0.regs->VI[REG_Q].UL);
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}
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if (mode & 8) { // Clip Instruction
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if (mode & 0x08) { // Clip Instruction
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microVU0.prog.IRinfo.info[0].cFlag.write = 0xff;
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microVU0.prog.IRinfo.info[0].cFlag.lastWrite = 0xff;
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}
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if (mode & 0x10) { // Update Status/Mac Flags
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microVU0.prog.IRinfo.info[0].sFlag.doFlag = 1;
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microVU0.prog.IRinfo.info[0].sFlag.doNonSticky = 1;
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microVU0.prog.IRinfo.info[0].sFlag.write = 0;
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microVU0.prog.IRinfo.info[0].sFlag.lastWrite = 0;
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microVU0.prog.IRinfo.info[0].mFlag.doFlag = 1;
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microVU0.prog.IRinfo.info[0].mFlag.write = 0xff;
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MOV32MtoR(gprF0, (uptr)µVU0.regs->VI[REG_STATUS_FLAG].UL);
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}
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}
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void endMacroOp(int mode) {
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if (mode & 2) { // Q-Reg was Written To
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if (mode & 0x02) { // Q-Reg was Written To
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SSE_MOVSS_XMM_to_M32((uptr)µVU0.regs->VI[REG_Q].UL, xmmPQ);
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}
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if (mode & 0x10) { // Status/Mac Flags were Updated
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MOV32RtoM((uptr)µVU0.regs->VI[REG_STATUS_FLAG].UL, gprF0);
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}
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microVU0.regAlloc->flushAll();
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}
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@ -261,10 +273,16 @@ static void recCFC2() {
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if (!_Rt_) return;
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iFlushCall(FLUSH_EVERYTHING);
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MOV32MtoR(EAX, (uptr)µVU0.regs->VI[_Rd_].UL);
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if (_Rd_ == REG_STATUS_FLAG) { // Normalize Status Flag
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MOV32MtoR(gprF0, (uptr)µVU0.regs->VI[REG_STATUS_FLAG].UL);
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mVUallocSFLAGc(EAX, gprF0, 0);
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}
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else MOV32MtoR(EAX, (uptr)µVU0.regs->VI[_Rd_].UL);
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// FixMe: Should R-Reg have upper 9 bits 0?
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MOV32RtoM((uptr)&cpuRegs.GPR.r[_Rt_].UL[0], EAX);
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if( _Rd_ >= 16 ) {
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if (_Rd_ >= 16) {
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CDQ(); // Sign Extend
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MOV32RtoM ((uptr)&cpuRegs.GPR.r[_Rt_].UL[1], EDX);
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}
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@ -289,7 +307,14 @@ static void recCTC2() {
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OR32ItoR (EAX, 0x3f800000);
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MOV32RtoM((uptr)µVU0.regs->VI[REG_R].UL, EAX);
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break;
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case REG_CMSAR1: // REG_CMSAR1
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case REG_STATUS_FLAG:
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if (_Rt_) { // Denormalizes flag into gprF1
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mVUallocSFLAGd((uptr)&cpuRegs.GPR.r[_Rt_].UL[0], 0);
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MOV32RtoM((uptr)µVU0.regs->VI[_Rd_].UL, gprF1);
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}
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else MOV32ItoM((uptr)µVU0.regs->VI[_Rd_].UL, 0);
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break;
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case REG_CMSAR1:
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if (_Rt_) {
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MOV32MtoR(EAX, (uptr)&cpuRegs.GPR.r[_Rt_].UL[0]);
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PUSH32R(EAX);
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