mirror of https://github.com/PCSX2/pcsx2.git
A commit for review, there's some unclear counters code. Also added a more precise NTSC vsync rate.
git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@326 a6443dda-0b58-4228-96e9-037be469359c
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@ -158,7 +158,7 @@ extern TESTRUNARGS g_TestRun;
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HBlank 15.73426573 KHz */
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HBlank 15.73426573 KHz */
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//VBlanks per second
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//VBlanks per second
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#define VBLANK_NTSC ((Config.PsxType & 2) ? 59.94 : 59.82)
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#define VBLANK_NTSC ((Config.PsxType & 2) ? 59.94005994 : 59.82)
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#define VBLANK_PAL ((Config.PsxType & 2) ? 50.00 : 49.76)
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#define VBLANK_PAL ((Config.PsxType & 2) ? 50.00 : 49.76)
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//HBlanks per second
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//HBlanks per second
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@ -168,10 +168,10 @@ extern TESTRUNARGS g_TestRun;
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//VBlank timers for EE, bit more accurate.
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//VBlank timers for EE, bit more accurate.
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#define VBLANKCNT(count) ((u32)((Config.PsxType & 1) ? (VBLANKPALSELECT * count) : (VBLANKNTSCSELECT * count)))
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#define VBLANKCNT(count) ((u32)((Config.PsxType & 1) ? (VBLANKPALSELECT * count) : (VBLANKNTSCSELECT * count)))
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#define VBLANKPALSELECT ((Config.PsxType & 2) ? (PS2CLK / 50.00) : (PS2CLK / 49.76))
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#define VBLANKPALSELECT ((Config.PsxType & 2) ? (PS2CLK / 50.00) : (PS2CLK / 49.76))
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#define VBLANKNTSCSELECT ((Config.PsxType & 2) ? (PS2CLK / 59.94) : (PS2CLK / 59.82))
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#define VBLANKNTSCSELECT ((Config.PsxType & 2) ? (PS2CLK / 59.94005994) : (PS2CLK / 59.82))
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//EE VBlank speeds
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//EE VBlank speeds
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#define PS2VBLANK_NTSC_INT ((PS2CLK / 59.94))
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#define PS2VBLANK_NTSC_INT ((PS2CLK / 59.94005994))
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#define PS2VBLANK_NTSC ((PS2CLK / 59.82))
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#define PS2VBLANK_NTSC ((PS2CLK / 59.82))
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#define PS2VBLANK_PAL_INT ((PS2CLK / 50.00))
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#define PS2VBLANK_PAL_INT ((PS2CLK / 50.00))
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#define PS2VBLANK_PAL ((PS2CLK / 49.76))
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#define PS2VBLANK_PAL ((PS2CLK / 49.76))
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@ -73,13 +73,14 @@ static __forceinline void _rcntSet( int i )
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}
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}
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static __forceinline void cpuRcntSet() {
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static __forceinline void cpuRcntSet() {
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int i;
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// Calculate our target cycle deltas.
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// Calculate our target cycle deltas.
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// This must be done regardless of if the hblank/vblank counters updated since
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// This must be done regardless of if the hblank/vblank counters updated since
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// cpuRegs.cycle changes, even if sCycle hasn't!
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// cpuRegs.cycle changes, even if sCycle hasn't!
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u32 counter4CycleT = ( counters[4].mode == MODE_HBLANK ) ? HBLANK_TIME_ : HRENDER_TIME_;
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//fixme : HBLANK_TIME_ and HRENDER_TIME_ are both SCANLINE_NTSC (or _PAL) / 2.. was that intended? (rama)
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//u32 counter4CycleT = ( counters[4].mode == MODE_HBLANK ) ? HBLANK_TIME_ : HRENDER_TIME_;
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u32 counter4CycleT = HBLANK_TIME_;
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u32 counter5CycleT = VSYNC_HALF_ - (cpuRegs.cycle - counters[5].sCycle);
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u32 counter5CycleT = VSYNC_HALF_ - (cpuRegs.cycle - counters[5].sCycle);
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counter4CycleT -= (cpuRegs.cycle - counters[4].sCycle);
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counter4CycleT -= (cpuRegs.cycle - counters[4].sCycle);
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@ -87,8 +88,10 @@ static __forceinline void cpuRcntSet() {
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nextsCounter = cpuRegs.cycle;
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nextsCounter = cpuRegs.cycle;
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for (i = 0; i < 4; i++)
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_rcntSet( 0 );
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_rcntSet( i );
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_rcntSet( 1 );
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_rcntSet( 2 );
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_rcntSet( 3 );
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}
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}
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void rcntInit() {
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void rcntInit() {
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@ -35,11 +35,13 @@ typedef struct {
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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// NTSC Timing Information!!! (some scanline info is guessed)
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// NTSC Timing Information!!! (some scanline info is guessed)
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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#define SCANLINE_NTSC (u32)(PS2CLK / 15734.25)//18743
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#define SCANLINE_NTSC (u32)(PS2CLK / 15734.27)//18743
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// fixme : Both, HRENDER_TIME_NTSC and HBLANK_TIME_NTSC the same?
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// also see cpuRcntSet() and possibly hScanline() for this issue (rama)
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#define HRENDER_TIME_NTSC (u32)(SCANLINE_NTSC / 2)//15528 //time from hblank end to hblank start (PS2CLK / 18991.368423051722991900181367568)
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#define HRENDER_TIME_NTSC (u32)(SCANLINE_NTSC / 2)//15528 //time from hblank end to hblank start (PS2CLK / 18991.368423051722991900181367568)
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#define HBLANK_TIME_NTSC (u32)(SCANLINE_NTSC / 2)//3215 //time from hblank start to hblank end (PS2CLK / 91738.91105912572817760653181028)
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#define HBLANK_TIME_NTSC (u32)(SCANLINE_NTSC / 2)//3215 //time from hblank start to hblank end (PS2CLK / 91738.91105912572817760653181028)
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#define VSYNC_NTSC (u32)(PS2CLK / 59.94) //hz
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#define VSYNC_NTSC (u32)(PS2CLK / 59.94005994) //hz
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#define VSYNC_HALF_NTSC (u32)(VSYNC_NTSC / 2) //hz
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#define VSYNC_HALF_NTSC (u32)(VSYNC_NTSC / 2) //hz //should be 2460058 but rounding puts it to 2460060
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#define SCANLINES_TOTAL_NTSC 525 // total number of scanlines
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#define SCANLINES_TOTAL_NTSC 525 // total number of scanlines
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#define SCANLINES_VSYNC_NTSC 3 // scanlines that are used for syncing every half-frame
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#define SCANLINES_VSYNC_NTSC 3 // scanlines that are used for syncing every half-frame
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@ -53,6 +55,8 @@ typedef struct {
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// PAL Timing Information!!! (some scanline info is guessed)
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// PAL Timing Information!!! (some scanline info is guessed)
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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#define SCANLINE_PAL (u32)(PS2CLK / 15625)//18874
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#define SCANLINE_PAL (u32)(PS2CLK / 15625)//18874
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// fixme : Both, HRENDER_TIME_PAL and HBLANK_TIME_PAL the same?
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// also see cpuRcntSet() and possibly hScanline() for this issue (rama)
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#define HRENDER_TIME_PAL (u32)(SCANLINE_PAL / 2)//15335 //time from hblank end to hblank start
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#define HRENDER_TIME_PAL (u32)(SCANLINE_PAL / 2)//15335 //time from hblank end to hblank start
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#define HBLANK_TIME_PAL (u32)(SCANLINE_PAL / 2)//3539 //time from hblank start to hblank end
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#define HBLANK_TIME_PAL (u32)(SCANLINE_PAL / 2)//3539 //time from hblank start to hblank end
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#define VSYNC_PAL (u32)(PS2CLK / 50) //hz
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#define VSYNC_PAL (u32)(PS2CLK / 50) //hz
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@ -123,8 +123,8 @@ typedef struct {
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int Hacks;
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int Hacks;
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int GameFixes;
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int GameFixes;
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int CustomFrameSkip;
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int CustomFrameSkip;
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int CustomConsecutiveFrames;
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u8 CustomConsecutiveFrames;
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int CustomConsecutiveSkip;
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u8 CustomConsecutiveSkip;
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u32 sseMXCSR;
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u32 sseMXCSR;
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u32 sseVUMXCSR;
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u32 sseVUMXCSR;
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} PcsxConfig;
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} PcsxConfig;
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