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IPU (linux): 

* fix asm constraint. X86 have only 6 registers...
* move some pointer to ecx and edx like windows asm


git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3590 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
gregory.hainaut 2010-08-02 12:49:48 +00:00
parent 76cc1bcd37
commit 7b05db1351
1 changed files with 7 additions and 5 deletions
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12
pcsx2/IPU/yuv2rgb.cpp
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@ -263,7 +263,6 @@ ihatemsvc:
__asm__ __volatile__ ( __asm__ __volatile__ (
".intel_syntax noprefix\n" ".intel_syntax noprefix\n"
"mov eax, 1\n"
"xor esi, esi\n" "xor esi, esi\n"
"xor edi, edi\n" "xor edi, edi\n"
@ -382,8 +381,9 @@ ihatemsvc:
"add edi, 16\n" "add edi, 16\n"
"neg eax\n" // run twice the onerow <=> edi = 16 or 48 or 80 etc... <=> check bit 5
"jl onerow\n" // run twice "test edi, 16\n"
"jnz onerow\n"
"add esi, 8\n" "add esi, 8\n"
"cmp esi, 64\n" "cmp esi, 64\n"
@ -393,9 +393,11 @@ ihatemsvc:
:[C_BIAS]"i"(C_BIAS), [Y_BIAS]"i"(Y_BIAS), [Y_MASK]"i"(Y_MASK), :[C_BIAS]"i"(C_BIAS), [Y_BIAS]"i"(Y_BIAS), [Y_MASK]"i"(Y_MASK),
[ROUND_1BIT]"i"(ROUND_1BIT), [Y_COEFF]"i"(Y_COEFF), [GCr_COEFF]"i"(GCr_COEFF), [ROUND_1BIT]"i"(ROUND_1BIT), [Y_COEFF]"i"(Y_COEFF), [GCr_COEFF]"i"(GCr_COEFF),
[GCb_COEFF]"i"(GCb_COEFF), [RCr_COEFF]"i"(RCr_COEFF), [BCb_COEFF]"i"(BCb_COEFF), [GCb_COEFF]"i"(GCb_COEFF), [RCr_COEFF]"i"(RCr_COEFF), [BCb_COEFF]"i"(BCb_COEFF),
[yuv2rgb_temp]"r"(yuv2rgb_temp), [sse2_tables]"r"(sse2_tableoffset), // Use ecx and edx as base pointers, to allow for Mod/RM form on memOps.
// This saves 2-3 bytes per instruction where these are used. :)
[yuv2rgb_temp]"c"(yuv2rgb_temp), [sse2_tables]"d"(sse2_tableoffset),
[mb8]"r"(mb8), [rgb32]"r"(rgb32) [mb8]"r"(mb8), [rgb32]"r"(rgb32)
: "eax", "esi", "edi", "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "memory" : "esi", "edi", "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "memory"
); );
#else #else
# error Unsupported compiler # error Unsupported compiler