From 78520b9a24982b16fec099c34ae90caec7177960 Mon Sep 17 00:00:00 2001 From: arcum42 Date: Fri, 20 Mar 2009 01:26:38 +0000 Subject: [PATCH] Get rid of some duplicated code in cpuException... git-svn-id: http://pcsx2.googlecode.com/svn/trunk@823 96395faa-99c1-11dd-bbfe-3dabce05a288 --- pcsx2/R3000A.h | 12 ++-- pcsx2/R5900.cpp | 162 ++++++++++++++++++------------------------------ pcsx2/R5900.h | 3 - 3 files changed, 67 insertions(+), 110 deletions(-) diff --git a/pcsx2/R3000A.h b/pcsx2/R3000A.h index 41cb4862a5..7ab13663e8 100644 --- a/pcsx2/R3000A.h +++ b/pcsx2/R3000A.h @@ -127,13 +127,13 @@ extern s32 psxCycleEE; // tracks IOP's current sych status with the EE #ifndef _PC_ #define _i32(x) (s32)x -#define _u32(x) x +#define _u32(x) (u32)x -#define _i16(x) (short)x -#define _u16(x) (unsigned short)x +#define _i16(x) (s16)x +#define _u16(x) (u16)x -#define _i8(x) (char)x -#define _u8(x) (unsigned char)x +#define _i8(x) (s8)x +#define _u8(x) (u8)x /**** R3000A Instruction Macros ****/ #define _PC_ psxRegs.pc // The next PC to be executed @@ -143,7 +143,7 @@ extern s32 psxCycleEE; // tracks IOP's current sych status with the EE #define _Rt_ ((psxRegs.code >> 16) & 0x1F) // The rt part of the instruction register #define _Rs_ ((psxRegs.code >> 21) & 0x1F) // The rs part of the instruction register #define _Sa_ ((psxRegs.code >> 6) & 0x1F) // The sa part of the instruction register -#define _Im_ ((unsigned short)psxRegs.code) // The immediate part of the instruction register +#define _Im_ ((u16)psxRegs.code) // The immediate part of the instruction register #define _Target_ (psxRegs.code & 0x03ffffff) // The target part of the instruction register #define _Imm_ ((short)psxRegs.code) // sign-extended immediate diff --git a/pcsx2/R5900.cpp b/pcsx2/R5900.cpp index b7e179f542..c39b5c632d 100644 --- a/pcsx2/R5900.cpp +++ b/pcsx2/R5900.cpp @@ -91,7 +91,7 @@ void cpuReset() hwReset(); vif0Reset(); - vif1Reset(); + vif1Reset(); rcntInit(); psxReset(); } @@ -109,79 +109,83 @@ void cpuShutdown() void cpuException(u32 code, u32 bd) { cpuRegs.branch = 0; // Tells the interpreter that an exception occurred during a branch. - + bool errLevel2, checkStatus; u32 offset; cpuRegs.CP0.n.Cause = code & 0xffff; - if(cpuRegs.CP0.n.Status.b.ERL == 0){ //Error Level 0-1 - if(((code & 0x7C) >= 0x8) && ((code & 0x7C) <= 0xC)) offset = 0x0; //TLB Refill - else if ((code & 0x7C) == 0x0) offset = 0x200; //Interrupt - else offset = 0x180; // Everything else + if(cpuRegs.CP0.n.Status.b.ERL == 0) + { + //Error Level 0-1 + errLevel2 = FALSE; + checkStatus = (cpuRegs.CP0.n.Status.b.BEV == 0); // for TLB/general exceptions + + if (((code & 0x7C) >= 0x8) && ((code & 0x7C) <= 0xC)) + offset = 0x0; //TLB Refill + else if ((code & 0x7C) == 0x0) + offset = 0x200; //Interrupt + else + offset = 0x180; // Everything else + } + else + { + //Error Level 2 + errLevel2 = TRUE; + checkStatus = (cpuRegs.CP0.n.Status.b.DEV == 0); // for perf/debug exceptions - - if (cpuRegs.CP0.n.Status.b.EXL == 0) { - cpuRegs.CP0.n.Status.b.EXL = 1; - if (bd) { - Console::Notice("branch delay!!"); - cpuRegs.CP0.n.EPC = cpuRegs.pc - 4; - cpuRegs.CP0.n.Cause |= 0x80000000; - } else { - cpuRegs.CP0.n.EPC = cpuRegs.pc; - cpuRegs.CP0.n.Cause &= ~0x80000000; - } - } else { - offset = 0x180; //Overrride the cause - //Console::Notice("cpuException: Status.EXL = 1 cause %x", params code); - } - if (cpuRegs.CP0.n.Status.b.BEV == 0) { - cpuRegs.pc = 0x80000000 + offset; - } else { - cpuRegs.pc = 0xBFC00200 + offset; - } - } else { //Error Level 2 Console::Error("*PCSX2* FIX ME: Level 2 cpuException"); - if((code & 0x38000) <= 0x8000 ) { //Reset / NMI + if ((code & 0x38000) <= 0x8000 ) + { + //Reset / NMI cpuRegs.pc = 0xBFC00000; Console::Notice("Reset request"); UpdateCP0Status(); return; - } else if((code & 0x38000) == 0x10000) offset = 0x80; //Performance Counter - else if((code & 0x38000) == 0x18000) offset = 0x100; //Debug - else Console::Error("Unknown Level 2 Exception!! Cause %x", params code); - - if (cpuRegs.CP0.n.Status.b.EXL == 0) { - cpuRegs.CP0.n.Status.b.EXL = 1; - if (bd) { - Console::Notice("branch delay!!"); - cpuRegs.CP0.n.EPC = cpuRegs.pc - 4; - cpuRegs.CP0.n.Cause |= 0x80000000; - } else { - cpuRegs.CP0.n.EPC = cpuRegs.pc; - cpuRegs.CP0.n.Cause &= ~0x80000000; - } - } else { - offset = 0x180; //Overrride the cause - Console::Notice("cpuException: Status.EXL = 1 cause %x", params code); - } - - if (cpuRegs.CP0.n.Status.b.DEV == 0) { - cpuRegs.pc = 0x80000000 + offset; - } else { - cpuRegs.pc = 0xBFC00200 + offset; - } + } + else if((code & 0x38000) == 0x10000) + offset = 0x80; //Performance Counter + else if((code & 0x38000) == 0x18000) + offset = 0x100; //Debug + else + Console::Error("Unknown Level 2 Exception!! Cause %x", params code); } + + if (cpuRegs.CP0.n.Status.b.EXL == 0) + { + cpuRegs.CP0.n.Status.b.EXL = 1; + if (bd) + { + Console::Notice("branch delay!!"); + cpuRegs.CP0.n.EPC = cpuRegs.pc - 4; + cpuRegs.CP0.n.Cause |= 0x80000000; + } + else + { + cpuRegs.CP0.n.EPC = cpuRegs.pc; + cpuRegs.CP0.n.Cause &= ~0x80000000; + } + } + else + { + offset = 0x180; //Override the cause + if (errLevel2) Console::Notice("cpuException: Status.EXL = 1 cause %x", params code); + } + + if (checkStatus) + cpuRegs.pc = 0x80000000 + offset; + else + cpuRegs.pc = 0xBFC00200 + offset; + UpdateCP0Status(); } -void cpuTlbMiss(u32 addr, u32 bd, u32 excode) { +void cpuTlbMiss(u32 addr, u32 bd, u32 excode) +{ Console::Error("cpuTlbMiss pc:%x, cycl:%x, addr: %x, status=%x, code=%x", params cpuRegs.pc, cpuRegs.cycle, addr, cpuRegs.CP0.n.Status.val, excode); - if (bd) { - Console::Notice("branch delay!!"); - } + if (bd) Console::Notice("branch delay!!"); - assert(0); // temporary + assert(0); // temporary cpuRegs.CP0.n.BadVAddr = addr; cpuRegs.CP0.n.Context &= 0xFF80000F; @@ -212,50 +216,6 @@ void cpuTlbMissW(u32 addr, u32 bd) { cpuTlbMiss(addr, bd, EXC_CODE_TLBS); } -void JumpCheckSym(u32 addr, u32 pc) { -#if 0 -// if (addr == 0x80051770) { SysPrintf("Log!: %s\n", PSM(cpuRegs.GPR.n.a0.UL[0])); Log=1; varLog|= 0x40000000; } - if (addr == 0x8002f150) { SysPrintf("printk: %s\n", PSM(cpuRegs.GPR.n.a0.UL[0])); } - if (addr == 0x8002aba0) return; - if (addr == 0x8002f450) return; - if (addr == 0x800dd520) return; -// if (addr == 0x80049300) SysPrintf("register_blkdev: %x\n", cpuRegs.GPR.n.a0.UL[0]); - if (addr == 0x8013cb70) { SysPrintf("change_root: %x\n", cpuRegs.GPR.n.a0.UL[0]); } -// if (addr == 0x8013d1e8) { SysPrintf("Log!\n"); Log++; if (Log==2) exit(0); varLog|= 0x40000000; } -// if (addr == 0x00234e88) { SysPrintf("StoreImage\n"); Log=1; /*psMu32(0x234e88) = 0x03e00008; psMu32(0x234e8c) = 0;*/ } -#endif -/* if ((pc >= 0x00131D50 && - pc < 0x00132454) || - (pc >= 0x00786a90 && - pc < 0x00786ac8))*/ - /*if (varLog & 0x40000000) { - char *str; - char *strf; - - str = disR5900GetSym(addr); - if (str != NULL) { - strf = disR5900GetUpperSym(pc); - if (strf) { - SysPrintf("Func %8.8x: %s (called by %8.8x: %s)\n", addr, str, pc, strf); - } else { - SysPrintf("Func %8.8x: %s (called by %x)\n", addr, str, pc); - } - if (!strcmp(str, "printf")) { SysPrintf("%s\n", (char*)PSM(cpuRegs.GPR.n.a0.UL[0])); } - if (!strcmp(str, "printk")) { SysPrintf("%s\n", (char*)PSM(cpuRegs.GPR.n.a0.UL[0])); } - } - }*/ -} - -void JumpCheckSymRet(u32 addr) { - /*if (varLog & 0x40000000) { - char *str; - str = disR5900GetUpperSym(addr); - if (str != NULL) { - SysPrintf("Return : %s, v0=%8.8x\n", str, cpuRegs.GPR.n.v0.UL[0]); - } - }*/ -} - __forceinline void _cpuTestMissingINTC() { if (cpuRegs.CP0.n.Status.val & 0x400 && psHu32(INTC_STAT) & psHu32(INTC_MASK)) { diff --git a/pcsx2/R5900.h b/pcsx2/R5900.h index 900142b2ea..8dbd6cda4c 100644 --- a/pcsx2/R5900.h +++ b/pcsx2/R5900.h @@ -219,9 +219,6 @@ struct tlbs #endif -void JumpCheckSym(u32 addr, u32 pc); -void JumpCheckSymRet(u32 addr); - PCSX2_ALIGNED16_EXTERN(cpuRegisters cpuRegs); PCSX2_ALIGNED16_EXTERN(fpuRegisters fpuRegs); PCSX2_ALIGNED16_EXTERN(tlbs tlb[48]);