mirror of https://github.com/PCSX2/pcsx2.git
Remove deprecated jASSUME from pcsx2 core. It is still used in some plugins
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1facc8efbc
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@ -68,7 +68,7 @@ void rcntReset(int index) {
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static __fi void _rcntSet( int cntidx )
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{
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s32 c;
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jASSUME( cntidx <= 4 ); // rcntSet isn't valid for h/vsync counters.
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pxAssume( cntidx <= 4 ); // rcntSet isn't valid for h/vsync counters.
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const Counter& counter = counters[cntidx];
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@ -542,7 +542,7 @@ __fi void psxRcntWmode16( int index, u32 value )
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{
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PSXCNT_LOG( "IOP Counter[%d] writeMode = 0x%04X", index, value );
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jASSUME( index >= 0 && index < 3 );
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pxAssume( index >= 0 && index < 3 );
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psxCounter& counter = psxCounters[index];
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counter.mode = value;
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@ -603,7 +603,7 @@ __fi void psxRcntWmode32( int index, u32 value )
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{
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PSXCNT_LOG( "IOP Counter[%d] writeMode = 0x%04x", index, value );
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jASSUME( index >= 3 && index < 6 );
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pxAssume( index >= 3 && index < 6 );
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psxCounter& counter = psxCounters[index];
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counter.mode = value;
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@ -261,7 +261,7 @@ __fi void cpuSetEvent()
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__fi void cpuClearInt( uint i )
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{
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jASSUME( i < 32 );
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pxAssume( i < 32 );
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cpuRegs.interrupt &= ~(1 << i);
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}
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@ -29,7 +29,7 @@ using namespace Internal;
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mem8_t __fastcall iopHwRead8_Page1( u32 addr )
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{
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// all addresses are assumed to be prefixed with 0x1f801xxx:
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jASSUME( (addr >> 12) == 0x1f801 );
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pxAssume( (addr >> 12) == 0x1f801 );
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u32 masked_addr = addr & 0x0fff;
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@ -81,7 +81,7 @@ mem8_t __fastcall iopHwRead8_Page1( u32 addr )
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mem8_t __fastcall iopHwRead8_Page3( u32 addr )
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{
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// all addresses are assumed to be prefixed with 0x1f803xxx:
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jASSUME( (addr >> 12) == 0x1f803 );
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pxAssume( (addr >> 12) == 0x1f803 );
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mem8_t ret;
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if( addr == 0x1f803100 ) // PS/EE/IOP conf related
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@ -98,7 +98,7 @@ mem8_t __fastcall iopHwRead8_Page3( u32 addr )
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mem8_t __fastcall iopHwRead8_Page8( u32 addr )
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{
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// all addresses are assumed to be prefixed with 0x1f808xxx:
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jASSUME( (addr >> 12) == 0x1f808 );
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pxAssume( (addr >> 12) == 0x1f808 );
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mem8_t ret;
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@ -117,10 +117,10 @@ template< typename T >
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static __fi T _HwRead_16or32_Page1( u32 addr )
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{
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// all addresses are assumed to be prefixed with 0x1f801xxx:
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jASSUME( (addr >> 12) == 0x1f801 );
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pxAssume( (addr >> 12) == 0x1f801 );
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// all addresses should be aligned to the data operand size:
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jASSUME(
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pxAssume(
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( sizeof(T) == 2 && (addr & 1) == 0 ) ||
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( sizeof(T) == 4 && (addr & 3) == 0 )
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);
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@ -385,7 +385,7 @@ mem16_t __fastcall iopHwRead16_Page1( u32 addr )
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mem16_t __fastcall iopHwRead16_Page3( u32 addr )
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{
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// all addresses are assumed to be prefixed with 0x1f803xxx:
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jASSUME( (addr >> 12) == 0x1f803 );
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pxAssume( (addr >> 12) == 0x1f803 );
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mem16_t ret = psxHu16(addr);
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IopHwTraceLog<mem16_t>( addr, ret, true );
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@ -397,7 +397,7 @@ mem16_t __fastcall iopHwRead16_Page3( u32 addr )
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mem16_t __fastcall iopHwRead16_Page8( u32 addr )
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{
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// all addresses are assumed to be prefixed with 0x1f808xxx:
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jASSUME( (addr >> 12) == 0x1f808 );
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pxAssume( (addr >> 12) == 0x1f808 );
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mem16_t ret = psxHu16(addr);
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IopHwTraceLog<mem16_t>( addr, ret, true );
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@ -416,7 +416,7 @@ mem32_t __fastcall iopHwRead32_Page1( u32 addr )
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mem32_t __fastcall iopHwRead32_Page3( u32 addr )
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{
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// all addresses are assumed to be prefixed with 0x1f803xxx:
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jASSUME( (addr >> 12) == 0x1f803 );
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pxAssume( (addr >> 12) == 0x1f803 );
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const mem32_t ret = psxHu32(addr);
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IopHwTraceLog<mem32_t>( addr, ret, true );
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return ret;
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@ -427,7 +427,7 @@ mem32_t __fastcall iopHwRead32_Page3( u32 addr )
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mem32_t __fastcall iopHwRead32_Page8( u32 addr )
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{
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// all addresses are assumed to be prefixed with 0x1f808xxx:
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jASSUME( (addr >> 12) == 0x1f808 );
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pxAssume( (addr >> 12) == 0x1f808 );
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u32 masked_addr = addr & 0x0fff;
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mem32_t ret;
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@ -105,7 +105,7 @@ void SetFastMemory(int bSetFast)
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//
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void recLoad64( u32 bits, bool sign )
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{
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jASSUME( bits == 64 || bits == 128 );
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pxAssume( bits == 64 || bits == 128 );
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// Load EDX with the destination.
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// 64/128 bit modes load the result directly into the cpuRegs.GPR struct.
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@ -147,7 +147,7 @@ void recLoad64( u32 bits, bool sign )
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//
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void recLoad32( u32 bits, bool sign )
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{
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jASSUME( bits <= 32 );
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pxAssume( bits <= 32 );
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// 8/16/32 bit modes return the loaded value in EAX.
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@ -339,7 +339,7 @@ void vtlb_dynarec_init()
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// Dynarec Load Implementations
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void vtlb_DynGenRead64(u32 bits)
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{
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jASSUME( bits == 64 || bits == 128 );
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pxAssume( bits == 64 || bits == 128 );
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uptr* writeback = DynGen_PrepRegs();
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@ -355,7 +355,7 @@ void vtlb_DynGenRead64(u32 bits)
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// Returns read value in eax.
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void vtlb_DynGenRead32(u32 bits, bool sign)
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{
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jASSUME( bits <= 32 );
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pxAssume( bits <= 32 );
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uptr* writeback = DynGen_PrepRegs();
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@ -204,7 +204,7 @@ using namespace std;
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#include "assert.h"
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#define __forceinline __inline__ __attribute__((always_inline,unused))
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// #define __forceinline __inline__ __attribute__((__always_inline__,__gnu_inline__))
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#define __assume(c) ((void)0)
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#define __assume(c) if (!(c)) __builtin_unreachable()
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#endif
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@ -32,25 +32,10 @@
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#define CALLBACK __stdcall
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#endif
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// jASSUME - give hints to the optimizer
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// This is primarily useful for the default case switch optimizer, which enables VC to
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// generate more compact switches.
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#ifdef NDEBUG
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# define jBREAKPOINT() ((void) 0)
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# ifdef _MSC_VER
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# define jASSUME(exp) (__assume(exp))
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# else
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# define jASSUME(exp) ((void) sizeof(exp))
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# endif
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#ifdef _MSC_VER
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#define UNREACHABLE_CODE __assume(0)
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#else
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# if defined(_MSC_VER)
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# define jBREAKPOINT() do { __asm int 3 } while(0)
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# else
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# define jBREAKPOINT() ((void) *(volatile char *) 0)
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# endif
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# define jASSUME(exp) if(exp) ; else jBREAKPOINT()
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#define UNREACHABLE_CODE __builtin_unreachable()
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#endif
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// disable the default case in a switch
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@ -59,7 +44,7 @@
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break; \
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\
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default: \
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jASSUME(0); \
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UNREACHABLE_CODE; \
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break; \
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}
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