mirror of https://github.com/PCSX2/pcsx2.git
microVU: Work in progress stuff... (no functional change)
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1540 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
cottonvibes
parent
4a7304d6f7
commit
73d388fc87
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@ -758,3 +758,244 @@ microVUt(void) mVUallocVIb(mV, int GPRreg, int _reg_) {
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if (!_reg_ && (_fxf_ < 3)) { XOR32RtoR(GPRreg, GPRreg); } \
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else { MOV32MtoR(GPRreg, (uptr)&mVU->regs->VF[_reg_].UL[0]); } \
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}
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//------------------------------------------------------------------
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// Reg Alloc
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//------------------------------------------------------------------
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struct microXMM {
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int reg; // VF Reg Number Stored
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int xyzw; // xyzw to write back
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int count; // Count of when first cached
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bool isNeeded; // Is needed for current instruction
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bool isTemp; // Is Temp Reg
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};
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#define xmmTotal 6 // Don't allocate PQ/ACC?
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class microRegAlloc {
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private:
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microXMM xmmReg[xmmTotal];
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VURegs* vuRegs;
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int counter;
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void clearReg(int reg) {
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xmmReg[reg].reg = 0;
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xmmReg[reg].count = 0;
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xmmReg[reg].isNeeded = 0;
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xmmReg[reg].isTemp = 1;
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}
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int findFreeRegRec(int startIdx) {
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for (int i = startIdx; i < xmmTotal; i++) {
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if (!xmmReg[i].isNeeded) {
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if ((i+1) >= xmmTotal) return i;
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int x = findFreeRegRec(i+1);
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if (x == -1) return i;
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return ((xmmReg[i].count < xmmReg[x].count) ? i : x);
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}
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}
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return -1;
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}
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int findFreeReg() {
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for (int i = 0; i < xmmTotal; i++) {
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if (!xmmReg[i].isNeeded && xmmReg[i].isTemp) {
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return i; // Reg is not needed and was a temp reg
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}
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}
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int x = findFreeRegRec(0);
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if (x < 0) { DevCon::Error("microVU Allocation Error!"); return 0; }
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return x;
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}
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public:
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microRegAlloc(VURegs* vuRegsPtr) {
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vuRegs = vuRegsPtr;
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reset();
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}
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void reset() {
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for (int i = 0; i < xmmTotal; i++) {
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clearReg(i);
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}
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counter = 0;
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}
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void writeBackReg(int reg) {
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if (xmmReg[reg].reg && xmmReg[reg].xyzw) {
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mVUsaveReg(reg, (uptr)&vuRegs->VF[xmmReg[reg].reg].UL[0], xmmReg[reg].xyzw, 1);
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for (int i = 0; i < xmmTotal; i++) {
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if (i = reg) continue;
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if (!xmmReg[i].isTemp && xmmReg[i].reg == xmmReg[reg].reg) {
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clearReg(i); // Invalidate any Cached Regs
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}
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}
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if (xmmReg[reg].xyzw == 0xf) { // Make Cached Reg
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xmmReg[reg].count = counter;
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xmmReg[reg].xyzw = 0;
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xmmReg[reg].isNeeded = 0;
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xmmReg[reg].isTemp = 0;
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return;
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}
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}
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clearReg(reg); // Clear Written Back Reg
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}
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void clearNeeded(int reg) {
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xmmReg[reg].isNeeded = 0;
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}
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int allocReg(int vfReg = -1, bool writeBack = 0, int xyzw = 0, int vfWriteBack = 0) {
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counter++;
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for (int i = 0; i < xmmTotal; i++) {
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if ((vfReg >= 0) && (!xmmReg[i].isTemp) && (xmmReg[i].reg == vfReg)) {
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if (writeBack) {
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int z = findFreeReg();
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writeBackReg(z);
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if (xyzw == 8) SSE2_SHUFPD_XMM_to_XMM(z, i, 0);
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else if (xyzw == 4) SSE2_SHUFPD_XMM_to_XMM(z, i, 1);
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else if (xyzw == 2) SSE2_SHUFPD_XMM_to_XMM(z, i, 2);
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else if (xyzw == 1) SSE2_SHUFPD_XMM_to_XMM(z, i, 3);
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else if (z != i) SSE_MOVAPS_XMM_to_XMM (z, i);
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xmmReg[z].reg = vfWriteBack;
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xmmReg[z].count = counter;
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xmmReg[z].xyzw = xyzw;
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xmmReg[z].isNeeded = 1;
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xmmReg[z].isTemp = 1;
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return z;
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}
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xmmReg[i].isNeeded = 1;
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return i;
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}
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}
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int x = findFreeReg();
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writeBackReg(x);
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if (vfReg >= 0) {
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if (writeBack) {
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mVUloadReg(x, (uptr)&vuRegs->VF[vfReg].UL[0], xyzw);
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xmmReg[x].reg = vfWriteBack;
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xmmReg[x].count = counter;
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xmmReg[x].xyzw = xyzw;
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xmmReg[x].isNeeded = 1;
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xmmReg[x].isTemp = 1;
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}
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else {
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SSE_MOVAPS_M128_to_XMM((uptr)&vuRegs->VF[vfReg].UL[0], x);
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xmmReg[x].reg = vfReg;
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xmmReg[x].count = counter;
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xmmReg[x].xyzw = 0;
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xmmReg[x].isNeeded = 1;
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xmmReg[x].isTemp = 0;
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}
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}
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else { // Is Temp Reg
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xmmReg[x].reg = 0;
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xmmReg[x].count = counter;
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xmmReg[x].xyzw = 0;
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xmmReg[x].isNeeded = 1;
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xmmReg[x].isTemp = 1;
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}
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return x;
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}
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};
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/*
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struct microXMM {
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int reg; // VF Reg Number Stored
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int xyzw; // Current xyzw Order
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int validXYZW; // Vectors that are valid
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bool isNeeded; // Is needed for current instruction
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bool isTemp; // Is Temp Reg
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bool isWritten; // The reg has been written to
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};
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#define xmmTotal 7 // Don't allocate Last XMM Reg for PQ instances (will change this later)
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class microRegAlloc {
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private:
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microXMM xmmReg[xmmTotal];
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VURegs* vuRegs;
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int vfStats[32];
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int findFreeReg(int startIdx) {
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for (int i = startIdx; i < xmmTotal; i++) {
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if (!xmmReg[i].isNeeded && xmmReg[i].isTemp) {
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return i; // Reg is not needed and was a temp reg
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}
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}
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for (int i = startIdx; i < xmmTotal; i++) {
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if (!xmmReg[i].isNeeded) {
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if ((i+1) >= xmmTotal) return i;
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int x = findFreeReg(i+1);
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if (x == -1) return i;
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return ((vfStats[xmmReg[i].reg] < vfStats[xmmReg[x].reg]) ? i : x);
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}
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}
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return -1;
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}
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public:
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microRegAlloc(VURegs* vuRegsPtr) {
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vuRegs = vuRegsPtr;
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reset();
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}
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void reset() {
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for (int i = 0; i < xmmTotal; i++) {
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xmmReg[i].reg = 0;
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xmmReg[i].isNeeded = 0;
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xmmReg[i].isTemp = 1;
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}
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}
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void loadStats(int* vfRegData) {
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for (int i = 0; i < 32; i++) {
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vfStats[i] = vfRegData[i];
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}
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}
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void changeXYZW(int reg, int newXYZW) {
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if (xmmReg[reg].xyzw != newXYZW) {
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int shuffleReg = 0;
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int xyzw = xmmReg[reg].xyzw;
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if (((xyzw >> 6) & 3) == ((newXYZW >> 0) & 3)) shuffleReg |= (3<<0);
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else if (((xyzw >> 4) & 3) == ((newXYZW >> 0) & 3)) shuffleReg |= (2<<0);
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else if (((xyzw >> 2) & 3) == ((newXYZW >> 0) & 3)) shuffleReg |= (1<<0);
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if (((xyzw >> 6) & 3) == ((newXYZW >> 2) & 3)) shuffleReg |= (3<<2);
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else if (((xyzw >> 4) & 3) == ((newXYZW >> 2) & 3)) shuffleReg |= (2<<2);
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else if (((xyzw >> 2) & 3) == ((newXYZW >> 2) & 3)) shuffleReg |= (1<<2);
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if (((xyzw >> 6) & 3) == ((newXYZW >> 4) & 3)) shuffleReg |= (3<<4);
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else if (((xyzw >> 4) & 3) == ((newXYZW >> 4) & 3)) shuffleReg |= (2<<4);
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else if (((xyzw >> 2) & 3) == ((newXYZW >> 4) & 3)) shuffleReg |= (1<<4);
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if (((xyzw >> 6) & 3) == ((newXYZW >> 6) & 3)) shuffleReg |= (3<<6);
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else if (((xyzw >> 4) & 3) == ((newXYZW >> 6) & 3)) shuffleReg |= (2<<6);
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else if (((xyzw >> 2) & 3) == ((newXYZW >> 6) & 3)) shuffleReg |= (1<<6);
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SSE2_PSHUFD_XMM_to_XMM(reg, reg, shuffleReg);
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}
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}
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int writeBack(int reg) {
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if (!xmmReg[reg].isTemp && xmmReg[reg].reg && xmmReg[reg].isWritten) {
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changeXYZW(reg, 0xe4);
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SSE_MOVAPS_XMM_to_M128(reg, (uptr)&vuRegs->VF[xmmReg[reg].reg].UL[0]); // Write Back Reg to Mem
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}
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}
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int allocReg(int vfReg, bool cache, int xyzw, int vfWriteBack) {
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for (int i = 0; i < xmmTotal; i++) {
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if (!xmmReg[i].isTemp && xmmReg[i].reg == vfReg) {
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if ((xmmReg[i].validXYZW != 0xf) && xmmReg[i].isWritten) {
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// write back partial reg
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//if (!forWriting) { get reg from mem }
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}
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xmmReg[i].isWritten |= (forWriting) ? 1 : 0;
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xmmReg[i].isNeeded = 1;
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return i;
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}
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}
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int x = findFreeReg(0);
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if (!xmmReg[x].isTemp && xmmReg[x].reg && xmmReg[x].isWritten) {
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changeXYZW(x, 0xe4);
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SSE_MOVAPS_XMM_to_M128(x, (uptr)&vuRegs->VF[xmmReg[x].reg].UL[0]); // Write Back Reg to Mem
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}
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if (vfReg != -1) {
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SSE_MOVAPS_M128_to_XMM((uptr)&vuRegs->VF[xmmReg[x].reg].UL[0], x); // Load Reg from Mem
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xmmReg[x].isNeeded = 1;
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xmmReg[x].isTemp = 0;
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xmmReg[x].xyzw = 0xe4;
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}
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else { // Is Temp Reg
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xmmReg[x].isNeeded = 1;
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xmmReg[x].isTemp = 1;
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}
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return x;
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}
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};
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*/
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@ -512,8 +512,8 @@ microVUr(void*) mVUcompile(microVU* mVU, u32 startPC, uptr pState) {
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// Check if branch-block has already been compiled
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blockCreate(branchAddr/8);
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pBlock = mVUblocks[branchAddr/8]->search((microRegInfo*)&mVUregs);
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if (pBlock) { xJMP( pBlock->x86ptrStart ); }
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else { mVUblockFetch(mVU, branchAddr, (uptr)&mVUregs); }
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if (pBlock) { xJMP( pBlock->x86ptrStart ); }
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else { mVUblockFetch(mVU, branchAddr, (uptr)&mVUregs); }
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}
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else {
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uptr jumpAddr;
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@ -238,7 +238,7 @@ mVUop(mVULowerOP_T3_11) { doTableStuff(mVULowerOP_T3_11_OPCODE, ((mVUgetCode >>
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mVUop(mVUopU) { doTableStuff(mVU_UPPER_OPCODE, (mVUgetCode & 0x3f)); } // Gets Upper Opcode
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mVUop(mVUopL) { doTableStuff(mVULOWER_OPCODE, (mVUgetCode >> 25)); } // Gets Lower Opcode
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mVUop(mVUunknown) {
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pass2 { SysPrintf("microVU%d: Unknown Micro VU opcode called (%x)\n", getIndex, mVUgetCode); }
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pass2 { SysPrintf("microVU%d: Unknown Micro VU opcode called (%x) [%04x]\n", getIndex, mVUgetCode, xPC); }
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pass3 { mVUlog("Unknown", mVUgetCode); }
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}
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