mirror of https://github.com/PCSX2/pcsx2.git
SPU2: Set sample rate correctly for PS1 mode (#3532)
* Moved ps1 init. Added Sample Rate change for SPU that gets set but not applied * SPU: misc fixes on SPU ps1 mode init * Init the soundbuffer to apply sample rate. Actually set the correct sample rate for the ps1 though it still won't apply Co-authored-by: Gauvain 'GovanifY' Roussel-Tarbouriech <gauvain@govanify.com> Co-authored-by: kenshen112 <obarrtimothy@gmail.com>
This commit is contained in:
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@ -30,6 +30,8 @@
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**/x64/Debug*
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**/x64/Debug*
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**/x64/Devel*
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**/x64/Devel*
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**/bin/PCSX2-linux.sh
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_ReSharper.*
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_ReSharper.*
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pcsx2.snapshot_*
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pcsx2.snapshot_*
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svnrev.h
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svnrev.h
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@ -63,6 +65,7 @@ oprofile_data/
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# Visual Studio upgrades
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# Visual Studio upgrades
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/Backup*
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/Backup*
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/UpgradeLog*.htm
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/UpgradeLog*.htm
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/.vscode*
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/bin/**/*.dll
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/bin/**/*.dll
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/bin/**/*.exp
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/bin/**/*.exp
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@ -112,3 +115,4 @@ oprofile_data/
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/pcsx2/windows/VCprojects/GSdx_opengl_debug_hw.txt
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/pcsx2/windows/VCprojects/GSdx_opengl_debug_hw.txt
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/pcsx2/windows/VCprojects/GSdx_opengl_debug_sw.txt
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/pcsx2/windows/VCprojects/GSdx_opengl_debug_sw.txt
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/out/build/x64-Debug (default)
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@ -263,6 +263,7 @@ void CALLBACK SPU2setSettingsDir(const char *dir);
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void CALLBACK SPU2setLogDir(const char *dir);
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void CALLBACK SPU2setLogDir(const char *dir);
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void CALLBACK SPU2reset();
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void CALLBACK SPU2reset();
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void CALLBACK SPU2ps1reset();
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void CALLBACK SPU2write(u32 mem, u16 value);
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void CALLBACK SPU2write(u32 mem, u16 value);
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u16 CALLBACK SPU2read(u32 mem);
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u16 CALLBACK SPU2read(u32 mem);
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@ -432,6 +433,7 @@ typedef void(CALLBACK *_PADWriteEvent)(keyEvent &evt);
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// SPU2
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// SPU2
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typedef s32(CALLBACK *_SPU2open)(void *pDsp);
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typedef s32(CALLBACK *_SPU2open)(void *pDsp);
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typedef void(CALLBACK *_SPU2reset)();
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typedef void(CALLBACK *_SPU2reset)();
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typedef void (CALLBACK *_SPU2ps1reset)();
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typedef void(CALLBACK *_SPU2write)(u32 mem, u16 value);
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typedef void(CALLBACK *_SPU2write)(u32 mem, u16 value);
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typedef u16(CALLBACK *_SPU2read)(u32 mem);
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typedef u16(CALLBACK *_SPU2read)(u32 mem);
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typedef void(CALLBACK *_SPU2readDMA4Mem)(u16 *pMem, int size);
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typedef void(CALLBACK *_SPU2readDMA4Mem)(u16 *pMem, int size);
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@ -536,6 +538,7 @@ extern _PADWriteEvent PADWriteEvent;
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#ifndef BUILTIN_SPU2_PLUGIN
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#ifndef BUILTIN_SPU2_PLUGIN
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extern _SPU2open SPU2open;
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extern _SPU2open SPU2open;
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extern _SPU2reset SPU2reset;
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extern _SPU2reset SPU2reset;
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extern _SPU2ps1reset SPU2ps1reset;
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extern _SPU2write SPU2write;
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extern _SPU2write SPU2write;
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extern _SPU2read SPU2read;
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extern _SPU2read SPU2read;
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@ -1473,24 +1473,24 @@ static __fi void cdvdWrite0F(u8 rt)
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static __fi void cdvdWrite14(u8 rt)
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static __fi void cdvdWrite14(u8 rt)
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{ // PS1 MODE?? // This should be done in the SBUS_F240 bit 19 write in HwWrite.cpp
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{ // PS1 MODE?? // This should be done in the SBUS_F240 bit 19 write in HwWrite.cpp
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u32 cycle = psxRegs.cycle;
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//u32 cycle = psxRegs.cycle;
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if (rt == 0xFE)
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//if (rt == 0xFE)
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Console.Warning("*PCSX2*: go PS1 mode DISC SPEED = FAST");
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//Console.Warning("*PCSX2*: go PS1 mode DISC SPEED = FAST");
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else
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//else
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Console.Warning("*PCSX2*: go PS1 mode DISC SPEED = %dX", rt);
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//Console.Warning("*PCSX2*: go PS1 mode DISC SPEED = %dX", rt);
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psxReset();
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//psxReset();
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PSXCLK = 33868800;
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//PSXCLK = 33868800;
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setPsxSpeed();
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//setPsxSpeed();
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// psxmode: todo: we should recalculate video timings for iop and ee. how to do that best?
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// psxmode: todo: we should recalculate video timings for iop and ee. how to do that best?
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// unlike regular ps2 games, the video mode for ps1driver isn't going through the GS set mode syscall
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// unlike regular ps2 games, the video mode for ps1driver isn't going through the GS set mode syscall
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// so.. something like this? :
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// so.. something like this? :
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//gsSetVideoMode(GS_VideoMode::NTSC);
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//gsSetVideoMode(GS_VideoMode::NTSC);
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//gsSetVideoMode(GS_VideoMode::DVD_NTSC);
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//gsSetVideoMode(GS_VideoMode::DVD_NTSC);
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psxHu32(0x1f801450) = 0x8;
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//psxHu32(0x1f801450) = 0x8;
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psxHu32(0x1f801078) = 1;
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//psxHu32(0x1f801078) = 1;
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psxRegs.cycle = cycle;
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//psxRegs.cycle = cycle;
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}
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}
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static __fi void fail_pol_cal()
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static __fi void fail_pol_cal()
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@ -2175,9 +2175,9 @@ void cdvdWrite(u8 key, u8 rt)
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case 0x0F:
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case 0x0F:
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cdvdWrite0F(rt);
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cdvdWrite0F(rt);
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break;
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break;
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case 0x14:
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//case 0x14:
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cdvdWrite14(rt);
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// cdvdWrite14(rt);
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break;
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// break;
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case 0x16:
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case 0x16:
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cdvdWrite16(rt);
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cdvdWrite16(rt);
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break;
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break;
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@ -20,6 +20,7 @@
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#include "newVif.h"
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#include "newVif.h"
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#include "IPU/IPUdma.h"
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#include "IPU/IPUdma.h"
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#include "Gif_Unit.h"
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#include "Gif_Unit.h"
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#include "IopCommon.h"
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using namespace R5900;
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using namespace R5900;
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@ -63,6 +64,11 @@ void hwReset()
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psHu32(DMAC_ENABLEW) = 0x1201;
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psHu32(DMAC_ENABLEW) = 0x1201;
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psHu32(DMAC_ENABLER) = 0x1201;
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psHu32(DMAC_ENABLER) = 0x1201;
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if ((psxHu32(HW_ICFG) & (1 << 3)))
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{
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SPU2ps1reset();
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}
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SPU2reset();
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SPU2reset();
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sifReset();
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sifReset();
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return;
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return;
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mcase(SBUS_F240) :
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mcase(SBUS_F240) :
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//if (value & (1 << 19)) // switch hardware into psx mode. Doesn't work for some reason, still needs this to be in cdvdWrite14?
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if (value & (1 << 19))
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//{
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{
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// u32 cycle = psxRegs.cycle;
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u32 cycle = psxRegs.cycle;
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// //pgifInit();
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//pgifInit();
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// psxHwReset();
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psxReset();
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// psxHu32(0x1f801450) = 0x8;
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PSXCLK = 33868800;
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// psxHu32(0x1f801078) = 1;
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SPU2ps1reset();
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// psxRegs.cycle = cycle;
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setPsxSpeed();
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//}
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psxHu32(0x1f801450) = 0x8;
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psxHu32(0x1f801078) = 1;
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psxRegs.cycle = cycle;
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}
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if(!(value & 0x100))
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if(!(value & 0x100))
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psHu32(mem) &= ~0x100;
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psHu32(mem) &= ~0x100;
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else
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else
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@ -279,6 +279,7 @@ static void PAD_update( u32 padslot ) { }
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_SPU2open SPU2open;
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_SPU2open SPU2open;
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_SPU2write SPU2write;
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_SPU2write SPU2write;
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_SPU2reset SPU2reset;
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_SPU2reset SPU2reset;
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_SPU2ps1reset SPU2ps1reset;
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_SPU2read SPU2read;
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_SPU2read SPU2read;
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_SPU2readDMA4Mem SPU2readDMA4Mem;
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_SPU2readDMA4Mem SPU2readDMA4Mem;
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@ -451,6 +452,7 @@ static const LegacyApi_ReqMethod s_MethMessReq_SPU2[] =
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{
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{
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{ "SPU2open", (vMeth**)&SPU2open, NULL },
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{ "SPU2open", (vMeth**)&SPU2open, NULL },
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{ "SPU2reset", (vMeth**)&SPU2reset, SPU2_Reset },
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{ "SPU2reset", (vMeth**)&SPU2reset, SPU2_Reset },
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{ "SPU2ps1reset", (vMeth**)&SPU2ps1reset, SPU2ps1reset},
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{ "SPU2write", (vMeth**)&SPU2write, NULL },
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{ "SPU2write", (vMeth**)&SPU2write, NULL },
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{ "SPU2read", (vMeth**)&SPU2read, NULL },
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{ "SPU2read", (vMeth**)&SPU2read, NULL },
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{ "SPU2readDMA4Mem", (vMeth**)&SPU2readDMA4Mem, NULL },
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{ "SPU2readDMA4Mem", (vMeth**)&SPU2readDMA4Mem, NULL },
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} else if (addr == PGPU_DAT_FIFO) { //reverse write - mind the direction set by reg f380
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} else if (addr == PGPU_DAT_FIFO) { //reverse write - mind the direction set by reg f380
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//PGpuDataReg = data;
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//PGpuDataReg = data;
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ringBufPut(&pgifDatRbC, &data);
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ringBufPut(&pgifDatRbC, &data);
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// Console.WriteLn( "\n\r PGIF REVERSE !!! DATA write 0x%08X = 0x%08X IF_CTRL= %08X PGPU_STAT= %08X CmdCnt 0x%X \n\r", addr, data, getUpdPgifCtrlReg(), getUpdPgpuStatReg(), pgifCmdRbC.count);
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// Console.WriteLn( "\n\r PGIF REVERSE !!! DATA write 0x%08X = 0x%08X IF_CTRL= %08X PGPU_STAT= %08X CmdCnt 0x%X \n\r", addr, data, getUpdPgifCtrlReg(), getUpdPgpuStatReg(), pgifCmdRbC.count);
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drainPgpuDmaNrToIop();
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drainPgpuDmaNrToIop();
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} else if (addr == PGPU_STAT) {
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} else if (addr == PGPU_STAT) {
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PGpuStatReg = data; //Should all bits be writable?
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PGpuStatReg = data; //Should all bits be writable?
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*/
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*/
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void pgifInit(void);
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void pgifInit(void);
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void pgifReset(void);
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extern void psxGPUw(int, u32);
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extern void psxGPUw(int, u32);
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extern u32 psxGPUr(int);
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extern u32 psxGPUr(int);
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// PCSX2 expects ASNI, not unicode, so this MUST always be char...
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// PCSX2 expects ASNI, not unicode, so this MUST always be char...
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static char libraryName[256];
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static char libraryName[256];
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int SampleRate = 48000;
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static bool IsOpened = false;
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static bool IsOpened = false;
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static bool IsInitialized = false;
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static bool IsInitialized = false;
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Cores[1].DoDMAwrite(pMem, size);
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Cores[1].DoDMAwrite(pMem, size);
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}
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}
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EXPORT_C_(void)
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EXPORT_C_(s32)
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SPU2reset()
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SPU2reset()
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{
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{
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SampleRate = 48000;
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if (SndBuffer::Test() != 0)
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{
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SndBuffer::Cleanup();
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}
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memset(spu2regs, 0, 0x010000);
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memset(spu2regs, 0, 0x010000);
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memset(_spu2mem, 0, 0x200000);
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memset(_spu2mem, 0, 0x200000);
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memset(_spu2mem + 0x2800, 7, 0x10); // from BIOS reversal. Locks the voices so they don't run free.
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memset(_spu2mem + 0x2800, 7, 0x10); // from BIOS reversal. Locks the voices so they don't run free.
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Cores[0].Init(0);
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Cores[0].Init(0);
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Cores[1].Init(1);
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Cores[1].Init(1);
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try {
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SndBuffer::Init();
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} catch (std::exception &ex) {
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fprintf(stderr, "SPU2-X Error: Could not initialize device, or something.\nReason: %s", ex.what());
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SPU2close();
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return -1;
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}
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return 0;
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}
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EXPORT_C_(s32)
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SPU2ps1reset()
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{
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SampleRate = 44100;
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if (SndBuffer::Test() != 0)
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{
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SndBuffer::Cleanup();
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}
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printf("RESET PS1 \n");
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memset(spu2regs, 0, 0x010000);
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memset(_spu2mem, 0, 0x200000);
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memset(_spu2mem + 0x2800, 7, 0x10); // from BIOS reversal. Locks the voices so they don't run free.
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// Reset the cores to actually apply the sample rate. Beware, thar be dragons in here.
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/*Cores[0].Init(0);
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Cores[1].Init(1);*/
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try {
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SndBuffer::Init();
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} catch (std::exception &ex) {
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fprintf(stderr, "SPU2-X Error: Could not initialize device, or something.\nReason: %s", ex.what());
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SPU2close();
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return -1;
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}
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return 0;
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}
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}
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EXPORT_C_(s32)
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EXPORT_C_(s32)
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EXPORT_C_(s32)
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EXPORT_C_(s32)
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SPU2init();
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SPU2init();
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EXPORT_C_(void)
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EXPORT_C_(s32)
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SPU2reset();
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SPU2reset();
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EXPORT_C_(s32)
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EXPORT_C_(s32)
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SPU2ps1reset();
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EXPORT_C_(s32)
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SPU2open(void *pDsp);
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SPU2open(void *pDsp);
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EXPORT_C_(void)
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EXPORT_C_(void)
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SPU2close();
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SPU2close();
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@ -377,6 +377,7 @@ void SndBuffer::Init()
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try {
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try {
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const float latencyMS = SndOutLatencyMS * 16;
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const float latencyMS = SndOutLatencyMS * 16;
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m_size = GetAlignedBufferSize((int)(latencyMS * SampleRate / 1000.0f));
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m_size = GetAlignedBufferSize((int)(latencyMS * SampleRate / 1000.0f));
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printf("%d SampleRate: \n", SampleRate);
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m_buffer = new StereoOut32[m_size];
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m_buffer = new StereoOut32[m_size];
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m_underrun_freeze = false;
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m_underrun_freeze = false;
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// Samplerate of the SPU2. For accurate playback we need to match this
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// Samplerate of the SPU2. For accurate playback we need to match this
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// exactly. Trying to scale samplerates and maintain SPU2's Ts timing accuracy
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// exactly. Trying to scale samplerates and maintain SPU2's Ts timing accuracy
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// is too problematic. :)
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// is too problematic. :)
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static const int SampleRate = 48000;
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extern int SampleRate;
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extern int FindOutputModuleById(const wchar_t *omodid);
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extern int FindOutputModuleById(const wchar_t *omodid);
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@ -59,3 +59,4 @@ EXPORTS
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SPU2replay = s2r_replay @30
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SPU2replay = s2r_replay @30
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SPU2reset @31
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SPU2reset @31
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SPU2ps1reset @32
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