mirror of https://github.com/PCSX2/pcsx2.git
Finish previous revert as TortoiseGit failed epicly at it.
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@ -16,7 +16,6 @@
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#include "PrecompiledHeader.h"
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#include "PrecompiledHeader.h"
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#include "Common.h"
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#include "Common.h"
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#include "Utilities/Math.h"
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namespace R5900 {
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namespace R5900 {
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namespace Interpreter {
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namespace Interpreter {
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@ -146,13 +145,30 @@ namespace MMI {
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//*****************MMI OPCODES*********************************
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//*****************MMI OPCODES*********************************
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void PLZCW() {
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static __fi void _PLZCW(int n)
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if (!_Rd_)
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{
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return;
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// This function counts the number of "like" bits in the source register, starting
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// with the MSB and working its way down, and returns the result MINUS ONE.
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// So 0xff00 would return 7, not 8.
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// Return the leading sign bits, excluding the original bit
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int c = 0;
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cpuRegs.GPR.r[_Rd_].UL[0] = count_leading_sign_bits(cpuRegs.GPR.r[_Rs_].SL[0]) - 1;
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s32 i = cpuRegs.GPR.r[_Rs_].SL[n];
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cpuRegs.GPR.r[_Rd_].UL[1] = count_leading_sign_bits(cpuRegs.GPR.r[_Rs_].SL[1]) - 1;
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// Negate the source based on the sign bit. This allows us to use a simple
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// unified bit test of the MSB for either condition.
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if( i >= 0 ) i = ~i;
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// shift first, compare, then increment. This excludes the sign bit from our final count.
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while( i <<= 1, i < 0 ) c++;
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cpuRegs.GPR.r[_Rd_].UL[n] = c;
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}
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void PLZCW() {
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if (!_Rd_) return;
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_PLZCW (0);
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_PLZCW (1);
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}
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}
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__fi void PMFHL_CLAMP(u16& dst, s32 src)
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__fi void PMFHL_CLAMP(u16& dst, s32 src)
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@ -25,7 +25,6 @@
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#include "R5900OpcodeTables.h"
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#include "R5900OpcodeTables.h"
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#include "iR5900.h"
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#include "iR5900.h"
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#include "iMMI.h"
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#include "iMMI.h"
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#include "Utilities/Math.h"
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using namespace x86Emitter;
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using namespace x86Emitter;
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@ -67,10 +66,23 @@ void recPLZCW()
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_deleteEEreg(_Rd_, 0);
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_deleteEEreg(_Rd_, 0);
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GPR_SET_CONST(_Rd_);
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GPR_SET_CONST(_Rd_);
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// Return the leading sign bits, excluding the original bit
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for(regs = 0; regs < 2; ++regs) {
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g_cpuConstRegs[_Rd_].UL[0] = count_leading_sign_bits(g_cpuConstRegs[_Rs_].SL[0]) - 1;
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u32 val = g_cpuConstRegs[_Rs_].UL[regs];
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g_cpuConstRegs[_Rd_].UL[1] = count_leading_sign_bits(g_cpuConstRegs[_Rs_].SL[1]) - 1;
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if( val != 0 ) {
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u32 setbit = val&0x80000000;
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g_cpuConstRegs[_Rd_].UL[regs] = 0;
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val <<= 1;
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while((val & 0x80000000) == setbit) {
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g_cpuConstRegs[_Rd_].UL[regs]++;
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val <<= 1;
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}
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}
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else {
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g_cpuConstRegs[_Rd_].UL[regs] = 31;
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}
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}
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return;
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return;
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}
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}
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